Chapter 2

Review of Digital Systems Design

Numbering Systems

Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number 987654, which can be represented as 9 x 100000 + 8 x 10000 + 7 x 1000 + 6 x 100 + 5 x 10 + 4 x 1 or more concisely as 9 x 105 + 8 x 104 +7 x 103 + 6 x 102 + 5 x 101 + 4 x 100

The numbers are 0, 1, 2 up to 9 since in a decimal system, the base is 10. This representation can be easily extended to fractional values as well. For example, the decimal number 99.99 can be represented as

9 x 101 + 9 x 100 + 9 x 10-1 + 9 x 10-2 In general, a number may be represented in any numbering system as dn-1 b

n-1 + dn-2 bn-2 + ….. + d1 b

1 + d0 b0 + d_1 b

-1 + d-2 b-2 + ….. + d-n-1 b-n-1 + d-n-2

b-n-2 Consider the binary number 101010.1010, whose decimal equivalent is 1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 0 x 20 + 1 x 2-1 + 0 x 2-2 + 1 x 2-3 + 0

x 2-4

= 42.625. A decimal number can be converted to a binary number by repeated division by 2 for the integer part and by repeated multiplication by 2 for the part after the decimal point.

Quotient Remainder

42 /2

21 /2 0

10 /2 1

5 /2 0

2 /2 1

1 /2 0

0 1 101010 = Integer answer

. 2x 0.625

1 2x 0.25

0 2x 0.5

1 .0

Fraction =.101

The final answer is got by putting the integer and fraction answers together as 101010.101.

Conversion of Numbers from one System to Another

Decimal Number

(Base 10)

Binary Number (Base 2)

Octal Number (Base 8)

Hexadecimal Number (Base

16) 00 0000 00 0 01 0001 01 1 02 0010 02 2 03 0011 03 3 04 0100 04 4 05 0101 05 5 06 0110 06 6 07 0111 07 7 08 1000 10 8 09 1001 11 9 10 1010 12 A 11 1011 13 B 12 1100 14 C 13 1101 15 D 14 1110 16 E 15 1111 17 F 16 10000 20 10

The following is an example of a hexadecimal number converted to a decimal number. (FEDCBA)16 = 15 x 165 + 14 X 164 + 13 x 163 + 12 X 162 + 11 x 16 + 10 = (16702650)10

Twos Complement Addition/Subtraction

Twos complement of a binary number may be evaluated by adding one to the ones complement (which is just performing bit-wise inversion) of the number.

Binary number : 10011001 Ones complement : 01100110

Twos complement : 01100111

Consider the numbers A = 10011001 and B = 01000111 in twos complement notation. Evaluate:

(a) A+B

(b) A-B

(c) B-A

(d) A-B

(e) -A-B

A = 10011001 -103

B = + 01000111 + 71

(a) A+B = Sum = 11100000 - 32

Twos complement of Sum = 00100000 - 32 A = 10011001 -103

Twos complement of B = 10111001 - 71

(b) A-B = Sum = 01010010 - 174

A = 110011001 -103

Twos complement of B = 110111001 - 71

(c) A-B = Sum = 101010010 - 174

Twos complement of Sum = 010101110 174

A = 110011001 -103

Twos complement of A = 001100111 +103

B = 01000111 + 71

(d) B-A = Sum = 010101110 +174

Twos complement of A = 001100111 +103

Twos complement of B = 110111001 - 71

(e) -A-B = Sum = 000100000 + 32

Codes

Binary and BCD codes

Decimal Number

Binary Code 8421

BCD Code

8421 8421 0 0000 0000 0000 1 0001 0000 0001 2 0010 0000 0010 3 0011 0000 0011 4 0100 0000 0100 5 0101 0000 0101

6 0110 0000 0110 7 0111 0000 0111 8 1000 0000 1000 9 1001 0000 1001 10 1010 0001 0000 11 1011 0001 0001 12 1100 0001 0010 13 1101 0001 0011 14 1110 0001 0100 15 1111 0001 0101

Gray Code

Four-bit Gray Code Sequence

Gray Code Sequence Decimal Equivalent 0000 0 0001 1 0011 3 0010 2 0110 6 0111 7 0101 5 0100 4 1100 12 1101 13 1111 15 1110 14 1010 10 1011 11 1001 9 1000 8

ASCII Code

Extended ASCII Code

Error Detection Code

1.The parity of the data 11111110 is odd since there are 7 numbers of '1' bits in the

data. The parity bit will be 1, giving the codeword 111111101.

2. The parity of the data 11111111 is even as there are 8 numbers of '1' bits. The

parity bit will be 0, giving the codeword 111111110.

3. The parity of the data 00000000 is even (zero being an even number). The parity

bit will be 0, giving the codeword 000000000.

4. A null or non-existent bitstream also has zero '1' bits and, therefore, it would get

the parity bit 0 in an even parity scheme.

Boolean Algebra

1. Commutative laws for addition and multiplication:

A + B = B + A (for addition)

A · B = B · A (for multiplication)

where A and B are two single bit variables.

2. Associative laws for addition and multiplication:

(A + B) + C= A + (B + C)

A · (B · C) = (A · B) · C

where A, B and C are single bit variables.

3. Distributive laws both for multiplication over addition and for addition over

multiplication:

A · (B + C) = (A · B) + (A · C)

A + (B · C) = (A + B) · (A + C)

The following laws are also satisfied:

4. (A+B)’ = A’B’

5. (AB)’ = A’+B’

6. A + (A · B) = A

7. A · (A + B) = A

8. A + (A’) = 1

9. A · (A’) = 0

0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 1;

0 · 0 = 0; 0 · 1 = 0; 1 · 0 = 0; 1 · 1 = 1

Verification of Commutative, Associative and Distributive laws

A B C A + B

B + A

(A + B)

+ C

A + (B + C)

A + (B · C)

(A + B) · (A + C)

A + (A · B)

A · (A + B)

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Boolean Functions using Minterms and Maxterms

Any Boolean function can be expressed as a sum of minterms or as a product of maxterms. For example, consider the function F1 formed by the sum of products of variables A, B and C:

F1 = A’B’C’ + A’BC’ + AB’C’ + ABC’ + ABC = m0 + m2 + m4 + m6 + m7 F1 may also be expressed in a short form as

F1 = Σ (0, 2, 4, 6, 7) where Σ implies sum (rather OR) of minterms.

Minterms and Maxterms for Binary Variables

Minterms Maxterms A B C Term Symbol Term Symbol 0 0 0 A’B’C’ m0 A + B + C M0 0 0 1 A’B’C m1 A + B + C’ M1 0 1 0 A’BC’ m2 A + B’ + C M2 0 1 1 A’BC m3 A + B’ + C’ M3 1 0 0 AB’C’ m4 A’ + B + C M4 1 0 1 AB’C m5 A’ + B + C’ M5 1 1 0 ABC’ m6 A’ + B’ + C M6 1 1 1 ABC m7 A’ + B’ + C’ M7

Truth Table of a Function to be Realized Using Minterms

A B C F1 0 0 0 1

0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1

1 0 1 0 1 1 0 1 1 1 1 1

Truth Table of a Function to be Realized Using Maxterms

A B C F2 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

Let us now consider the function F2’ formed by active low product of sums of variables A, B and C: F2’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) = M1·M3·M5 where M1, M3, M5 are called Max terms. In short, the function may be expressed as follows: F2’ = Π (1, 3, 5) The product symbol, Π, denotes the ANDing of maxterms. It may be noted that the function F2’ is just the complement of F1. The final result is F2, the complement of F2’ and the same as F1. Thus, one may use either the minterms or the maxterms to evaluate a function, whichever is simpler.

_________________________________________________________________________________

Logic Gates

A B F3

A B F4

F2A

F1 A Buffer

Inverter

AND

OR

F1 = A

F2 = A’

F3 = AB

F4 = A+B

GATE

SYMBOL FUNCTION

A B F5

F6

NAND

NOR A B

F5 = (AB)’

F6 = (A+B)’

Symbols and Functions of the Common Types of Gates

The Karnaugh MAP Method of Optimization of Logic Circuits

m0 m1

m2 m3

0 1AB

0

1

K Map for Two Signals A and B

C

AB

1

00 01 11 10

0 m0 m1 m3 m2 m4 m5 m7 m6

K Map for Three Signals A, B and C

AB

00 01 11 10CD

00

01

11

10

m0 m1 m3 m2 m4 m5 m7 m6

m12 m13 m15 m14 m8 m9 m11 m10

K Map for Four Signals A, B, C and D

0 0 1

F1 = A + B

0 1AB

A

B1 1 1

K Map Reduction for Two Signals using Minterms

AC’

A’BC B’C’

C 00 01

0

11 10AB

1

1 0 1 1

0 1 0 0

F2 = Σ (0, 2, 3, 5) F2 = AC’ + B’C’ + A’BC

K Map Reduction for Three Signals using Minterms CD

00 01

00

B

11

11

10

10AB

B’ (Horizontal)

01

D’ Vertical

B’D’ for the four

corners

1 1 1 1

0 1 1 0

0 1 1 0

1 1 1 1

F3 = B + B’D’ = B + D’

K Map Reduction for Four Signals using Minterms

CD 00 01

00

11

11

10

10AB

B (Horizontal)

01

D’ Vertical

B+D’ for the four

corners

F4 = B + D’

K Map Reduction for Four Signals using Maxterms

1 1 1 1

0 1 1 0

0 1 1 0

1 1 1 1

Combination Circuits Multiplexers

S1 S0 F 0 0 I0 0 1 I1 1 0 I2 1 1 I3

b Function table c Block diagram

I3 I2 I1 I0

4 - 1 MUX Inputs F

Select P

S1 S0 ins

A Four Input Multiplexer

Demultiplexer

I0

I1

I2

I3

S1

S0 F

a Logic diagram

S1’

S1’

S1’

S0’

S0’

S0’

S0

S0 S1

S1

a Block Diagram

D3 D2 D1 D0

1 - 4 Demultiplexer

S1 S0 Input 0 0 D0

S1

Input

Select Pins

S0

0 1 D1 1 0 D2 1 1 D3

b Function Table

A Four Output Demultiplexer

Decoder

D3 D2 D1 D0

BCD to Decimal Decoder

A2 BCD Inputs

A3

A0

A1

D7 D6 D5 D4

D9 D8

Active low

Decimal Outputs

BCD to Decimal Decoder

Truth Table of BCD to Decimal Decoder

Inputs Intermediate Outputs

A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1

A3' D0 = A3'A2' A1' A0' A2'

A1' A0'

A3'

A3' A2'

A1'

A0'

Logic Diagram of BCD to Decimal Decoder

Magnitude Comparator

Block Diagram of a 4-bit Magnitude Comparator

D1 = A3'A2' A1' A0 A2' A1' A0

A3 D9 = A3A2' A1' A0 A2'

A1' A0

A3

A2

A1

A0

0

1

9

E3

u2

E3 E 2u1

E3 E2

u0

E1

u3 (A < B)

E3A3 B3

E2A2 B2

E1A1 B1

E0A0 B0

4-bit Magnitude

Comparator

( A < B )

( A = B )

( A > B )

A

B

Logic Circuit Diagram of a 4-bit Magnitude Comparator

Adder/Subtractor Circuits

Half Adder Sum_HA = A’B + AB’ = A B

Truth Table of a Half Adder

A B Sum_HA 0 0 0 0 1 1

1 0 1 1 1 0

AB

Logic of a Half Adder

Full Adder

Truth Table of a Full Adder

Sum_HA = A B

S_FA = A B C

AB C

C FA = AB+BC+CA

A B

B C

C A

A B C C_FA S_FA 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Logic Realization of a Full Adder The sum and carry outputs are respectively S_FA = A B C C_FA = AB+BC+CA

Half Subtractor

Truth Table of a Half Subtractor

A B S_HS 0 0 0 0 1 1 1 0 1 1 1 0

S_HS = A’B + AB’ = A B.

S_HS = A B AB

Logic of a Half Adder

Full Subtractor

Truth Table of a Full Subtractor A B C B_FS S_FS

0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

B_FS = A’B + A’C + BC

S_FS = A’B’C + A’BC’ + ABC + AB’C’

S FS = A’B’C + A’BC’ + ABC + AB’C’

A’ B’

B FS = A’B + A’C + BC

A’ B

A’ C

B C

C

A’ B C’ A B C

A B’ C’

Logic Gate Realization of a Full Subtractor

Arithmetic Logic Unit

ALU Logic Symbol (Courtesy of Texas Instruments Inc.)

74xx181, ALU function table (Courtesy of Texas Instruments Inc.)

S0 S1 S2 S3

A0 A1 A2 A3

B0 B1 B2 B3

F0 F1 F2 F3

G P

A=B M

C_in

C-out

For Look-Ahead Carry Function Controls

Carry Inputs

ALU

A Outputs

Data Inputs

B

Carry-out

Active high data Selection

M = L: Arithmetic operations

S3 S2 S1 S0 M =H

Logic functions Cn’ = H (no carry) Cn’ = L (with carry)

L L L L F = A F = A F = A plus 1

L L L H F = A + B F = A + B F = A + B plus 1

________________________________________________________________________

_________

Programmable Logic Devices

Programmable Connects

Programmable OR Array

AND Outputs Inputs Array

a Programmable read-only memory (PROM/EPROM/Flash ROM)

Programmable Logic Devices, ROM, PLA, PAL

Read-Only Memory

Block Diagram of ROM

Each bit (b) in a word may be regarded as a Boolean function. Usually, the ROMs come with large memory sizes such as 4 KB, 8 KB, up to over 512 KB. Therefore,

ProgrammableND Array

A

OR Array Outputs Inputs

c Programmable array Logic (PAL)

Programmable Connects

Outputs Pr

Programmable Connects

ogrammableND Array

A

Programmable Connects

Programmable OR Array Inputs

b Programmable Logic array (PLA)

AN-1 | A0

W OutputsN inputs 2N x W ROM

DW-1 | D0

ROMs are usually overkill for realizing Boolean functions. However, they are quite cheap and, therefore, may be cost-effective.

Programmable Logic Array (PLA)

B’ B A A’ L L’

PLA with twelve inputs and eight outputs

Programmable Array Logic (PAL)

Graphic symbol of AND inputs of PAL

F1 = AL’ + A’B

X X

F8 = A’B + B’L

X

X

X

X X

X

X X

X

X X X X

B’ B A A’ L’ L

PAL with twelve inputs and eight outputs

Sequential Circuits

Block diagram of a sequential circuit

Inputs Next State Value(s)

Combinational circuits

Register(s)

Outputs

Clock

F1 = AL’ + A’B

X X X

F8 = A’B + B’L

X X

X X

RS Flip-Flop

RS flip-flop circuit using NOR gates

RS flip-flop circuit using NAND gates

Q

Q’

Clk

S

R

a Logic Diagram

Q

Q’

S

R

a Logic diagram

S R Q Q’ 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 1

b Truth table

(after S =1, R = 0)

(after S =0, R = 1)

S R Q Q’ 1 0 1 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 0 0

R

b Truth table

(after S =1, R = 0)

(after S =0, R = 1)

Q

Q’ S

a Logic Circuit

SR SS R Q(n) Q(n+1)

Clocked RS flip-flop

JK Flip-Flop

0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 Indeterminate 1 1 1 Indeterminate

00 01 11 10

b Characteristic Table

S Q

d Symbol

Q’ R

Clk

K Q

Q J

CP

RD

Q

RD

Q

Q(n+1) = S+R’Q

SR = 0

c Characteristic Equation

R’Q

0 0 X 1 Q

1 0 X 1 1

0

Clocked JK Flip-flop

Truth table of JK Flip-Flop

INPUTS OUTPUTS OPERATING MODE

J K Q RD CP Q

Asynchronous Reset (Clear) L X X X L H

Toggle H

h h q q Load “0” (Reset) H l h L H Load “1” (Set) H h l H L Hold “no change” H l l q

q

H = HIGH voltage level steady state.

L = LOW voltage level steady state.

h = HIGH voltage level one setup time prior to the HIGH-to-LOW Clock transition.

l = LOW voltage level one setup time prior to the HIGH-to-LOW Clock transition.

X = Don’t care.

q = Lower case letters indicate the state of the referenced output prior to the HIGH-

to-LOW Clock transition.

= Positive Clock pulse.

D Flip-Flop

D Flip-Flop

Q

Q D

CP

SD

RD

SD

RD Q

Q Clk

D

Truth table of D Flip-Flop

INPUTS OUTPUTSOPERATING MODE

CP D Q SD RD Q Asynchronous Set L H X X H L

Asynchronous Reset (Clear) H L X X L H

Undetermined L L X X H H

Load “1” (Set) H H h H L

Load “0” (Reset) H H l L H

H = HIGH voltage level steady state.

L = LOW voltage level steady state.

h = HIGH voltage level one setup time prior to the LOW-to-HIGH Clock transition.

l = LOW voltage level one setup time prior to the LOW-to-HIGH Clock transition.

X = Don’t care.

T Flip-Flop

T Q Clk Q’

a Logic Diagram

T Flip-Flop

Symbols for Flip-Flops

Characteristic Tables of Flip-Flops

T Q(n) Q(n+1) 0 0 0 0 1 1

1 0 1 1 1 0

b Characteristic Table

T 0 1 Q(n)

1 0 0

0 1 1

Q(n+1) = TQ(n)’+T’Q(n)

c Characteristic Equation

D Q Q Q Q S J T

CLK

RS FF

R Q’

JK FF

K

CLK CLK CLK

Q’ Q’ Q’

D FF T FF

RS Flip-Flop JK Flip-Flop

J K Q(n + 1) Condition

0 0 Q(n) No change 0 1 0 Reset 1 0 1 Set 1 1 Q’(n) Complement

S R Q(n+ 1) Condition 0 0 Q(n) No change 0 1 0 Reset 1 0 1 Set

1 1 ? Unpredictable

D Flip-Flop T Flip-Flop

Excitation Tables of Flip-Flops

N-bit Shift Register

Q(n) Q(n+1) S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0

RS FF

Q(n) Q(n+1) J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

JK FF

Q(n) Q(n+1) D 0 0 0 0 1 1 1 0 0 1 1 1

D FF

Q(n) Q(n+1) T 0 0 0 0 1 1 1 0 1 1 1 0

T FF

D Q(n + 1) Condition T Q(n + 1) Condition

0 0 Reset 0 Q(n) No change 1 1 Set 1 Q’(n) Complement

D0 Q0 D1 Q1 DN-1 QN-1

Clk

Serial Input

Serial Output

Random Access Memory (RAM) D 0W-1 – D

AN-1 – A0

Block diagram of a RAM _________________________________________________________________________________

Clock Parameters and Skew

Clock Waveform

RAM 2N x D

R Q 0W-1 – Q

W CS

tr tf

TON TOFF

T

90 %

50 %

10 % 0 %

100 %

CLK 1 Interconnect Delay 1

Clock skew

Setup, Hold and Propagation Delay Times in a Register

Setup and Hold Times in a Flip-flop

CLK

CLOCK CLK 1CLK N

Interconnect Delay N CLK N

Clock

Data can change here

Data must Data can change here Data input

be stable here

tS tH

tpLH tpHL

D Input

Clock

Q Output tpLH tpHL

Q’ Output

Propagation Delay Time in a D Flip-flop

The maximum clock frequency may be expressed as: Fmax = 1/ Tclk or

Fmax = 1/(tpmax + tCmax + tS)

Hold time is satisfied if: tpmin + tCmin ≥ tH

Digital System Design using SSI/MSI Components

Outputs Inputs Combination Registers Circuits

Block Diagram of a Digital System

Two-bit Binary Counter using JK Flip-flops

00

01 11

1 1

INPUT I = 0

0

0

State Diagram for a Controlled Counter

State Table for the Controlled 2-bits Binary Counter

External Input

Flip-Flops Flip-Flops Flip-Flops Present State Next State Inputs

I A B A+ B+ JA KA JB KB 0 0 0 0 0 0 X 0 X 0 0 1 0 1 0 X X 0 0 1 0 1 0 X 0 0 X 0 1 1 1 1 X 0 X 0 1 0 0 0 0 0 X 0 X 1 0 1 1 0 1 X X 1 1 1 0 1 1 X 0 1 X 1 1 1 0 0 X 1 X 1

JA = IB

AB

0 0 X X

0 1 X X

X X 0 0

X X 1 0

00 01 11 10

1

0

KA = IB

I

AB 00 01 11 10

I 0

1

K Maps for JK Flip-flops’ inputs

Logic Circuit Diagram of the Controlled 2-bits Binary Counter

Design of a 3-Bit Counter Using T and D Flip-flops

000

010 110

001 111

X 0 0 X

X 1 1 X

KB = I

00 01 11 10 AB

I 0

1

0 X X 0

AB 00 01 11 10 I

0

0 X X 1 1

JB = IA

J Q

K Q’

J Q

K Q’

CLK

I B

I A

A

B

JB

JA / KA

JA

KA

CLK JB

I = KB

State diagram of a 3-bit binary counter

State Table for a 3-Bit Counter Using T and D Flip-flops

Present State Next State T Flip-Flops Inputs

D Flip-Flops Inputs

A B C A+ B+ C+ TA TB TC DA DB DC

0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0

K Maps for a 3-bit binary counter Using T Flip-flops

TA = BC

BC

0 0 1 0

0 0 1 0

0 1 1 0

0 1 1 0

00 01 11 10

1

0

TB = C

A A

BC 00 01 11 10

1

0 1 1 1 1

BC 00 01 11 10

A

1 1 1 1

0

1

TC = 1

Q T

Logic Circuit Diagram of the 3-bit binary counter Using T Flip-flops

K Maps for the 3-bit binary counter Using D Flip-flops

Q’

B C

B

TA CLK

C = TB

T Q

Q’

A

CLK

TA

T Q

Q’

C

CLK

VCC = TC

DA = A’BC+AB’+AC’

BC

0 0 1 0

1 1 0 1

0 1 0 1

0 1 0 1

00 01 11 10

1

0

DB = B’C+BC’

A A

BC 00 01 11 10

1

0 1 0 0 1

1 0 0 1

BC 00 01 11 10

A 0

1

DC = C’

D Q

Q’ A C’

B

CLK

DB

D Q

Q’

DA A A’

CLK

D Q

Q’

C

CLK

C’ = DC

B DA A’

B’

C’

C

A B’

B DB C

Logic Circuit Diagram of the 3-bit binary counter Using D Flip-flops

Controlled Three-bit Binary Counter using ROM and Registers

State Table for ROM based Counter Implementation

ROM Address

A3 A2 A1 A0 ROM Content

D3 D2 D1 D0 Input Present State Next State

I A B C A+ B+ C+ OUT 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1

Registers

Digital System Design Using Registers and a ROM

Algorithmic State Machine

State Box of an ASM Chart

Outputs or Operations

CodeState Name

a Format

LOAD, Z = 0

0000INITIALIZE

b An Example

Condition

1 or T To

Conditional Output or State Box

0 or F

From State Box

Outputs or Operations

From Decision Box

To Next State Box

A3A

B 16 x 4 ROM

A+ A I D3B+

BD2A A2

C+CC D1A1B

OUT D0A0CCLK

a Decision Box b Conditional Output

Decision Box and Conditional Output of an ASM Chart

0000

An Example of Combined Decision Boxes and Conditional Outputs

Digital System Design Using ASM Chart and PAL

SR = 0

S0

CS

0001

1 0

S1

LD 0

1

SR = AA

0010S2

Processor Status

Control Signals

Data ControlLogic

Output Data

Input Data

External inputs

Processor

CLKCLK

Block Diagram of a Digital System Viewed as Control and Data Processors

Single Pulser Using ASM Chart

ASM Chart of the Single Pulser

ASM Table of Single Pulser

State Name

Qualifier Present State

Next State Single_Pulse

Detect Synch_PB’ 0 0 0 Synch_PB 0 1 1

0

1

Synch_PB

0

1

0

1

Single Pulse

DETECT

DELAY

Synch_PB

Delay Synch_PB’ 1 0 0 Synch_PB 1 1 0

State Register Data Synchronizer

Synch_PB Deb_PB Q DD

Circuit Diagram of the Single Pulser

Design of a Vending Machine using PAL

To Output Solenoids of the can dispensing mechanism

RDY

OS1

OS2

OS3

OS4

OS5

CCA

COIN ACCEPTOR

CA

CLEAR

CA

s0 s1 s2

1 2 4

Dec. Weights

2HZ CLK

RES

4

100 K

s2

+ Vcc

+ Vcc

s1 s0

BCD SWITCH

10 μF

To ready lamp O

(Typ. for all outputs)

PAL

CONTROLLER

Q’ CLK CLK

Single_Pulse

Usage

1. Wait for RDY lamp to switch ON.

2. Set BCD switch to the desired value.

3. Insert the correct coin and collect the desired can.

Circuit Diagram of a Vending Machine using PAL

One-hot

State Assignment s = s2 s1 s0 => BCD switch to select the

desired item

S0 1 0 0 0 0 0

S1 0 1 0 0 0 0 CA = Coin Accepted

S2 0 0 1 0 0 0 RDY = System is Ready to accept coin

S3 0 0 0 1 0 0 RES = Power On reset signal

S4 0 0 0 0 1 0 CCA = Clear Coin Accept

S5 0 0 0 0 0 1

S0 RDY=1

CA=1 s=1/6/9

S1 OS1=1 CCA=1 S3

OS3=1 CCA=1

S2 OS2=1 CCA=1

S4 OS4=1 CCA=1

S5 OS5=1 CCA=1

CA=0

CA=1 s= s2 s1 s0 = 0/5/8

CA=1 s=4

CA=1 CA=1 s=3 s=2/7

State Graph for Vending Machine

State Table for Vending Machine

Present state Inputs Next state Outputs R C O O O O O A B C D E

F CA s2 s1 s0

A+ B+ C+ D+ E+ F+ D C S S S S S Y A 1 2 3 4 5

S0 1 0 0 0 0 0 0 x x x S0 1 0 0 0 0 0 1 0 0 0 0 0 0

1 0 0 0 S1 0 1 0 0 0 0 1 0 0 0 0 0 0

1 0 0 1 S2 0 0 1 0 0 0 1 0 0 0 0 0 0

1 0 1 0 S3 0 0 0 1 0 0 1 0 0 0 0 0 0

1 0 1 1 S4 0 0 0 0 1 0 1 0 0 0 0 0 0

1 1 0 0 S5 0 0 0 0 0 1 1 0 0 0 0 0 0

1 1 0 1 S1 0 1 0 0 0 0 1 0 0 0 0 0 0

S2 0 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0

S3 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0

S1 0 1 0 0 0 0 x x x x S0 1 0 0 0 0 0 0 1 1 0 0 0 0

S2 0 0 1 0 0 0 x x x x 1 0 0 0 0 0 0 1 0 1 0 0 0

x x x x

x x x x

1 0 0 0 0 0 0 1 0 0 1 0 0 S3 0 0 0 1 0 0

S4 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0

S5 0 0 0 0 0 1 x x x x 1 0 0 0 0 0 0 1 0 0 0 0 1

A+ = A B C D E F . CA + CCA+ RES,

B+ = G.( s2 s1 s0 + s2 s1 s0 ), where G = A B C D E F . C A. RES C+ = G.(s2 s1 s0 + s2 s1 s0 ) D+ = G.(s2 s1 s0 + s2 s1 s0 ) E+ = G.s2 s1 s0 F+ = G.s2 s1 s0 RDY = A. RES’, OS1 = B. RES’, OS2 = C. RES’, OS3 = D. RES’, OS4 = E. RES’, OS5 = F. RES’, CCA = (B + C + D + E + F) . RES’

Medium 20 Series, 16R6* PAL Logic Diagram

G G A A B B C C D D E E F F

45

37

39

RES

1 2

0

3 4 5 6 7

1 CLK

7 4 65 1 2 3 8 9 10 11 12 13 14 15

91011

14

12 13

15 Q

Q

Q

Q

Q

8

16

18 19

22

20 21

23

17

24

26 27

30

28 29

31

25

32

34 35

38

36

33

40

42 43

46

44

47

41

15

14

16

17

18

6

5

7

4

3

2

G 19

A

B

A+

B+

0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

×

× ×××

RDY

OS1

CA

OS2

OS3

OS4 Q D

Q D

Q D

Q D

Q D

NC

s0

s1

s2

C C+

D D+

E E+

×××

××

× ××× × × ×

×

×

×

×

×

×

×

× × ×

× × ×

× × ×

× × ×

× ××

× ××

× × ×

* Device of Monolithic Memories

Realization of the Vending Machine Controller using PAL

CLK

Basic Timing Diagram of the Vending Machine Controller

OS1

RES

RDY

1.4 S 0.5 S

CA

For S = 0 High OS2 -

OS5