MICROCOMPUTER ARCHITECTURE12.1 Basic Blocks of a Microcomputer2.2 Typical Microcomputer Architecture2.3 Single-Chip Microprocessor2.4 rogram !"ecution #y Con$entional Microprocessors2.% rogram !"ecution #y typical 32-#it Microprocessors2.& Scalar an' Superscalar Microprocessors2.( )*SC $s. C*SC2A microcomputer has three #asic #locks+ a central processing unit ,C-./ a memory unit/an' an input0output ,*01. unit.The C-,microprocessor. e"ecutes all the instructions an' performs arithmetic an' logic operations on 'ata.A memory unit stores both data and instructions. The memory section typically contains )1M an' )AM chips.A system #us ,comprise' of se$eral 2ires. connects these #locks.34*n a single-chip microcomputer/ these three elements are on one chip/ 2hereasin a single-chip microprocessor/ separate chips are re3uire' for memory an' *01.%&The microcomputer4s system #us contains three #uses/ a''ress/ 'ata/ an' control #us 5hen a memory or an *01 chip recei$es 'ata from the microprocessor/ it is calle' a WRITE operation, and 'ata is 2ritten into a selecte' memory location or an *01 port ,register.. 5hen a memory or an *01 chip sen's 'ata to the microprocessor/ it is calle' a READ operation, and data is rea' from a selecte' memory location or an *01 port.(The Address Bus1.Unidirectional bus: Information transfer takes place in only one direction, from the microprocessor to the memory or *01 elements. 2. Typically 20 to 32 bits long.3. The si6e of the a''ress #us 'etermines thetotal num#er of memory a''resses a$aila#le For example : microprocessor with ! address pi"s ca"#e"erate !! $ %&!'%&'(%&!'( )*tes7The data bus, 1. #i'irectional #us+ 'ata can fow in both directions, that is, to or from the microprocessor. 2. The si6e of the 'ata #us $aries from one microprocessor to another.8The control bus 1. consists of a number of sinals that are used to synchroni!e operation of the in'i$i'ual microcomputer elements.19*s it Unidirectional or #i'irectional #us ::The system clock signals are containe' in the control #us.The num#er of cycles per secon' ,hert6/ a##re$iate' ;6. is referre' to as the clockfre"uency.clock cycle < 10f 2here f is the clock fre3uency.clock fre3uency 'etermines the spee' of the microcomputer.11The microprocessor is the C- of the microcomputerThe logic insi'e the microprocessor chip can #e 'i$i'e' into three main areas+ the register section/ the control unit/ an' the arithmetic-logic unit ,A=-..12The num#er/ si6e/ an' types of registers $ary from one microprocessor to another.Basic Microprocessor Re#isters There are +our )asic microprocessor re#isters: instruction reister, proram counter, memory address reister, and accumulator.13Instruction register (IR) :The instruction reister stores instructions.The 2or' si6e of the microprocessor 'etermines the si6e of the instruction register. >or e"ample/ a 32-#it microprocessor has a 32-#it instruction register.14rogra! "ounter ("):The proram counter contains the address of the instruction or operation co'e ,op-co'e..The program counter normally contains the a''ress of the ne"t instruction to #e e"ecute'.The si6e of the program counter is 'etermine' #y the si6e of the a''ress #us.1%How Pro#ram Cou"ter is ,or- .1. -pon acti$ating the microprocessor4s )!S!T input/ the a''ress of the ?rst instruction to #e e"ecute' is loa'e' into the program counter.2.To e"ecute an instruction/ the microprocessor typically places the contents of the program counter on the a''ress #us an' rea's ,@fetchesA. the contents of this a''ress,i.e./ instruction. from memory3. The program counter contents are incremente' automatically #y the microprocessor4s internal logic. Microprocessor e"ecutes a program se3uentially/ unless the program contains an instruction such as a B-M instruction/ 2hich changes the se3uence.1e!or$ Address Register (#AR). The memory a''ress register contains the a''ress of 'ata. The microprocessor uses the a''ress/ 2hich is store' in the memory a''ress register/ as a 'irect pointer to memory. The contents of the a''ress is the actual 'ata that is #eing transferre'.1(%eneral urpose Register (%R). &or an '(bit !icroprocessor, the general(purpose register is calle' the accu!ulator.*t stores the result after most A=- operations.These 7-#it microprocessors ha$e instructions to shift or rotate the accumulator one #it to the right or left through the carry Cag.*n1&- an' 32-#it microprocessors the accumulator is replace' #y a D).any D) can #e use' as an accumulator.17%eneral urpose Register (%R).The term general(purpose co!es )ro! the )act that these registers can hold data, !e!or$a''resses/ or the results of arithmetic or logic operations.Most registers are general-purpose/ #ut some/ such as the program counter ,C./are pro$i'e' for 'e'icate' functions.18Other Microprocessor Re#isters such as general-purpose registers/ in'e" register/ status register an' stack pointer register.#e"eral/purpose re#isters spee's up the e"ecution of a program #ecause the microprocessor 'oes not ha$e to rea' 'ata from e"ternal memory $ia the 'ata #us if 'ata is store' in one of its general-purpose registers.I"dex Re#ister is typically use' as a counter in a''ress mo'i?cation for an instruction or for general storage functions. -se' to access ta#les or arrays of 'ata.0tatus Re#ister1 a processor status word re#ister or co"ditio" code re#ister/ contains in'i$i'ual #its/ 2ith each #it ha$ing special signi?cance. The #its in the status register are calle' Cags.29Fla#s T*peA carr* 2a# is use' to reCect 2hether or not the result generate' #y an arithmetic operation is greater than the microprocessor4s 2or' si6e.21Auxiliary carry flagFla#s T*peA *ero +ag is use' to sho2 2hether the result of an operation is 6ero. *t is set to1 if the result is 6ero/ an' it is reset to 9 if the result is non6ero.A parit$ +ag is set to 1 to in'icate 2hether the result of the last operation contains either an e$en num#er of 14s ,e$en parity. or an o'' num#er of 14s ,o'' parity./ 'epen'ing on the microprocessor.22Fla#s T*peA sign +ag (sometimes calle' a negati$e Cag. is use' to in'icate 2hether the result of the last operation is positi$e,set to 9. or negati$e,set to 1.,-er+o. +ag arises from representation of the sign Cag #y the most signi?cant #it of a 2or' in signe' #inary operation. The o$erCo2 Cag is set to1 if the result of an arithmetic operation is too #ig for the microprocessor4s ma"imum 2or' si6e/ other2ise it is reset to 923!EAM=! +>in' the sign/carry/6ero/o$erCo2/an' parity e$en Cag for the follo2ing arithmetic sign num#er+,11119999.F,19199991. unctions+1.Binary a''ition an' logic operations2. >in'ing the one4s complement of 'ata3. Shifting or rotating the contents of a general-purpose register 1 #it to the left or right through a carry3%Simple Microprocessor3&BuLer )egister + Stores any 'ata rea' from memory for further processing #y the A=-.3(Typical Microprocessor3738The entium contains t2o instruction pipelines+ the --pipe an' the M-pipe. The --pipe can e"ecute all integer an' Coating-point instructions. The M-pipe can e"ecute simple integer instructionsThe entium contains t2o separate cache memories+ co'e cache an' 'ata cache.49The control unit performs t2o #asic operations+ 1. instruction interpretation2. an' instruction se3uencing.41There are t2o metho's for 'esigning a control unit+42hardwired co"trol Micropro#rammed co"trol1;rmware:clocke' se3uential circuit. )1M insi'e the control unit ,control memory+more e"pensi$eCe"i#ility;o2 incrementing the contents of the register #y 1 is 'one in microprogramming control ::,see ?gures in ne"t sli'es.43444%4&4(47The follo2ing three steps for completing the instruction+1.,etch. The microprocessor fetches -instruction read+ the instruction from the main memory ,e"ternal to the microprocessor. into the instruction register.2. .ecode. The microprocessor decodes or translates the instruction usin the control unit. The control unit inputs the contents of the instruction register/ an' then 'eco'es ,translates. the instruction to 'etermine the instruction type.. /0ecute. The microprocessor e0ecutes the instruction usin the control unit. To accomplish the task/ the control unit generates a num#er of ena#le signals re3uire' #y the instruction.48>or e"ample/ suppose that it is 'esire' to a'' the contents of t2o registers/ < an' 1, and store the result in reister 2. To accomplish this, a con*entional microprocessor performs the follo2ing steps+1. The microprocessor fetches the instruction into the instruction register.2. The control unit ,C-. 'eco'es the contents of the instruction register.3. The C- e"ecutes the instruction #y generating ena#le signals for the register an' A=U sections to perform the follo2ing+a. The C- transfers the contents of registers < a"d 0 )ro! the Register section into the A=-.#. The C- comman's the A=U to A443 c. The C- transfers the result from the A=- into register G of the register section.%9!nhancement in 32-#it microprocessors ,like entium. inclu'e + cache memory/ memory manaement/ pipelinin/ foatin3point arithmetic/ an' branch prediction.Cache memory is a high-spee' rea'02rite memory implemente' as on-chiphar'2are in typical 32-#it microprocessors in or'er to increase processing rates. This topic is co$ere' in more 'etail in Chapter 3.%1Memor* ma"a#eme"t allo2s programmers to 2rite programs much larger than those that coul' ?t in the main memory space a$aila#le to the microprocessorsJ the programs are simply store' on a secon'ary 'e$ice/ such as a har' 'isk. This topic is co$ere' in more 'etail in Chapter 3.%2Basic Concept%3Hi is Hardware designed to perform activity Ai%4T2o Nin' of ipelining+Arithmetic operations an' instruction e"ecution.%%Arithmetic Pipeli"esConsi'er the process of a''ing t2o Coating-point num#ers x $9.8234 O >?% a"d $ 1 2.3' 4 52 !.>irst+ e"ponents of x a"d $ are une6ual.Secon'+ e"ponent alignment.Thir'+ erform the a''ition>ourth+ Pormali6e the ?nal ans2er%&%(I"structio" Pipeli"es*nstruction cycle typically in$ol$es the follo2ing acti$ities+1. *nstruction fetch -nee's ?$e clocks to complete2. *nstruction 'eco'e3. 1peran' fetch ,Hata )ea'.4. 1peration e"ecution%. )esult routing.%7%8!"ample of the e"ecution of a stream of ?$e instructions+ 11/12/13/14/ an' 1%/ in 2hich *3 is a con'itional #ranch instruction.&9This allo2s these microprocessors to anticipate Kumps of the instruction Co2 ahea' of time.&1To accomplish this/ the entium inclu'es on-chip har'2are calle' the 4ranch Unit ,B-.. The B- contains the #ranch e"ecution unit ,B!-. an' the #ranch pre'iction unit ,B-.. 5hene$er the entium encounters a con'itional #ranch instruction/ it sen's it to the B- for e"ecution. The B- e$aluates the instruction4s #ranch con'ition using the B!- an' 'etermines 2hether the #ranch shoul' or shoul' not #e taken. 1nce the B- 'etermines the #ranch con'ition/ it calculates the starting a''ress ,Branch target. of the ne"t #lock of co'e to #e e"ecute'. The entium then starts fetching co'e at the ne2 a''ress.&2Scalar processors such as the 7947& can e"ecute one instruction per cycle. The 7947& contains only one pipeline. Superscalar microprocessors/ can e"ecutemore than one instruction per cycle. These microprocessors contain more than one pipeline.The entium/ a superscalar microprocessor/ contains t2o in'epen'ent pipelines. This allo2s the entium to e"ecute t2o instructions per cycle.&3There are t2o types of microprocessor architectures+ )*SC an' C*SC. )*SC stan' for ,re'uce' instruction set computer. an' C*SCfor ,comple" instruction set computer.&4&%CI0C RI0Clarge num#er of instructionsan' many a''ressing mo'esa simple instructionset 2ith a fe2 a''ressing mo'esslo2er clock rate fast clock ratecomple" control unit/thus re3uiring microprogramme' implementation.har'2ire' control -nitmore 'iQcult to pipelineJ more eQcient pipelining.comple" programs re3uire fe2er instructions in C*SC)*SC re3uires a large num#er of instructions to accomplish the same task*ntel4s original entium is a C*SC microprocessor. *ntel entium ro an' other succee'ing mem#ers of the entium family an' Motorola &79&9 use a com#ination of )*SC an' C*SC architectures for pro$i'ing high performance. The entium ro an' other succee'ing&&