chapter-2 basics 2.1 mosfet basic study -...
TRANSCRIPT
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CHAPTER-2
BASICS
The Basics chapter emphasizes upon the various concepts that are
involved in the functioning of MOS devices, effect of threshold voltage on
characteristics, sub threshold conduction, MOSFET based circuits and
the description of software that is used to carry out the research work
reported in this thesis.
2.1 MOSFET Basic Study
The MOSFET is a four terminal device with the terminal’s source,
drain, gate and substrate [1]. The MOSFET may be an N-channel
MOSFET or P-channel MOSFET. The N-channel MOSFET consists of a
lightly doped p type substrate into which two heavily doped n+ diffusion
regions called source and drain are diffused. Similarly the p- channel
MOSFET consists of N type substrate into which two p+ diffusion regions
called source and drain are diffused.
There are also two categories into which the MOSFET devices can be
split 1) Enhancement MOSFET (EMOSFET) and 2) Depletion MOSFET
(DMOSFET). A MOSFET which has no conducting region at zero gate bias
is called EMOSFET and if a conducting channel exists already at zero
gate bias it is called DMOSFET. The structure of both MOSFET’s is
explained below.
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2.1.1 N - Channel Enhancement MOSFET Structure
Figure 2.1(a): Structure of N-Channel Enhancement MOSFET
N-channel Enhancement MOSFET (EMOSFET) structure is shown in
Figure 2.1(a). It consists of p-type substrate, in which the source and
drain regions are formed by diffusing n- type impurities .The surface of
the substrate region between the drain and source is covered with a thin
oxide layer and the (poly silicon) gate is deposited on top of this dielectric.
The channel length is the distance between the drain and source
diffusion regions and the channel width is the lateral extent of the
channel (perpendicular to the length dimension). The oxide layer
thickness is denoted by tox . For Vd=Vs=Vgs=0, the channel is not
established and the device is in a non conducting condition. When a
positive voltage is applied to gate with respect to source, an electric field
is established between gate and substrate, and causes a charge inversion
region in the substrate, under the gate insulation. A conduction channel
is formed between source and drain.
2.1.2 N-channel Depletion MOSFET structure
Figure 2.1(b) shows the structure of N-channel Depletion MOSFET
(DMOSFET). This n-channel Depletion MOSFET’S are formed on p-type
substrate. By implanting suitable impurities in the region between source
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and drain, the channel is established between the source and drain
regions at Vgs=0.
Figure 2.1(b): Structure of N-Channel Depletion MOSFET
The structure of p-channel EMOSFET’S and DMOSFET can be
explained on similar grounds.
2.1.3 N channel EMOSFET operation
The EMOSFET can be operated in three different modes. They are 1)
Accumulation 2) Depletion and 3) Inversion modes. When a negative
voltage is applied to the gate, the mobile holes are accumulated to the
region below the gate. This is called the accumulation region and is
shown in Figure 2.2(a).A depletion region is formed when a small positive
voltage is applied to the gate and the holes in the substrate are repelled
from the region directly beneath the gate. This region is shown in Figure
2.2(b).When a large positive voltage greater than threshold voltage (VT) is
applied, more and more positively charged holes are repelled and a few
number of free electrons in the substrate are accumulated in the region
beneath the gate .This accumulation of free electrons, form a conductive
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layer of electrons in the p type body and is called inversion layer .This
mode of operation is called Inversion mode and is shown in Figure 2.2( c )
(a) (b) (c)
Figure 2.2(a),(b) and (c):Modes of operation of N-Channel EMOSFET
2.1.4 N channel DMOSFET operation
Depletion mode MOSFET transistor conducts even when Vgs=0 .It is
because that the channel is implanted between source and drain during
manufacturing. When the gate voltage is made negative, positive charged
particles are induced in the channel through the sio2 of the gate
capacitance. Since the drain current is due to majority carries( electrons
for an n-type material ) , the induced positive charges make the channel
less conductive and as Vgs is made more negative, drain current drops .A
depletion MOSFET can also be operated in an enhancement mode by
applying a positive gate voltage into the n-type channel. This is the way
how the conductivity of channel increases.
2.1.5 Characteristics of N channel EMOSFET and N channel
DMOSFET
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In this section the characteristics and region of operation of MOSFET’s
are discussed [2].
2.1.5.1 Transfer characteristics of EMOSFET
Figure 2.3: Transfer characteristics of N channel EMOSFET
The figure 2.3 shows the transfer characteristics of N-channel
EMOSFET. It may be noted from the figure 2.3 that when the gate to
source voltage (Vgs) is less than threshold voltage (Vtn), almost zero
current flows between S and D i.e. (Ids=0). This region of operation of
EMOSFET is called cutoff region or weak inversion region. Increasing the
gate to source voltage above threshold voltage, bias the NMOSFET into
the active region of operation by forming the electron charge layer Qe. The
drain source voltage (Vds) provides the difference in potential needed to
move the charge which results in the current Ids(n) flowing through the
device.
2.1.5.2 Drain characteristics of EMOSFET
Figure 2.4: Drain characteristics of EMOSFET
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The drain characteristics (Id vs Vds) of N channel EMOSFET is shown
in figure 2.4. At the very beginning, as Vds first increases, Ids increases
linearly .This mode of operation is called linear or triode or non
saturation mode. In this mode, the gate voltage is greater than threshold
voltage (Vgs>Vtn) and Vds is small i.e ( Vds < Vgs-Vtn). The transistor is
turned on and a channel has been created which allows current to flow
between the drain and source.
The current from drain to source in linear mode is modeled as
Ids = µn Cox( W/L)(( vgs-vtn)vds- vds2/2)---------Equation 2.1
Where µn is the charge carrier mobility, W is gate width , L is the gate
length and Cox is the gate oxide capacitance per unit area.
From the drain characteristics, it can be observed that when Vgs>Vtn
and Vds > Vgs-Vtn, Ids stops increasing and almost remains constant. This
mode of operation of EMOSFET is called saturation mode.In this
saturation mode, the current is controlled by only the gate –to- source
voltage and modeled as
Ids = (µnCox )/2(W/L)(vgs-vtn)2 ---------------Equation 2.2
2.1.5.3 The transfer characteristics of DMOSFET
Figure 2.5: Transfer characteristics of DMOSFET
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The transfer characteristics of DMOSFET are shown in figure 2.5.
When Vgs is zero and negative, the MOSFET operates in the depletion
mode. On the other hand, if Vgs is zero and positive, the MOSFET
operates in the enhancement mode. The drain current Ids at any point
along the transfer characteristics is given by the relation
2
)(
1
−=
offgs
dssdsV
VgsII ------------------Equation 2.3
It may be noted that even if Vgs=o the device has a drain current equal to
Idss. Due to this fact, it is called normally- ON MOSFET. In depletion
mode, when Vgs=0, maximum current will flow between source to drain.
Thus Ids=Idss. Similarly when Vgs increased continuously, after a certain
extent, the positive charges induced by gate completely depletes the
channel. Thus no drain current flows.
In enhancement mode of operation, increasing Vgs >0, more free
electrons are induced in the channel .Thus it enhances the electrons,
which results in increase in Ids.
2.1.5.4 Drain characteristics of DMOSFET
The drain characteristics for the N channel DMOSFET is given in
figure 2.6
Figure 2.6: Drain characteristics of DMOSFET
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These curves are plotted for both negative and positive values of gate
to source (Vgs) voltage. The curves shown above the Vgs =0 , have a
positive value where as those below it have a negative value of Vgs.
When Vgs is zero and negative, the MOSFET operates in depletion
mode .On the other hand, if Vgs is zero and positive, the MOSFET
operates in the enhancement mode. When Vds =0, there is no conduction
take place between source to drain. If Vgs <0 and Vds >0, then drain
current increases linearly. As a result of Vgs <0 is applied to the gate
induces positive charged holes in the channel and also it controls the
channel width. Thus the conduction (between source to drain is
maintained as constant) i.e Ids is constant. If Vgs >0, the gate induces
more electrons in channel side. It is added with free electrons generated
by source. Again the potential applied to gate determines the channel
width and maintains constant current flow through it as shown in figure
2.6.
Throughout the thesis, only EMOSFETS are considered. PMOSFETS
can be explained on similar grounds and the Table 2.1 gives the
structure, transfer characteristics, output characteristics of both
NMOSFET and PMOSFET devices.
It may be seen from the above discussion that the current voltage
relationships depends on applied voltages and the characteristic
parameters of FET. Important characteristic parameters are width of the
channel, length of channel, thickness of oxide, in addition to the source
and drain junction depths. There are other material parameters like
mobility carries (µn and µp), the silicon material permittivity and the
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conductivity of the channel .The next section deals with the effect of
these parameters on the characteristics of MOSFETS.
Type Cross Section Output
Characteristics
Transfer
Characteristics
N- Channel DMOSFET
N-Channel EMOSFET
P- Channel DMOSFET
P-Channel EMOSFET
Table 2.1-Structure, Output and Transfer characteristics of MOSFET Devices
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2.1.6 Effect of Threshold voltage on the characteristics
As seen from the equations (2.1) and (2.2), there is a characteristics
parameter of the device which indicates the extent of conduction, i.e
threshold voltage which is possible for a given set of voltages. This
threshold voltage in turn depends on the conductivity of substrate, oxide
thickness and surface potential.
2.1.6.1 Threshold voltage (VT) of MOSFET
The threshold voltage of MOSFET is discussed by C.Zhang ,T .Xin
[3,4] and is presented in this section.
Figure 2.7 shows a long-channel enhancement mode n-MOSFET
where body, source and drain terminals are grounded. A voltage, Vgs is
applied to the gate and initially it is zero. As the gate voltage is increased
from a zero value to a positive magnitude, initially a depletion region is
created followed by weak inversion region close to the Si – SiO2 interface.
As the gate voltage is further increased, a condition of strong inversion
sets in where a p-type silicon is inverted to an n-type silicon. This
condition occurs at a certain value of the gate to source voltage and is
called the threshold voltage (VT).
There are three Voltage components which contribute to the threshold
voltage (VT) of a MOSFET. These voltage components are the gate to
semiconductor work function difference (GCφ ) ,
OX
OX
C
Q− due to fixed oxide
charge present in the oxide and at the Si – SiO2 interface, and a gate
voltage
−−
OX
B
FC
Qφ2 to change the surface potential to the strong
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inversion condition and to offset the induced depletion region charge,
QB . Fφ is Fermi energy and COX is the gate oxide capacitance per unit
area.
Figure 2.7: The cross-section of an NMOS transistor
The threshold voltage, VT can be expressed as follows
−−+−=
OX
B
F
OX
OX
GCTC
Q
C
QV φφ 2 -----------------------Equation (2.4)
The first part
−
OX
OX
GCC
Qφ represents voltage required to establish flat-
band (FB) condition .The second part
−−
OX
B
FC
Qφ2 represent voltage
required to bend the bands in Si through a potential of 2 Fφ .
The voltage required for establishing the FB –condition is described by
VFB =
−
OX
OX
GCC
Qφ -------------------------------Equation (2.5)
For n –MOSFET, the charge in the depletion region per unit area, QB is
given by
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FsSiAdAB qNXqNQ φφε −−== 2 for Fs φφ − ≥ 0------Equation (2.6)
Where NA is the substrate doping density, Xd is thickness of the
depletion region and Siε is the permittivity of silicon. The electrostatic
potential at the silicon surface with respect to Si bulk is described by sφ .
At the condition of strong inversion, with no body bias (VSB = 0), the
depletion region charge, QBO is given by
FsiABO qNQ φε 22 −−= -------------------------- Equation (2.7)
In presence of body bias (VSB ≠ 0), the surface potential required to
produce the inversion region is modified to SBF V+− φ2 . The corresponding
charge stored in the depletion region, QB is given by
SBFsiAB VqNQ +−−= φε 22 ---------------- Equation (2.8)
For the n-MOSFET, Eq.(2.4) can be written as
OX
BB
OX
OX
OX
BO
FGCTC
C
Q
C
QV
−−−−−= φφ 2 , or------------ Equation (2.9)
( )FSBFTNOT VVV φφγ 22 −++= -------------- ---Equation (2.10)
Where VT is the threshold voltage of n-MOSFET and VTNO is the zero –
bias threshold voltage with VSB = 0. The Parameters, γ is called the body
– effect coefficient or body factor and is given by Asi
OX
NqC
εγ 21
= .
Normally, 0≤SBV , results in TOT VV ≥ . With the substrate bias, 0≥SBV ,
VT is less than VTO . Thus, an n- MOSFET can be designed to operate at a
reduced voltage .Equation (2.10) can be used for the p-MOSFET with the
use of proper sign. The threshold voltage of p-MOSFET, VTP is given by
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( )FSBFTPOTP VVV φφγ 22 −+−= -----------------Equation (2.11)
Where VTPO is the zero biased threshold voltage of n- MOSFET
Dsi
OX
NqC
εγ 21
= and ND is the doping density in n – substrate.
2.1.7 Effect of length and width on the characteristics of MOSFETS
It may be seen from the equation 2.1 and 2.2, that the current
flowing through the device varies as a ratio of W/L. By increasing the
W/L, one can increase the current that flows for a certain set of terminal
voltages.
2.1.8 Effect of Technology on the characteristics of MOSFETS As the feature size of the device shrinks, the I-V relations given by the
earlier equations get modified by what are called short channel effects
and the corresponding I-V relationships for n-channel devices are given
below by [5].
DI =0, Vgs<VT (cutoff)
++
−−= ds
eff
eff
ds
ds
Tgs
eff
eff
D VL
LV
VVV
L
WkI
θ
θλ
)1(1
2-------------Equation 2.12
[Vgs>VT, Vgs-VT>Vds (ohmic)]
( )
++−= ds
eff
eff
gsTgs
eff
eff
D VL
LVVV
L
WkI
δ
δλ
)1(1
2---------------- Equation 2.13
[Vgs>VT, Vgs-VT>Vds (ohmic)]
θ has units (length)-1 =1
2.0−µ
k=Trans conductance parameter
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Weff, Leff denote the effective channel width and length
Weff =W-WR Leff = L-2LD-LR
Vgs=Gate to source voltage, Vds=Drain to source voltage, VT=Threshold
voltage
Where W, L are drawn width and length. WR and LR are constants
representing width and length reduction due to processing. LD is the
lateral diffusion of source or drain under the gate.
Where λ = channel length modulation parameter
2.1.9 Sub threshold conduction
So far the discussion is around I-V relationships in the normal
operating region (Vgs>Vt). With the need for reducing the power, the use of
FET in sub threshold region (Vgs<Vt) is becoming popular. In the present
section, there is a brief discussion of sub threshold behavior of MOSFET.
Basically the sub threshold conduction or sub threshold leakage or
sub-threshold drain current is the current that flows between the source
and drain of a MOSFET, when the transistor is in the sub threshold
region or weak inversion region, that is for gate to source voltages below
the threshold voltage (Vgs<VT)
The sub threshold current varies exponentially with Vgs and the
current voltage relation is given by equation
−=
−
−
VT
VdsVT
VV
osubds eeII
Tgs
1)(
η
--------------- Equation 2.14
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Where Io= µoCox
L
WVT
2 and η = sub threshold swing coefficient
defined as η =1+OX
dep
C
Cwhere
C dep=Depletion capacitance
OXC =oxide capacitance
VT= Thermal voltage = Kq
T
µo= zero bias electron mobility in the channel
W/L= width over length ratio of the device
VT= Threshold voltage
In sub threshold logic, the drive current (Ion) is the sub threshold current
modeled by equation (2.15) as
Ion= Isub (Vgs=Vds=Vdd< VT) ------------------------ Equation (2.15)
Also the transistor “off” state current (Ioff) is the drain current when
gate-voltage is zero is given by equation (2.16)
Ioff = Isub(Vgs=0,Vds=Vdd<VT)-----------------------Equation (2.16)
It is observed that the drain current changes exponentially with Vgs where
as in strong inversion, drain current responds quadratically with Vgs .
The transfer characteristics of MOSFET is sub threshold region is
usually plotted as in terms of log Id vs gate voltage and typical curve
looks like in the figure 2.8[6].
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Figure 2.8: Transfer characteristics of MOSFET in sub threshold region
There are two parameters that are normally defined in this region
and they are
1) sub threshold slope and
2) sub threshold Swing
2.1.9.1 Sub threshold slope and sub threshold swing
The dependence of gate voltage swing needed to change the drain
current by an order of magnitude is defined as a sub threshold slope ‘S’
and ‘S’ is defined as
S = ( )
gs
d
dV
ILogd1
10
−
------------------------------Equation (2.17)
The sub threshold slope S is an important device parameter in the
sub threshold region. The smaller the S value is the higher the drive Ion
current is, and thus the faster the device .The sub threshold swing is
inversely proportional to slope.
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In this section the basic MOSFET structure, behavior and its
characteristics have been discussed .The following section deals with the
CMOS Inverter, which is the fundamental logic gate.
2.2 CMOS inverter structure and operation
Figure 2.9-CMOS Inverter structure
So for , the basics of MOSFET devices have been considered. In the
present section a detailed description of CMOS inverter circuit is
considered, as the thesis mainly deals with the CMOS circuits.
The figure 2.9 shows the circuit diagram of a static CMOS inverter.
When the input voltage (VIN) is high and equal to VDD, the NMOS
transistor is on and PMOS transistor is off. When the input voltage (VIN)
is low, NMOS and PMOS transistors are off and on respectively and a
path exists between VDD and VOUT yielding a high output voltage.
2.2.1 Voltage transfer characteristics of CMOS inverter
The voltage transfer characteristics give the response of the inverter
circuit, Vout to specific input voltage Vin. The resultant voltage transfer
characteristics of static CMOS inverter is given in figure 2.10. From the
voltage transfer characteristics, the input and output logic levels are
obtained. In the figure 2.10, VOH refers to the high level output voltage of
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the circuit, when input voltage applied is 0v. Similarly VOL represents
the low level output voltage of the circuit when input voltage applied is
0.2v. The input logic levels VIH (high level input voltage) and VIL(low level
input voltage) are the points at which the voltage transfer characteristics
has slope of -1.
2.2.1.1 Noise Margins of CMOS Inverter
Figure 2.10-VTC characteristics with logic levels
For a gate to be insensitive to noise disturbance, it is essential that
the logic 0 and logic 1 intervals to be as large as possible. A measure of
sensitivity of a gate to noise is given by the noise margin low (NML) and
noise margin high (NMH).
The low level noise margin is given by NML= VIL-VOL---- Equation 2.18
The high level noise margin is given by NMH=VOH-V1H. ---Equation 2.19
2.2.1.2 Dynamic characteristics of CMOS inverter
The dynamic characteristics of CMOS inverter include the power
dissipation, propagation delay, rise and fall time delay and power delay
product.
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2.2.1.2.1 Delay time definitions of CMOS Inverter
The input and output voltage waveforms of a typical inverter circuit
are shown in figure 2.11.The delay parameters include TPHL(high to low
propagation delay), TPLH (low to high propagation delay), T rise(rise time)
and T fall(fall time).
Figure 2.11 propagation delays and rise and fall times
The propagation delay times TpHL and TpLH determines the input to
output signal delay during the high to low and low to high transition of
the output respectively. By definition, TpHL is the time delay between the
50% transition of the rising input voltage and the 50% transition of the
falling output voltage. Similarly, TpLH is the time delay between the 50%
transition of the falling input voltage and the 50% transition of the
raising output voltage.
The average Propagation delay Tp of the inverter characterizes the
average time required for the input signal to propagate through the
inverter.
Propagation delay Tp = ( )
2
LHTHLT pp + ------------- Equation 2.20
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The rise time Trise is defined as the time required for the output voltage
to rise from the 10% level to 90% level. Similarly, the fall time Tfall is
defined as the time required for the output voltage to drop from the 90%
level to 10% level. Reducing gate delays in digital circuits allows the data
processing at a faster rate and improves overall performance.
2.2.1.2.2 Power consumption of CMOS Inverter
The second performance metric of the CMOS inverter is the power
consumption .The average power consumption in conventional CMOS
digital circuits is the sum of three main components.
1) The dynamic (switching) power consumption.
2) The short circuit power consumption
3) The leakage power consumption or static power consumption.
2.2.1.2.2.1 The Dynamic (Switching) power consumption of CMOS
Inverter
In conventional CMOS technologies, the dynamic (switching) power
consumption is the major contributor to the total power dissipation. It is
due to switching capacitance, diffusion capacitance, inter connect
capacitances and the junction capacitance. The CMOS inverter circuit is
shown in Figure 2.9. The output capacitor C constitutes the lumped
parasitic capacitances .When input switches from high to low, the NMOS
transistor is turned OFF and PMOS transistor is ON and capacitor C is
charged .The total energy that is drawn from power supply during this
charging process is equal to CV D D2.Half of the energy is dissipated in
PMOS transistor and other half is stored in capacitor C .When input
switches from low to high, the NMOS transistor turns ON and the
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capacitance C discharges through NMOS transistor. For any logic gate, if
inputs to the gate are assumed to switch at a rate of f times per second,
then the average switching power for that gate is given by
Psw=α.C.V2.fclk -------------------------------------------------Equation 2.21
Where α is the switching activity factor which indicate the probability of
the output switching from 0 to 1,C is the switching capacitance ,V is the
voltage swing and f clk is the switching frequency.
2.2.1.2.2.2 The Short circuit power consumption of CMOS Inverter
Short-circuit power arises when a conducting path exists between
supply and ground. i.e when both PMOS and NMOS are simultaneously
ON. Short circuit current flows when the rise time and fall time of the
input signal is slow. The pull-up and pull-down devices should be sized
properly to achieve slow rise/fall time. This component of power
consumption can be significant in pre charge and evaluate circuits.
Careful design is required to keep this component of power dissipation
small enough to be ignored.
2.2.1.2.2.3 The Static power consumption of CMOS Inverter
For a clear understanding of static power consumption, the CMOS
inverter modes are considered and are shown in Figure 2.12.As shown in
Figure 2.12, case 1, if the input is at logic 0, p-MOS device is on and the
n-MOS device is off. The output voltage is logic 1. Similarly, when logic
1 input is applied, the n-MOS device is on and the p-MOS device is off.
The output voltage is logic 0. From the figure 2.12 it is observed that one
of the transistors is always off. When the gate input is in either of these
logic states, dc current that flows from VDD to GND, is only the sub
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threshold conduction or leakage current. Static power consumption is
the product of the device leakage current and the supply voltage. Total
static power consumption, PS, can be obtained as shown in below
equation (2.22).
PS = Σ (leakage current) * (supply voltage) ------------- Equation (2.22)
Compared to the dynamic power consumption, static power
consumption have been considered as negligible. But in modern CMOS
processes, due to decrease in supply voltage and sub threshold voltage,
the leakage current increases, causing increase in static power
consumption. Hence in modern CMOS technologies, the static power
dissipation component cannot be neglected.
Figure 2.12 CMOS Inverter Mode for Static Power Consumption
2.2.1.2.3 Power delay product of CMOS Inverter
Power delay product (PDP) is the product of the propagation delay
(usually in nanoseconds )and the power dissipation( usually in milli
watts).It has dimensions of energy and usually expressed in the unit
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called pico joule .The smaller the power delay product is, the better the
logic family is considered to be.
2.3 Combinational circuits
In combinational circuits, at any instant of time, the output depends
upon the inputs present at that instant of time .This indicates that there
is no memory in these circuits. Combinational logic circuits are built
from basic logic gates like Inverter ,NAND and NOR gates .The common
combinational circuits built from basic logic gates include Multiplexers,
Decoders ,De-multiplexers and full adder circuits and full subtracter
circuits etc.
2.4 Sequential circuits
In sequential circuits ,the output at any instant of time depend upon
the present inputs as well as past inputs and outputs .That means there
are memory elements available in sequential circuits for storing past
information .Sequential circuits are classified into two main categories
known as synchronous sequential logic circuit and asynchronous
sequential logic circuit. In synchronous sequential logic circuits, the
changes in state occurs by a clock signal applied to the circuit. In the
case of asynchronous sequential logic circuits ,the changes in state
occurs after inputs change and the changes do not depend upon clock
signal .Flip-flop is the basic sequential logic circuit .Flip-flop is used as
the logic storage device in more complex sequential circuits.
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2.5 Conclusions
This chapter is devoted to basics of MOS devices ,combinational and
sequential circuits which is important to understand the contents of this
thesis .In the next chapter the literature survey and the work carried out
by various people to address the problem of power reduction, especially
in sub threshold region of operation of CMOS circuits is dealt with.