chapter 10 cad

7/31/2019 Chapter 10 Cad

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SIMULATION

Used for the purpose of design verification (i,e) ,toeliminate design errors before delivering the designto the foundry.

It involves the construction of a computer model ofthe hardware that is being designed and executingthe model to analyze its behavior.


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Various Simulation Tools

1. Device level simulation - involves a single semiconductordevice.

2. Circuit level simulation deals with small groups of

transistors modeled in the analog domain.3. Timing level simulation deals with signals in analog

domain.

4. Switch level simulation deals with MOS transistors asswitches.

5. Gate level simulation deals with gates (NAND,OR ,etc.,)

6. Register transfer level simulation used in synchronouscircuits.

7. System level simulation deals with hardware(e.g .VHDL)


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Software modules in a simulator

1. Simulator Kernel performs the actual simulation.

2. The processing of the input description ahardware description language or a schematic entry tool

that provides an internal format that is well suited to beprocessed by the simulator kernel.

3. The processing of the stimuli used for theprocessing of the input signals that is fed to the actual

circuit.4. The presentation of the results results are

presented to the users by tables of time value pairs,value time plots or various types of animation.


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Gate level modeling and

simulation1. Signal Modeling

2. Gate Modeling3. Delay Modeling

4. Connectivity Modeling

5. Compiler driven simulation6. Event driven simulation


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Gate Modeling

The model should be designed such that thesignal values at the gates outputs are

efficiently computed as a function of thegates inputs .It is achieved through

* Truth table representation

* Subroutine representation


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A truth table representation of a NAND gateincluding the unknown signal value is givenby

In_1 In_2 Out

0 0 1

0 1 1

0 X 1

1 0 1

1 1 0

1 X X

X 0 1

X 1 X

X X X


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Delay modeling An accurate modeling of the delays is important since the delays

can affect the correct functioning of the circuit.

The most important models are

1.Propagation delay model:This model associates a fixed delay with the gates

output. So, any effect of switching inputs is seen at the output afterthis fixed delay. Special cases of the model are

* Zero delay model (delay = 0)

* Unit delay model ( delay = 1)

2.Rise/fall delay model:

This model uses different delays when an outputsignal rises and falls.


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Delay modeling(contd.)3.Inertial delay model:

This model is used to specify the

minimal width that a positive or negative pulse shouldpossess to have any effect at the output.

The minimal width is needed bcoz thecapacitances in a gate have to be charged before the

gates output can change.


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Connectivity modeling This model is used to design a suitable data structure to

represent the connectivity of all gates in the network.

The connectivity representation is required to compute

the propagation of signals through the gates in thecircuit.


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Compiler driven simulation

This is very much used in synchronous circuits, whichcontains registers that store the state of the system and

combinational logic that computes the next state. Consider a simple combinational circuit shown in the

next slide:


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Compiler driven simulation(contd,.)


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Compiler driven simulation(contd,.)

The first step in code generation is leveling(n1 to n5 have level 0,n6 and n7 have level 1,n8 has level 2,and n9 has level 3).

The level number is then used as a sorting criterion for codegeneration. The code for the zero delay simulation of the circuitis given by

n1


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So, to generate code for the unit delay simulation, we consider the variables as ni,tinstead of ni, with i ranging overall net numbers and t ranging over the timeinstants. The pseudo-code is given by

for(t


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Eventdriven simulation

Normally, very few gates switch states simultaneously .So, computing signalpropagation through all gates in the network over and over again leads tounnecessary calculations.

So, we go for event driven simulation which recomputes the signals that areactually changing. Here event refers to signal change.

The central data structure for event driven simulation is the event queueor event list. An event has three attributes:

1) time at which event is supposed to happen.

2) circuit net that will change value at that time.

3) new value that this net will assume.

An event queue stores events and performs the following actions:

1) returning the earliest of the events still to be processedand removing it from the queue.

2) adding a new event at an arbitrary time in the queue.

An event queue can be implemented using ARRAYS or the TIME-

WHEEL.


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Event driven simulation(contd,.)

Array implementation of the event queue


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Event-driven simulation(contd,.) Array implementation was shown in the previous slide where,t is a

minimum unit of time and all delays occurring in the circuit can beexpressed as an integer multiple kt oft.

This array implementation can both return the earliest event andadd new events in constant time. However , the biggestdisadvantage of this method is that, it requires the array to be asbig as the number of time steps that the simulation should take.

So, we go for Time-wheel implementation where we reuse thearray locations that would otherwise remain unused once the

current time had become larger than their indices. This is achieved by using an index t mod L instead of t; where L is

the total number of array locations available.


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Event-driven simulation(contd,.)

Time wheel implementation


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Eventdriven simulation(contd,.) The pseudo-code of the event driven simulation function is given by

event_driven_simulation(){

struct event_queue *Q;

Q


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Switch-level Modeling and Simulation

The switch level is a level between the circuit level(where signals are

analog) and the gate level(where signals are discrete).

Switch level simulation is more accurate than gate level simulation and

requires less computational effort than circuit level simulation.

We are going to discuss about

1) Connectivity and signal modeling

2) Simulation mechanisms


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Connectivity and Signal Modeling

A signal is represented by a pair {s,v},where:

->s is a strength(normally capacitances and resistances)

->v is a level(a voltage with discrete values at least

including 1 , 0 , X ).

Nets or nodes are divided into two groups:->storage nets (that are able to store charge; also they

have a strength(capacitance value))

->input nets(often a power supply terminal)

In Bryants model, all strength values sare integers in the range 1,2,k,,w,with the following sub division

-> s = w: s is the strength of an input signal;

-> k < s < w: s is the strength of a transistor;

-> 1


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Connectivity and Signal Modeling(contd,.)The model is now explained by NAND gates indifferent logic circuit styles:


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Simulation Mechanisms

Normally, the circuit is not simulated as a whole at the switch level ,it isfirst partitioned into sub-circuits that only have uni-directionalcommunication with each other.

The partitioning is done by

1) Static partitioningHere, the connections to the gate of a transistor determine sub-

circuit boundaries irrespective of the signals carried by the nets.

2) Dynamic partitioning

It takes signal values into account which can result in further

partitioning of the sub-circuits. The disadvantage is that the partitioning ofthe circuit has to be repetitively recomputed as the signals change.

These two partitioning methods are diagrammatically explained in the nextslide.


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Simulation Mechanism(Contd,.)


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Shown below is the multigraph model of the static CMOS NAND gate.The multigraph model is used to present the algorithms used in switchlevel simulation.


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Multigraph model:

A graph model with a single type of vertex for the nets and one type

of edge for the transistors. The edge runs between the net connected

respectively to the source and gate ports of the transistor.

This model is used to present the switch level simulation algorithm.

Assumptions to be considered before writing the actual algorithm:

For a given multigraph G(V,E)

-> the signal present on the vertex (u V) can be denoted by (u,u),

where u is the signals strength and u is the signals level.

-> for an edge (u,v) E, u,v is the strength of the transistor

corresponding to the edge if the transistor is conducting. If the transistor is

non conducting ,the value ofu,v is zero.


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Simulation Mechanism:

Assumptions(contd,.)

Also, the transistor limits the strength of the signal passing through it to itsown strength. If a signal at v is stronger than a signal at u , no signalflows from u to v ,but a signal flows from v to u.

The storage nets is subdivided into two groups as

1)Driven nets (signal values are determined by a

conducting path from input nets)

2)Charged nets(does not have such a path)

For a driven net v V, the resulting signal will obey:

v = max1


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Simulation Mechanism(Contd,.) Data structures to be used for switch level simulation algorithm:

struct signal

{

int strength;

voltage level;

};

struct vertex

{

set of struct edge edges;

int strength;

struct signal state;};

struct edge

{

struct vertex *to, *from;

int strength;


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Simulation Mechanism(Contd,.)Consider a small circuit of CMOS transistors:


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chapter 10 cad

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