September 14, 2011

Jo-Won Lee1/Moon-Kyung Kim2

1 Dept. of Convergence Nanoscience, Hanyang University

2 Cornell University

Challenges in the Future Nanoelectronics

Comparison between Microprocessor & E. coli Source: Modified from M. Simpson & P. Cummings in ACS Nano, v5, p2425, 2011

2

Through billions of years, nature has developed a self- assembling, selfduplicating, self-healing, adaptive processing unit that has 6 orders of magnitude higher memory density and 2 orders of magnitude higher computing capacity while utilizing 8 orders of magnitude less power. Required power for the robot as smart as the human

brain(20 Watt) :10-20 MW a small hydroelectric plant

Classification Microprocessor ( i7) Escherichia Coli

Memory Density 12 MB at 32nm (Cache)

= ~5X10-6 Mb/m2

9.2 Mb

= ~5 Mb/m2

# of Logic Gate ~1.2 B/240 mm2

= 5 logic gate/m2

~1,000

= ~500 logic gate/m2

Power Consumption 35 W

= ~3X10-8 W/m2

10-15 W

= 5X10-16 W/m2

3

No Further Miniaturization for MOSFET

Technical Obstacles for Miniaturization

Variation in properties

and size - Unacceptable at nm scale

Lithography

- EUV is the final station

- What can be the next?

Scaling capability

- No solution for NAND Flash

below 10nm

Heat dissipation at nm

- Associated with raising and

lowering an energy barrier

of at least kβT

At present, below 10nm CMOS is very uncertain to manufacture.

- Functionality will be continuously increased following Moore’s law.

2005~2015 : Performance enhancements by new technology - Continued CMOS shrinking, Multicore chips, 3-D packaging, New memory, etc.

> 2015? : New device (Beyond CMOS)? → NRI’s Goal

4

1950 1960 1970 1980 1990 2000 2010

Bipolar CMOS

?

Start of Water Cooling

Year of Announcement

1940

Vacuum Tubes

14

12

10

6

4

2

0

8

Module

Heat Flu

x(w

atts/c

m2)

1947: Invention of Transistor

Why Look for a New Switch Source: Modified from Jeff Welser at INC5, UCLA, May 2009

5

Prohibitive Cost Increase in Fab. Construction & Process R&D: EE Times, June 16, 2011

Year of Production

03~07 08~11 After 2012

Fab. Construction Cost (300mm )

~90 Toolsets necessary

Process R&D Cost

($ B

illio

n)

90~65nm 45~32nm 22~12nm 0

0.4

0.8

1.2

1.6

90~65nm 45~32nm 22~12nm

$0.3~0.4B

$0,6~0.9B

$1.3B

0

1

3

5

$2.5~3B

$3.5~4B

$4.5~6B

7

($ B

illio

n)

EUV tool costs hit $125M- EE Times, Nov. 19th 2010

Gradual Change in Nanofabrication Tech. Source: Modified from NISTEP Report, May, 2007

2010 2020

Top Down - Sequential

Bottom Up - Non-sequential

Gradual change in nanofabrication domain

Technological Uncertainty

3rd Gen. 4th Gen. to 5th Gen.

(NanoSystem) (Molecular Nanosystem/NBIC)

6

DSA

Ribosome Protein: 5~50nm Cell: 10~30μm

Tissue: μm~cm Organ (Heart): cm

Process to Build Human Being

7

8

What can we substitute CMOS for ? Source: Modified from C. Michael Garner, Sept.16, 2003, Intel

Alternative state variables

Spin, nuclear, photon

exciton

Phase; Multiferroics

Plasmonics

Quantum state

Magnetic flux quanta

Mechanical deformation

Dipole orientation

Molecular state

Required characteristics

Scalability : density/cost

Improved performance

Power efficiency

Gain

Operational reliability

Room temp. operation

Less than 10nm channel

Preferred approach

CMOS process

compatibility

CMOS architectural

compatibility

Up to now or maybe forever, no alternative variables can compete with electron.

9

Variable Switching

Energy

Physical

Size Limit

Practical

Size Limit

Electron 2~4 KT 1nm

3-5nm

Spin

500 KT

7nm

>40nm

Photon 3600 KT 20nm

>90nm

Switching energy: from 0 state to 1 state

Spin & Photon are not alternative for Electron as a switching device due to the power consumption

The infrastructure for spin and photon would require a considerable change from what the industry is doing today.

Physical & Practical Limits of State Variables Source: J.A. Hutchby et al., in ICSICT, October, 2006 , Shanghai, China p1049

10

Proposed Emerging Memories for Tera-level

CMOS Based Memory (Evolutionary) - FRAM - MRAM (Magnetic RAM) - PRAM (Phase Change RAM) - FBDRAM (Floating Body DRAM) - NFGM (Nano Floating Gate Memory) - MONOS (Metal Oxide Nitride Oxide Semiconductor) - PoRAM (Polymer RAM ) - RRAM (Resistive RAM) Beyond CMOS Memory (Revolutionary)

- Single Electron Memory - Tracked MRAM - MoRAM (Molecular RAM) - CNT Memory - CBRAM (Conductive Bridge) - Cross-bar (CNT, Resistive, Magnetic) - NEMS Memory: Very high voltage (100 volt) - Memristor

11

Risk Factors for the Future NVM Source: Modified from EE Times, April 4, 2011 after M. Durcan, Feb., 2011

NAND PRAM CBRAM RRAM STT-MRAM

MRAM FRAM Molecul

ar

Data Retention

Medium Low Medium Extreme

Low

Low

Low

Extreme

Bit Density

Low Extreme Medium Medium Extreme Extreme Extreme High

Endurance Medium Low (?)

Low (?)

Extreme

Low

Low

Low

Extreme

Power per Bit

Low High Low Low High Extreme High High

Manufactu-rability

Medium Medium Extreme Medium Extreme Extreme Extreme

Extreme

12

Generic Road-blocks to Tera-level Memory

CMOS-based Conventional/Evolutionary Memory: the same

as the CMOS road-block to scaling–down

- Lithography: EUV, Imprint, E-beam, Bottom-up

Not ready for above 256 Giga Flash

EUV: End of the road

- Device: SCE, Leakage, Read/Write Disturbance

- Reliability: Retention, Endurance

- Not scalable to tera-level unless 3-D integration is applied

Emerging Memory (revolutionary)

- Uncertain for feasibility as a device (cell level demonstration o.k.)

- Uncertain for reliability, reproducibility and manufacturability

What is graphene good for?

13

Electronics:

- High frequency devices utilizing the highest mobility ever

(200,000cm2/Vs at RT: 1,400 for Si and 8500 cm2/Vs for GaAs)

- Interconnet utilizing high current capacity (108 A/cm2) and

lower resistance (1μΩ-cm: 35% less than Cu)

- Heat pad using high thermal conductivity (5 KW/mK: 10 x larger than

Cu and Al)

Transparent Electrode: by seeding plastics with just 1%

- Replacement of ITO (Transparency; 90%, Resistance: 30 Ohm/sq)

Spintronics:

- Potential high spin injection efficiency due to the larger spin diffusion

Mechanical:

- Composite Matls. (Young’s Modulus: 1.0 TPa, Intrinsic Strength: 130 GPa)

Chemical:

- Highest surface to volume ratio ever if utilizing two-side surfaces

Energy Storage:

- A super-conductive membrane between the battery’s poles leading to

ultra-capacitors

Graphene was originally seen as a material that could replace Si in

digital logic circuits. Grahene does not have a bandgap, and its

transistor is very difficult to turn off (on/off ratio= <~1,000).

- Opening a gap of just 1eV is necessary to make graphene ribbons

smaller than 2 nm with single atom precision

Is it possible using current fabrication technology?

- For bilayer graphene, creating a gap of 0.25eV requires around

100 V and you would simply not have access to such high voltages

in devices like cell phones, laptops or tablets

The CVD graphene is not a single crystal and can not be. This leads to

serious problems in the application of nanoelectronics-logic and memory.

- Mobility degradation and variation in properties

- No advantage over other single crystalline high mobility semicond.(Ⅲ-Ⅴ)

It's becoming clear that graphene's promise is not in electronics,

but lies elsewhere. Challenges not the same as those by CNT

- CNT challenges: impossible a few years ago and still impossible now

14

What is graphene bad for?

15

Graphene Synthesis and Applications

Catalog no. K12864, October 2011 c. 370 pp., ISBN: 978-1-4398-6187-5 $129.95 / £82.00

Edited by Wonbong Choi: Florida International University

Jo-Won Lee: Hanyang University

16

What have we achieved for superintelligent nanosystem through TND for last 10 years?

●W

Ls

●B

L

s ●SSL ●GS

L

●PI

PE

NAND Flash (3D + CTF): VLSI 2009

Microphotograph of RTD 29GHz

VCO: 1/170 power consumption

AlGaSb: 1m

Si (001)

GaSb

AlSb

III-V Epi. Growth on Si

InSb QDs

17

An all-Si single electrons at R.T. for ultra low-power computing

18

Neutral Beam and Atomic Layer Etching Equipment & Processes

<35 nm Etch Pattern>

50nm

35nm

35nm Si pattern etch • The charging damage could be removed by using neutral beam instead of inductively coupled plasma.

• Highly anisotropic etch profile could be obtained.

• Significant property improvement of InP HEMTs device by atomic layer etching without damaging (gate recess)

1E9 1E10 1E11 1E12 0

10

20

30

40

50

ALET RIE

f T =100 GHz

Frequency [ GHz ]

f T =166 GHz

L g =0.3 m, Wg =20 m

H 2

1 [

dB

]

Un

it c

urr

en

t g

ain

,

Lg=0.25 m

<InP HEMTs Device Characteristics>

I G (

A)

19

Epi. Graphene by Thermal Decomposition of SiC

Thermal decomposition of SiC wafer surface under vacuum

of 10-6 to 10-5 torr

1300 to 1500oC growth regime

Growth phenomena on silicon and carbon faces

- Si face : 1~ 2 layers, uniform

- C face : 2~5 layers, thicker graphene, high mobility

Raman peaks of graphene on C-face - D peak (1,350) defect,

- 2D peak (2,700) - G peak (1,620) graphene

0.00E+00

2.00E-04

4.00E-04

6.00E-04

8.00E-04

-10 -5 0 5 10

Graphene Transistor: W x L(50um x 50um)

0.5V

1V

Vg (V)

Id (A)

Field Effect mobility: 980 cm2/Vs

TEM

RAMAN

1,500 3,000

20

Metal gate

GST

ALD SiO2

Thermal SiO2

p- Si Substrate

Non-annealed Sample:

T↑ → R↓ ⇒ Meta-stable

FCC Crystalline Phase

H2 Annealed Sample:

T↑ → R↑ ⇒ Stable HCP

Crystalline Phase

New Single Element Memory using GST

5um*5um

-1 0 1 2 3 4 10f

1p

100p

10n

1

100

1m

Dra

in C

urr

en

t, I

D,(

A)

Gate Voltage, VG,(V)

No Anneal @ VD = 0.1V No Anneal @ VD = 2.0V Anneal @ VD = 0.1V Anneal @ VD = 2.0V

Temperature, T('C) 0 20 60 100 140 180

100

1k

10k

100k

1M

125?

1.25m

12.5m

125m

1.25

Resis

tivit

y,

ρ(Ω

*cm

)

Resis

tan

ce,

R [

Oh

m]

Heat Up @HB Test Cool Down @HB Test H2 Anneal @Full F/O No Anneal @Full F/O

21

Thank you!