Latches and Flip Flop

Lecture 11

Digital Design

Dr. PO Kimtho

Department of Computer Sciences

Norton University (NU)

Topic Outlines

Latches & Flip-Flops

Differences between Latches and Flip-

Flops

Types of Latches and Flip-Flops

Edge-Triggered Flip-Flops

Flip-Flop Operating Characteristics

Introduction

Latches and flip-flops are the basic single-bit memory

elements used to build sequential circuit with one or

two inputs/outputs, designed using individual logic

gates and feedback loops.

Latches & Flip-Flops

Latches

The output of a latch depends on its current inputs and on its

previous output and its change of state can happen at any time

when its inputs change.

Flip-Flops

The output of a flip-flop also depends on current inputs and its

previous output but the change of state occurs at specific times

determined by a clock input.

Differences between Latches and Flip-Flops

Latches & Flip-Flops

Latches

S-R (SET-RESET) Latch

Gated S-R Latch

Gated D-Latch

Flip-Flops

Edge-Triggered S-R Flip-Flop

Edge-Triggered D Flip-Flop

Edge-Triggered J-K Flip-Flop

Types of Latches and Flip-Flops

Latches

Type of temporary storage device that has 2 stable (bi-

stable) states

Similar to flip-flop – the outputs are connected back to

opposite inputs

Main difference from flip-flop is the method used for

changing their state

Types:

S-R latch, Gated/Enabled S-R latch and Gated D latch

Active-HIGH input S-R Latch Active-LOW input S-R Latch

S-R (SET-RESET) Latch

Latches

S-R Latch

Logic symbols

Latches

Negative-OR equivalent of the NAND gate S-R latch

S-R Latch

Latches

Truth table for an active-LOW input S-R latch

S-R Latch

Latches

Question: What is the truth table for an active-HIGH input S-R latch?

The three modes of basic latch operation • SET • RESET • no-change & • the invalid condition

S-R Latch

Waveforms

Assume that Q is initially LOW

S-R Latch

Latches

A gate input is added to the S-R latch to make the latch synchronous.

In order for the set and reset inputs to change the latch, the gate input must be active (HIGH/Enable).

When the gate input is low, the latch remains in the hold condition.

Gated S-R Latch

Latches

Gated S-R Latch

Latches

S R G Q Q’ Comment

0 0 0 Q Q’ Hold

1 0 0 Q Q’ Hold

0 1 0 Q Q’ Hold

1 1 0 Q Q’ Hold

0 0 1 Q Q’ Hold

1 0 1 1 0 Set

0 1 1 0 1 Reset

1 1 1 0 0 Not allowed

Gated S-R Latch Truth-table

Latches

1 2 3 4 5

Gated S-R Latch Waveform

Latches

1 2 3 4 5

Gated S-R Latch Waveform

Latches

set reset set reset set

Gated S-R Latch Application

S-R latch is used to eliminate switch contact bounce

Latches

The D (data) latch has a single input that is used to set and to reset the flip-flop.

When the gate is high, the Q output will follow the D input.

When the gate is low, the Q output will hold.

Gated D Latch (74LS75)

Latches

Gated D Latch (74LS75)

Latches

The output follows the input when the gate is high but is in a hold when the gate is low.

Gated D Latch (74LS75) Waveform

Latches

Flip-Flops

Flip-flops are synchronous devices

Synchronous means that the output changes state only

at a specified point on the triggering input called the

clock (CLK)

An edge-triggered flip-flop changes state either at the

positive edge (rising edge) or at the negative edge

(falling edge)

Three types of edge-triggered flip-flops:

S-R Flip-Flops

D Flip-Flops

J-K Flip-Flops

Edge-triggered flip-flop logic

Positive

edge-

triggered

Negative

edge-

triggered

(bubble at C

input)

Flip-Flops

Clock signals and synchronous sequential circuits

A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

Rising edges of

the clock

(Positive-edge

triggered)

Falling edges

of the clock

(Negative-edge

triggered)

Clock signal

Clock Cycle

Time

1

0

Flip-Flops

Edge-triggered S-R Flip-Flop

The basic of S-R flip-flop consist of 2 NOR gates with the outputs cross-coupled to the inputs

Cross-NOR S-R Flip-Flop

Flip-Flops

Note: Flip-flop cannot change

state except on the triggering

edge of a clock pulse.

When S=R=1, invalid condition

exists

Edge-triggered S-R Flip-Flop

Flip-Flops

INPUTS OUTPUTS COMMENTS

S R CLK Q Q

0 0 X Q0 Q0

No change

(Hold condition)

0 1 0 1 RESET

1 0 1 0 SET

1 1 ? ? Invalid

= clock transition LOW to HIGH X = irrelevant (“don’t care”) Q0 = output level prior to clock transition

Edge-triggered S-R Flip-Flop (+ve edge)

-ve edge?

Flip-Flops

Flip-Flops

Addition of an inverter to an S-R flip-flop creates a basic

D flip-flop

Edge-triggered D Flip-Flop

A positive-edge triggered D flip-flop

QUESTION: What is the condition of this S-R flip-

flop?

Flip-Flops

SET

If there is a HIGH on the D input when a clock pulse is

applied, the flip-flop will SET and the HIGH on the D input

is stored by the flip-flop on the positive-going edge of the

clock pulse (In the SET state, flip-flop is storing 1)

RESET

If there is a LOW on the D input when a clock pulse is

applied, the flip-flop will RESET and the LOW on the D

input is stored by the flip-flop on the positive-going edge

of the clock pulse (In the RESET state, flip-flop is storing

0)

Edge-triggered D Flip-Flop (Function of +ve e-t)

INPUTS OUTPUTS COMMENTS

D CLK Q Q

1 1 0 SET

(stores a 1)

0 0 1 RESET

(stores a 0)

= clock transition LOW to HIGH

Edge-triggered D Flip-Flop (+ve e-t)

Truth Table

Flip-Flops

Flip-Flops

Function of J-K Flip Flop is identical to that of the S-R

flip flop in the SET, RESET and no-change conditions of

operation

The difference is that the J-K flip-flop has no invalid

states as does the S-R flip-flop

On each successive clock spike, the flip-flop changes to

the opposite state. This mode is called toggle operation

Edge-triggered J-K Flip-Flop

Simplified logic diagram for a positive edge-triggered J-K flip flop

Edge-triggered J-K Flip-Flop

Flip-Flops

Truth Table for positive edge-triggered J-K flip-flop

INPUTS OUTPUTS COMMENTS

J K CLK Q Q

0 0 Q0 Q0 No change

0 1 0 1 RESET

1 0 1 0 SET

1 1 Q0 Q0 Toggle

(Opposite state)

= clock transition LOW to HIGH Q0 = output level prior to clock transition

Edge-triggered J-K Flip-Flop

Flip-Flops

Flip-Flops Operating Characteristics

Define as the interval of time required after an input

signal has been applied for the resulting output change

to occur

Propagation delay time

tPLH

Propagation delay tPLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

Propagation delay time

tPHL

Propagation delay tPHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

Flip-Flops Operating Characteristics

Flip-Flops Operating Characteristics

Define as the minimum interval required for the logic

levels to be maintained constantly on the inputs (J and K,

or S and R, or D) prior to the triggering edge of the clock

pulse in order for the levels to be reliably clocked into the

flip-flop

Set-up time (ts)

Flip-Flops Operating Characteristics

Define as the minimum interval required for the logic

levels to remain on the inputs after the triggering edge of

the clock pulse in order for the levels to be reliably

clocked into the flip-flop

Hold time (th)

Maximum Clock Frequency (fmax)

The highest rate at which a flip-flop can be reliably triggered.

At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough, and its operation would be impaired

Power dissipation

P = Vcc x Icc

Flip-Flops Operating Characteristics