ch 9. memory, cplds, and fpgas
DESCRIPTION
Ch 9. Memory, CPLDs, and FPGAs. 1. Read-Only Memory. Az : output polarity control Az = 0 output active low Az = 1 output active high. 9.1.1 Using ROMs for “Random” Combinational Logic Function. 9.1.1 Using ROMs for “Random” Combinational Logic Function. - PowerPoint PPT PresentationTRANSCRIPT
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Ch 9. Memory, CPLDs, and FPGAs
1. Read-Only Memory
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Az : output polarity controlAz = 0 output active lowAz = 1 output active high
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.1 Using ROMs for “Random” Combinational Logic Function
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9.1.2 Internal ROM Structure
If diode present, 1Otherwise, Ø
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Diodes are missing, thenD3 – D0 = 0111 instead of 0010
9.1.2 Internal ROM Structure
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9.1.3 Two-Dimensional Decoding
To reduce decoding complexity -> 7 to 128 decoder is huge-> instead, 3 – to 8 decoder + 16 – to – 1 MUX
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If tr exist, 1Otherwise, Ø
9.1.3 Two-Dimensional Decoding
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9.1.3 Two-Dimensional Decoding
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9.1.4 Commercial ROM Types
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9.1.4 Commercial ROM Types
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9.1.4 Commercial ROM Types
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9.1.5 ROM Control Inputs and Timing
Three state busOE : output enableCS : chip select
OE & CS must be assecped
32k x 8bit ROM x 4 = 128kbytes(= 215 x 4 = 217) 17address bits
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9.1.5 ROM Control Inputs and Timing
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9.1.5 ROM Control Inputs and Timing
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9.1.6 ROM Applications
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In many phone connections, your voice is purposely attennated by a few decibels to make things work better (page. 729)
9.1.6 ROM Applications
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9.1.6 ROM Applications
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9.1.6 ROM Applications
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9.1.6 ROM Applications
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9.1.6 ROM Applications
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3. Static RAM9.3.1 Static-RAM Inputs and Outputs
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D-latch when SEL = Ø OUT <- Q when SEL = WR = Ø D <- IN
9.3.1 Static-RAM Inputs and Outputs
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9.3.2 Static-RAM Internal Structure
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9.3.3 Static-RAM Timing
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9.3.3 Static-RAM Timing
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9.3.4 Standard Static-RAMs
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9.3.4 Standard Static-RAMs
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9.3.5 Synchronous SRAM
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9.3.5 Synchronous SRAM
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9.3.5 Synchronous SRAM
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9.3.5 Synchronous SRAM
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9.3.5 Synchronous SRAM
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4. Dynamic RAM9.4.1 Dynamic-RAM Structure
To store 1, word = bit = 1To store Ø, word 1, bit = Ø
Bit line prechanged between H&1To read, word = H If cell = 1 Bit line = 1If cell = Ø, bit line = Ø
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9.4.1 Dynamic-RAM Structure
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9.4.1 Dynamic-RAM Structure
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9.4.1 Dynamic-RAM Structure
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9.4.2 SDRAM Timing
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9.4.2 SDRAM Timing
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9.4.2 SDRAM Timing
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9.4.2 SDRAM Timing
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5. Complex Programmable Logic Devices
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9.5.1 Xilinx XC9500 CPLD Family
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9.5.1 Xilinx XC9500 CPLD Family
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9.5.2 Function-Block Architecture
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9.5.2 Function-Block Architecture
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9.5.3 Input/Output-Block Architecture
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9.5.4 Switch Matrix
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9.6.1 Xilinx XC4000 FPGA Family
6. Field-Programmable Gate Arrays
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9.6.1 Xilinx XC4000 FPGA Family
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F&G perform any combinationLogic function of 4 inputs H for three inputs
9.6.1 Xilinx XC4000 FPGA Family
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9.6.3 Input/Output Block
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9.6.3 Input/Output Block
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9.6.4 Programmable Interconnect
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9.6.4 Programmable Interconnect