ch 8 - control unit and algorithmic state machines
DESCRIPTION
Ch 8 - Control Unit and Algorithmic State Machines. Control Unit. An Instruction performs a well defined task such as adding a number in memory to a number in register file in CPU Example: ADD M(R1), R2, R3 - PowerPoint PPT PresentationTRANSCRIPT
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Ch 8 - Control Unitand Algorithmic State Machines
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Control Unit
An Instruction performs a well defined tasksuch as adding a number in memory to a
number in register file in CPUExample: ADD M(R1), R2, R3which might mean : add the contents of
memory location M(R1) to the contents of register R2 and leave the result in R3
Requires a sequence of microoperations to bring the memory contents, to read the R2, to add, to write the result back in R3
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Control Unit
The whole process requires a sequencing of microoperation control signals
Will depend on the instruction Sequencing is done by the control unit At each clock pulse, a different number of
control signals become high. The control signal coming out of the control
unit is called a ‘control word’
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Control Unit
There are 2 types of control units: Hard wired- All circuits are sequential
circuits and fixed Microprogrammed: The control words are
stored in a memory called ‘Control Memory’ How do we design a hard-wired control unit?
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Control Unit
Control units are just sequential circuits Even a small CU can have many states and
inputs Classical sequential circuit design won’t work
Too many variables Extremely difficult to modify
Therefore most control unit designs are based on some other sequential circuit architecture
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Algorithmic State Machines
One way of improving the level of understanding is to use ASM Charts Algorithmic State Machine (ASM)
ASM charts look something like a software flow diagram
ASM chart is still basically a state diagram Will be used to solve problems that will take a
sequence , maybe a loop of microoperations in hardware
That’s why they are called Algorithmic State Machines
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ASM
An ‘algorithm’ like sequence:
t1.P: R0 R1
t2.Q: R2 M(R1)
t3.T: R0 R1+R2 A hardware Algorithm: Register transfers,
microops and related control signals to realize a given task
ASM: representation of a hardware algorithm in a form of a flowchart
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An example of an ASM: Multiplier
An ‘ASM block’ is a state box and remaining boxes
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ASM Chart Elements
ASM Charts are composed of ASM Blocks An ASM block is composed of
One and only one state box Optional decision boxes Optional conditional output boxes
Each ASM block has a single entry Connected to the state box
Multiple outputs are allowed (decisions) Some outputs may be conditional (Mealy) All transfers in an ASM block are performed in a common
clock cycle.
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ASM State Box
Moore outputs go here
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ASM State Box Example
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ASM Decision Box
c) ASM scalar decision box
From ASM State Box
Condition true pathCondition false path
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ASM Conditional Output Box
Mealy outputs go here
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ASM Vector Decision Box
n-bit Condition
Entry
Exit 0Exit 1
Exit 2n-1
e) ASM vector decision box
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Example:Serial Transmitter
Serial transmitter circuit is basically the same as the serial port output of your PC Sends data to receiver by parallel to serial
conversion (5 to 8 bits per transmission) Extra information is transmitted so receiver
knows where the data starts and ends Odd or even parity can also be included for error
detection
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Serial Transmitter Block Diagram
SERIALTRANSMITTER
DATA
LSNSPEPS
GO
8
2
CLK
SO
DONE
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Serial Transmitter Control / Protocol
MARK
SPACE
StartBit
Stop Bit(1 or 2)
ParityBit
Data Bits (5 to 8), LSB first
LS
00011011
Definition
5 bits6 bits7 bits8 bits
NS
01
Definition
1 stop bit2 stop bits
PE
01
Definition
no parityparity bit
PS
01
Definition
even parityodd parity
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Serial Transmitter RTL
MARK: SO ← ‘1’SPACE: SO ← ‘0’, SR ← DATA, P ← PSDOUT: SO ← SR(0), SR ← shr(SR), P ← P O SR(0)POUT: SO ← P
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Serial Transmitter Control
The serial transmitter CU must provide the proper sequence of control signals to the datapath Controls are MARK, SPACE, DOUT, POUT
The sequence is conditional on the number of data bits, parity enable, and # stop bits
The GO input signals when to start operation This gives us a total of 5 inputs
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Serial Xmit State Diagram
D7-------DOUT
D6-------DOUT
D5-------DOUT
STOP-------
MARK
PAR-------POUT
D0-------DOUT
D1-------DOUT
D2-------DOUT
D3-------DOUT
D4-------DOUT
IDLE-------
MARK,DONE
INIT-------
SPACE GO
RST___GO
LS=3
LS=2
LS=1
LS=0
PE
NS
__ __PE & NS
__ PE & NS
__ NS
Initial Control Unit State Diagram
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Serial Xmit CU
With 12 states, we need 4 flip-flops; this with the 5 inputs will require us to simplify 9 variable combinational logic functions
We can simplify things if we break the problem into two parts A simplified sequential circuit A controlled counter to count the data bits
SPACE: CNTR “01” & LS (4, 5, 6, 7)DOUT: CNTR CNTR - 1LAST := (CNTR = “0000”)
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Reduced Serial Xmit State Diagram
DAT-------DOUT
STOP-------MARK
PAR-------POUT
IDLE-------
MARK,DONE
INIT-------
SPACE
GO
RST___GO
LAST & PE
NS
__ PE & NS & LAST
__ __PE & NS & LAST
__ NS
Final Control Unit State Diagram
_____ LAST
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Serial Transmit ASM Chart
MARK, DONE
IDLE
GO0 1
B
A
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Serial Transmit ASM Chart
SPACE
INIT
C
B
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Serial Transmit ASM Chart
DOUT
DAT
LAST0 1
C
A
PE0 1
NS0 1
D
E
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Serial Transmit ASM Chart
POUT
PAR
NS0 1
D
EA
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Serial Transmit ASM Chart
MARK
STOP
A
E
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One Flip-Flop Per State CUs
Also known as “One Hot” Each state represented by separate FF Active state indicated by FF that is set
All other FFs are reset
State transitions made by shifting the “hot” 1 to the next state
1 FF/State CUs are easy to implement Directly map hardware onto ASM chart
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1 Hot State
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1 Hot Decision
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1 Hot Junction
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1 Hot Conditional Output
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1 Hot Considerations
Operation relies on one and only one FF set at any one time Sync state: when set, all other FFs are reset System reset must also initialize CU
If an output condition is asserted in more than one state, just OR the FF outputs
Modification is easy; changes limited
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Sequence Register and Decoder
A parallel register (usually D-FFs) stores control unit state value
States values are decoded into discrete state signals
Discrete state signals combined with inputs to generate sequence register next state values Not too hard to design but next state logic can
get complex quickly
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Controlled Counter as Sequence Register
Like sequence register and decoder but we take advantage of built-in sequencing of counter
Counter control logic determines if counter clears, loads, holds, or counts
Control unit next state is indirectly determined by control logic
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Controlled Counter Built-in Sequencing
n+1
0
k
n
CLEAR
HOLD
LOAD
COUNT
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Reduced Serial Xmit State Diagram
DAT-------DOUT
STOP-------MARK
PAR-------POUT
IDLE-------MARK
INIT-------
SPACE
GO
RST___GO
LAST & PE
NS
__ PE & NS & LAST
__ __PE & NS & LAST
__ NS
Final Control Unit State Diagram
_____ LAST
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Counter Control Mapping and States
DAT-------DOUT
STOP-------MARK
PAR-------POUT
IDLE-------MARK
INIT-------
SPACE
GO
RST___GO
LAST & PE
NS
__ PE & NS & LAST
__ __PE & NS & LAST
__ NS
Final Control Unit State Diagram
_____ LAST
0
1
2 3
4EN
EN
EN
EN
CLR
CLRCLR
LD
HLD
HLD
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Counter Control Equations
ST4 NSST3 NSPELASTST2 CLR
NSPELASTST2 LOAD
NSST3
PELASTST2 ST1 GOST0 EN
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Control Unit Block Diagram
EN A Qa
B Qb
C Qc
D Qd
CLLD
CLK
MUX
01234567
S0S1S2
0010
Comb.Logic
ST0
ST1
ST2
ST3
ST4
inputs
control
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Sequential Multiplication
Combination logic multiplication needs massive amount of logic for large op. sizes
Sequential multiplication is much more logic efficient but takes multiple clocks
Basic step (see text p. 370) is: If multiplier bit = ‘1’
Add multiplicand to partial product
Shift partial product right
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Sequential Multiplication
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Sequential Multiplication
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Multiplier Block Diagram
Reg. B
Reg. A Reg. Q
Counter P
Adder
C
Zerodetect
ControlUnit
INn-1
G
Z
Q0
Control SignalsOUT
n
Cout
n
0
n n
n
4
We assume B,Q and P are
İnitially loaded.
And G signal is controlled from
outside
Multiplicand
initially
Multiplier
initially
AQ : result
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Multiplier ASM Chart
A ← 0P ← n-1C ← 0
G
A ← A + BC ← Cout
Q0
CAQ ← shr(CAQ)C ← 0
P ← P-1
Z
IDLE
MUL0
MUL1
0 1
0
0
1
1
Z is checked in parallel with P=P-1
so the loop is repeated n times
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Design of the Control unit
Microoperation control signals Control of sequencing
should be generated in the CU.
For microop control signals, we look at every register and get all operations on each register.
For sequencing, we remove the microops and get a state diagram.Our states are called IDLE, MUL0, MUL1
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Design of the Control unit
Control signal names. Initialize,load, shift-dec, clear-c
Realized together
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Design of the Control unit
Design of sequencing: Do like a sequential circuit by :
Removing all outputs and conditional output boxes from ASM chart
Any decision box that’s not affecting the state flow must be removed.
Stripped- off ASM chart is seen next. ASM Chart State Diagram State table
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Design of the Control unit
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Design of the Control unit
Sequence register and decoder approach 2 FF’s since we have 3 states The state outputs are inputted to a decoder to
obtain IDLE, MUL0, MUL1 Make the state table from state diagram Find the input equations to FF’s.
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Design of the Control unit
DM1=MUL0
DM0=IDLE.G+MUL1.Z’
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Design of the Control unit
IDLE:00MUL0:01
MUL:10
G=0
G=1
Z=0Z=1
Outputs: same as states
This completes the design of multiplier!
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Microprogrammed Control
The control words are stored in a memory permanently
This memory is called ‘Control Memory’ Made of ‘ROM’ technology: Read Only Memory PROM:programmable ROM(EPROM,EEPROM..) Can only be read - written once permanently The microops in a hardware algorithm are written
to control memory like a program-called microprogram
The control memory has its own sequencing mechanizm; microprogram has parts as microops and sequencing info
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Microprogrammed CU Block Diagram
CAR: holds present ROM address
CDR: holds current microinstruction
MICROINSTRUCTIONS
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Microprogrammed CU Characteristics
Control Store (PROM) contains two types of information:
The control values for the data path
Information which specifies how next CAR value (microaddress) is determined
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Multiplier Microprogrammed CU
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Microprogrammed CU Control Memory Word
IT LD SD CCSELNXTADD0 NXTADD1
3 3 2 1 1 1 1
Microprogrammed CU Control Datapath Control
Depending on the value of the selected condition(SEL), the microprogram continues with either NXTADD0 or
NEXTADD1. IT(Initialize) , LD, SD, CC are control signals discussed previously.
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Select Field Definitions
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μP CU Control Memory Contents (μ code)
DATAPATHSELNXTADD1 NXTADD0
Microprogrammed CU Control Datapath Control
INIT
-
ADD
-
IDLE
IDLE
MUL0
MUL1
MUL1
MUL0
DG
NXT
DQ
NXT
DZ
-
IT, CC
-
LD
SD, CC
IDLE
INIT
MUL0
ADD
MUL1
CAR
We converted the ASM chart here to a microprogram!
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μP CU Control Memory Contents (binary)
IT LD SD CCSELNXTADD1 NXTADD0
Microprogrammed CU Control Datapath Control
001
000
011
000
010
000
010
100
100
000
01
00
10
00
11
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
000
001
010
011
100
ADDRESS
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Hardwired CU versus Microprogrammed CU
Speed: Hardwired is faster ; reading from ROM takes time, especially if its big
Cost: Microprogrammed is cheaper Flexibility: Mp. much more flexible. Upward
competibility among succesive processors etc.
Since speed is the most important factor today, hardwired control is preferred.