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CHAPTER 5

Computer Arithmetic

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Addition and Subtraction of Signed-Magnitude numbers.

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Hardware for signed-magnitude addition and subtraction

B register

Complementer

Parallel adder

A register

Bs

AVF

E

As

Output

Carry

M (Mode Control)

Load SumS

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Flowchart for add and subtract operations.

As = Bs

Minuend in A

Subtrahend in B

Subtract Operation

Augend in A

Addend in B

Add Operation

As BsAs Bs

EA A + B

AVF E

= 0= 1

EA A + B +1

AVF E

As Bs

= 0 = 1

As = Bs As Bs

E A

A A

A A + 1

AS AS

End

(Result is in A and AS)

A 0

= 0

0

= 0 = 1 ABA

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Hardware for signed 2s complement addition andsubtraction

BR Register

Complementer and

Parallel adder

AC Register

V

Overflow

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Algorithm for adding and subtracting numbers in signed 2scomplement representation

Minuend in AC

Subtrahend in BR

ACAC+BR + 1

VOverflow

End

Subtract

Augend in AC

Addend in BR

ACAC+BR

VOverflow

End

Add

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Numerical Example of Binary Multiplication

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Hardware for multiply operation.

Sequence counter (SC)B register

Complement and paralleladder

A register Q register

As Qs

E

(rightmost bit)

Qn

0

Bs

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Flowchart for multiply operation.

Multiplicand in B

Multiplier in Q

AsQs Bs

QsQs Bs

A 0 , E0

SCn -1

Qn EA A + B

Shr EAQ

SC SC - 1

END

(product is in AQ)

SC

=1=0

=00

Multiply operation

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Hardware for Booths algorithms.

Sequence counter (SC)BR register

Complement and paralleladder

AC register QR register

Qn Qn + 1

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Booths algorithm for multiplication of signed-2scomplement numbers.

Multiplicand in BR

Multiplier in QR

AC 0

Qn+1 0

SC n

ACAC + BRACAC + BR + 1

ashr (AC & QR)

SC SC - 1

END

SC

QnQn + 1

=00

=01=10

=00

=11

Multiply

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2-bit by 2-bit array multiplier.

HA

C S

HA

C S

bob1

bob1

ao

a1

coc1c2c3

b1 bo

a1 ao

ao

b1

ao

bo

boa1a1 b1

coc1c2c3

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4-bit by 3-bit array multiplier.

a0b

ob

1b

2b

3

bob1b2b3

bob1b2b3

Addend Augend

4-bit adder

Sum and out put carry

Addend Augend

4-bit adder

Sum and out put carry

0

coc1

a1

a2

c2c3c4c5c6

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Example of binary division

11010

0111000000

01110

011100

- 10001

- 010110- - 10001

- - 001010

- - - 010100

- - - - 10001

- - - - 000110

- - - - - 00110

Quotient = Q

Dividend = A

5-bits of A < B, quotient has 5 bits

6-bits of A B

Shift right B and subtract; enter 1 in Q

7-bits of remainder BShift right B and subtract; enter 1 in Q

Remainder < B; enter 0 in Q; shift right B

Remainder B

Shift right B and subtract; enter 1 in Q

Remainder < B; enter 0 in Q

Final remainder

Divisor:

B = 10001

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Flow chart for divide operation.

Dividend in AQDivisor in B

Divide operation

Qs As BsSC n - 1

EA A+B+1

E

EA A+B

DVF 1

EA A+B

DVF 0

ENDDivide overflow

Sh1 EAQ

E

EA A + B + 1 A A + B + 1

E

0 = = 1

EA A + B

A < B = 0

Qn 1

A B

SC SC - 1

SC

ENDQuotient is in Q

Remainder in A

= 0 0

= 1 = 0= 1

Divide magnitudes

A < BA B