ceng 4480 l10 memory 3byu/ceng4480/2018fall/slides/l10... · 2018-11-14 · l10 memory-3 cam cell...
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CENG 4480L10 Memory 3
Reference:• Chapter 11 Memories• CMOS VLSI Design—A Circuits and Systems Perspective
• by H.E.Weste and D.M.Harris
Bei Yu
L10 Memory-3
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory(CAM)
Read/Write Memory(RAM)
(Volatile)
Read Only Memory(ROM)
(Nonvolatile)
Static RAM(SRAM)
Dynamic RAM(DRAM)
Shift Registers Queues
First InFirst Out(FIFO)
Last InFirst Out(LIFO)
Serial InParallel Out
(SIPO)
Parallel InSerial Out
(PISO)
Mask ROM ProgrammableROM
(PROM)
ErasableProgrammable
ROM(EPROM)
ElectricallyErasable
ProgrammableROM
(EEPROM)
Flash ROM
Memory Arrays
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L10 Memory-3
Read-Only Memories
• Read-Only Memories are nonvolatile– Retain their contents when power is removed
• Mask-programmed ROMs use one transistor per bit– Presence or absence determines 1 or 0
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NOR ROM• 4-word x 6-bit NOR-ROM
– Selected word-line high– Represented with dot diagram
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Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
ROM Array
2:4DEC
A0A1
Y0Y1Y2Y3Y4Y5
weakpseudo-nMOS
pullups
Looks like 6 4-input pseudo-nMOS NORs
L10 Memory-3
EX: NOR ROM• Draw 4-word 4-bit NOR-ROM structure and dot diagram
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Word 0: 0100
Word 1: 1001
Word 2: 0101
Word 3: 0000
ROM Array
2:4DEC
A0A1
Y0Y1Y2Y3Y4Y5
weakpseudo-nMOS
pullups
L10 Memory-3
NAND ROM• 4-word x 4-bit NAND-ROM
– All word-lines high with exception of selected row
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L10 Memory-3
EX. NAND ROM• What’s it function?
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WL[0]=0:
WL[1]=0:
WL[2]=0:
WL[3]=0:
L10 Memory-3
NOR ROM v.s. NAND ROM• NOR ROM:
• (+) Faster• (-) Larger Area (VDD lines)
• NAND ROM:• (+) High density, small area• (-) Slower
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ROM Array
2:4DEC
A0A1
Y0Y1Y2Y3Y4Y5
weakpseudo-nMOS
pullups
delay grows quadratically with the number of series transistors discharging the bitline.
L10 Memory-3
NOR ROM Array Layout*• Unit cell is 12 x 8 λ (about 1/10 size of SRAM)
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bit5 bit4 bit3 bit2 bit1 bit0
word0
word1
word2
word3
L10 Memory-3
Row Decoders*• ROM row decoders must pitch-match with ROM
– Only a single track per word!
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word0
word1
word2
word3
A0 A1 A0 A1A0 A1 A0 A1
L10 Memory-3
Complete ROM Layout*
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PROMs and EPROMs*• Programmable ROMs
– Build array with transistors at every site– Burn out fuses to disable unwanted transistors
• Electrically Programmable ROMs– Use floating gate to turn off unwanted transistors– EPROM, EEPROM, Flash
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n+
p
GateSource Drain
bulk Si
Thin Gate Oxide(SiO2)
n+
PolysiliconFloating Gate
L10 Memory-3
NOR / NAND Flash Memory*• NOR flash: Intel 1988• NAND flash: Toshiba 1989
• NOR: faster, more expensive• NAND: higher density
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[Toshiba’08]
L10 Memory-3
Building Logic with ROMs• ROM as lookup table containing truth table
– n inputs, k outputs requires 2n words x k bits– Changing function is easy – reprogram ROM
• Finite State Machine– n inputs, k outputs, s bits of state– Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
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ninputs
2n w
ordlines
ROM Array
k outputs
DE
C
ROMinputs outputs
state
n ks
ks
L10 Memory-3
Example: RoboAntLet’s build an AntSensors: Antennae
(L,R) – 1 when in contactActuators: Legs
Forward step F Ten degree turns TL, TR
Goal: make our ant smart enough to get out of a mazeStrategy: keep right antenna on wall(RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman)
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L R
L10 Memory-3 16
L10 Memory-3
Lost in space
• Action: go forward until we hit something– Initial state
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L10 Memory-3
Bonk!!!
• Action: turn left (rotate counterclockwise)– Until we don’t touch anymore
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L10 Memory-3
A little to the right
• Action: step forward and turn right a little– Looking for wall
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Then a little to the right
• Action: step and turn left a little, until not touching
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Whoops – a corner!
• Action: step and turn right until hitting next wall
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Simplification
• Merge equivalent states where possible
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L10 Memory-3
State Transition TableS1:0 L R S1:0’ TR TL F
00 0 0 00 0 0 1
00 1 X 01 0 0 1
00 0 1 01 0 0 1
01 1 X 01 0 1 0
01 0 1 01 0 1 0
01 0 0 10 0 1 0
10 X 0 10 1 0 1
10 X 1 11 1 0 1
11 1 X 01 0 1 1
11 0 0 10 0 1 1
11 0 1 11 0 1 1
Lost
RCCW
Wall1
Wall2
Next state Output valuesInputsCurrent state
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L10 Memory-3
ROM Implementation• 16-word x 5 bit ROM
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ROML, R
S1:0
TL, TR, F
S'1:0
S1' S0' TR'TL' F'
0000000100100011010001010110011110001001101010111100110111101111
4:16 DE
C
S1 S0 L R
L10 Memory-3
PLAs• A Programmable Logic Array performs any function
in sum-of-products form.• Literals: inputs & complements• Products / Minterms: AND of literals• Outputs: OR of Minterms
• Example: Full Adder
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out
s abc abc abc abcc ab bc ac= + + +
= + +
AND Plane OR Plane
abcabcabcabcab
bcac
sa b coutc
Minterm
s
Inputs Outputs
L10 Memory-3
NOR-NOR PLAs• ANDs and ORs not very efficient in CMOS• Dynamic or Pseudo-nMOS NORs very efficient• Use DeMorgan’s Law to convert to all NORs
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AND Plane OR Plane
abcabcabcabcab
bcac
sa b c
outc
AND Plane OR Plane
abcabcabcabcab
bcac
sa b c
outc
L10 Memory-3
PLA Schematic & Layout
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AND Plane OR Plane
abcabcabcabcab
bcac
sa b c
outc
L10 Memory-3
PLAs vs. ROMs
• The OR plane of the PLA is like the ROM array• The AND plane of the PLA is like the ROM decoder• PLAs are more flexible than ROMs
– No need to have 2n rows for n inputs– Only generate the minterms that are needed– Take advantage of logic simplification
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L10 Memory-3
RoboAnt PLA*• Convert state transition table to logic• Karnaugh map
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S1:0 L R S1:0’ TR TL F00 0 0 00 0 0 100 1 X 01 0 0 100 0 1 01 0 0 101 1 01 0 1 001 0 1 01 0 1 001 0 0 10 0 1 010 X 0 10 1 0 110 X 1 11 1 0 111 1 X 01 0 1 111 0 0 10 0 1 111 0 1 11 0 1 1
1 0
0
1 0
TR S STL S
F S S
=
=
= +
L10 Memory-3
EX. RoboAnt Dot Diagram*
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1 0 1 0
1 0
1 0
0
1 0
1'
0 '
S S S LS LRS
S R LS LS
TR S STL S
F S S
= + +
= + +
=
=
= +
L10 Memory-3
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory(CAM)
Read/Write Memory(RAM)
(Volatile)
Read Only Memory(ROM)
(Nonvolatile)
Static RAM(SRAM)
Dynamic RAM(DRAM)
Shift Registers Queues
First InFirst Out(FIFO)
Last InFirst Out(LIFO)
Serial InParallel Out
(SIPO)
Parallel InSerial Out
(PISO)
Mask ROM ProgrammableROM
(PROM)
ErasableProgrammable
ROM(EPROM)
ElectricallyErasable
ProgrammableROM
(EEPROM)
Flash ROM
Memory Arrays*
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L10 Memory-3
CAMs*• Extension of ordinary memory (e.g. SRAM)
– Read and write memory as usual– Also match to see which words contain a key
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CAM
adr data/key
matchread
write
L10 Memory-3
10T CAM Cell*• Add four match transistors to 6T SRAM
– 56 x 43 λ unit cell
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bit bit_b
word
match
cell
cell_b
L10 Memory-3
CAM Cell Operation*• Read and write like ordinary SRAM• For matching:
– Leave wordline low– Precharge matchlines– Place key on bitlines– Matchlines evaluate
• Miss line– Pseudo-nMOS NOR of match lines– Goes high if no words match
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row decoder
weak
missmatch0
match1
match2
match3
clk
column circuitry
CAM cell
address
data
read/write