cedt, indian institute of science, bangalore, india 1 a r educed s witch c ount 5- l evel i nverter...

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 1

A Reduced Switch Count 5-Level

Inverter With Common-Mode Voltage

Elimination and capacitor voltage balancing

For an Open-End Winding IM Drive

Gopal MondalCentre for Electronics Design and Technology

Indian Institute of Science, BangaloreINDIA: 560012


Flow of presentation

Multi-level inverters Previous work Motivation Proposed Scheme Implementation of the proposed Scheme Experimental Results DC-link capacitor voltage balancing an open loop

control scheme Implementation of the Closed loop capacitor voltage

balancing Experimental Results Speed Reversal


Multi-level inverters


Multi-level inverters are the preferred choice in industry for the application in High voltage and High power application

Advantages of Multi-level inverters

Higher voltage can be generated using the devices of lower rating.

Increased number of voltage levels produce better voltage waveforms and reduced THD.

Switching frequency can be reduced for the PWM operation.

Multi-level inverters


A five-level inverter for the open end winding IM drive

Fig.-1

Previous work

The 5-level inverters (Inverter-I and Inverter-II) at both the end of the open end winding induction motor are realised by cascading two 2-level inverters and one 3-level (NPC) inverter.


space vector locations for inverter-I or inverter-II

Fig.-2

Previous work

For each inverters

(inverter-I and inverter-II)

total 125 switching

states available which are

distributed over the 61

voltage vector points

creating a 5-level voltage

vector structure


Combined voltage space vector structure of a dual five-level inverter fed open-end winding induction motor drive

Combined voltage vectors of inverter-I and inverter-II giving a 9-level voltage vector structure.

There are 15625 switching states distributed over 217 voltage space vector point. Fig.-3

Previous work


Common mode voltage (CMV)Because of the common DC- sources at both end

of the inverters, there will be circulating current called the common mode current due to the common mode voltage.

CMV for inverter-I is defined as VCMA = (VAO + VBO + VCO) / 3. (1)

CMV for inverter-II’ is defined as VCMA’ = (VA’O’ + VB’O’ + VC’O’) / 3. (2)Equivalent common-mode voltage for the

combined inverter system (CMV generated at the inverter phases) is

VCM = VCMA – VCMA’

If the nine level voltage vector is generated without common mode voltage, there are 8 DC sources required instead of four.

Previous work


Common mode voltages and its effects

PWM inverters generate high frequency, high amplitude common mode voltages, which induces ‘shaft voltage’ on the rotor side

When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents

This damages the bearings, leading to motor failures and also causes EMI

PWM inverters which do not generate common mode voltage are suggested as a solution to the above problems

Previous work


To eliminate the common mode voltage only those switching states has zero common mode voltage are chosen for the PWM switching.

19 voltage vectors with 19 switching states has zero common mode voltage. Switching states with zero common mode voltage Produce a 3-level voltage space vector structure

Fig.-4

Voltage vectors with zero common mode voltage for the inverter-I and Inverter-II

Previous work


Combined voltage vector structure of inverter-I and Inverter-II

Combination of the two three-level voltage space vector structure will give a five-level structure.

There are 361 switching states distributed over 61 voltage vector points

Fig.-5

Previous work


The power circuit uses total 48 switches.

Redundant switching states are used for the common mode voltage elimination and closed loop DC-link capacitor voltage balancing.

Number of voltage sources can be reduced and two voltage sources are enough with four DC-link capacitors to implement the five level voltage waveform.

Previous work


The reduced power circuit with less number of voltage sources is-

Previous work


Previous work

Fig.-6


There are 361 switching states available for 61 voltage space vector locations for the five level inverter discussed. But only few are used for the common mode voltage elimination and DC-link capacitor voltage balancing.

It implies that the number of redundant switching states can be reduced keeping the performance of the inverter same.

It is observed that by reducing the power circuit structure it is possible to maintain the same performance of the inverter.

Motivation


The propose power circuit of the five-level inverter for open-end winding induction motor drive

Fig.-7

Proposed Scheme


The propose power circuit of the 5-level inverter

The five-level inverters (Inverter system-A and Inverter system-A’) are realised by cascading Two 2-level and a three-level inverters.

Two 2-level inverters are common to both the inverter system-A and Inverter system-A’ Fig.-7b

Proposed Scheme


The propose power circuit of the five-level inverter for open-end winding induction motor drive

Fig.-7a

Proposed Scheme

Complementary

Switches for leg-A of

inverter system-A:

S11 and S14

S21 and S34

S31 and S24

S41 and S44

Similar for the other

phases



Proposed Scheme

Fig.-7b

Due to the power circuit structure some of the available redundant switching states are reduced,

but the available switching states are sufficient for the common mode elimination and DC-link capacitor voltage balancing.


Combined voltage space

vector locations for 5-level

inverter with zero common mode voltage

Proposed Scheme

Fig.-7c


Proposed Scheme

Fig.-7c

Combined voltage space vector for 5-level inverter with zero common mode

voltage



voltage

Proposed Scheme

Switching states for the voltage vector A1’ (-101,-202), (10-1,000), (000,-101), (20-2,10-1), (01-1,-110), (02-2,-12-1),(0-11,-1-12), (-12-1,-220), (11-2,01-1), (1-10,0-11), (1-21,0-22), (2-1-1,1-10),(-110,-211), (2-20,1-21)

Fig.-7c


Some of the switching states are impossible for Fig-II

Fig.-7d

Proposed Scheme

Fig.-II. Proposed power circuitFig.-I. Previous power circuit

Switching state(2-1-1,1-10) possible Switching state (2-1-1,1-10) impossible



voltage

Previous Scheme


Fig.-7c



voltage

Proposed Scheme


Fig.-7c



Fig.-7e

Proposed Scheme

Number of redundant switching states are less for this power circuit compared to the previous one(361).

There are 241 switching states possible for The present scheme(61 voltage space vector locations)

But the available switching states are sufficient for the common mode voltage elimination and DC-link capacitor voltage balancing


Selection of the Switching states for the elimination of common mode voltage

Common mode voltage is eliminated by selecting the switching states which have zero common mode voltage.

Switching states are selected in such a way, that the pole voltage have the half-wave symmetry and there is no even harmonics in both pole and phase voltages

Proposed Scheme

Fig.-8


Speed control scheme

A simple V/f control is used for the implementation of the proposed five-level inverter. The PWM strategy is automatically calculating the switching time for the voltage vectors and the switching states are selected from the look up table in the FPGA.

Proposed Scheme


Experimental Results

(a) Simulation result (b) experimental resultFig.9(a),(b): top and bottom are Pole voltages VOA and VOA’ and the middle one is machine

phase voltage VAA’ for switching the inner Sectors.

[Y-axis: 1div=50V, X-axis: 1div=0.02 sec]


(a) Simulation result (b) experimental result

[Y-axis: 1div=50V,1div=1A, X-axis: 1div=0.01 sec] [Y-axis: 1div=50V, 1div=5A, X-axis: 1div=0.02 sec]

Fig.10(a),(b): Phase voltage and phase current for switching the inner Sectors.




(a) (b)

Fig.11(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics]




phase voltage VAA’ for three-level of operation






Fig.13(a),(b): Phase voltage and phase current for three-level of operation.



(a) (b) Fig.14(a),(b): [Y-axis: normalized amplitude, X-axis: order of harmonics]




phase voltage VAA’ for four-level of operation

(a) [Y-axis: 1div=50V, X-axis: 1div=0.02 sec] (b) [Y-axis: 1div=50V, X-axis: 1div=0.01 sec]





Fig.13(a),(b): Phase voltage and phase current for four-level of operation.




phase voltage VAA’ for five-level of operation






Fig.13(a),(b): Phase voltage and phase current for five-level of operation.


DC-link capacitor voltage balancing


With Proper DC link capacitor balancing the four DC-link voltage sources can be reduced to TWO




Fig.16. Reduced power circuit with capacitor voltage balancing


Two switching states are selected at locations for DC link balancing along with common mode voltage elimination,

The selected two switching states at a particular location has opposite effect on DC link capacitor balancing

So in Two sampling periods the DC link capacitor charges balance can be achieved

In locations where there is no effect on the DC-link capacitors, only one switching state is used for CME

DC-link capacitor voltage balancing- an Open loop control scheme


Motor phase connections for different switching states

Two switching states for the same voltage vector

Fig.-17



Current through

C4:iC+iA

C3:iC

C2:iA

C1:iC+iA

Two switching states for the same voltage vector

Fig.-17


Current through

C4:iC+iA

C3:iA

C2:iC

C1:iC+iA


After two switching interval total current through

C4:2*(iC+iA)

C3: iC+iA

C2: iC+iA

C1:2*(iC+iA)

=>Vc4 = Vc1 and Vc2 = Vc3

(000,-101) and (10-1,000) are complementary pairs



Current through

C4:iC+iA

C3:0

C2:0

C1:iC+iA

=>Vc4 = Vc1 and Vc2 = Vc3

Switching state with no effect on DC-link capacitor voltages

Fig.-18



Fig.-19. (a) Voltage and current waveform for the operation of the motorFrom zero speed to the 5-level of operation



Open loop capacitor voltage balancing works well for the ideal conditions.

For any abnormal conditions like1. Sudden short circuit,

2. Asymmetry in PWM pulses,

3. Unequal DC-link capacitors etc.

Closed loop capacitor voltage balancing is required




It is sufficient to maintain the equal voltage between the capacitor pairs C4, C1 and C3, C2

There are three condition can happen in each pair of capacitors-

C4 > C1 (controller state)C1H

C4 = C1 C1N

C4 < C1 C1L

C3 > C2 C2H

C3 = C2 C2N

C3 < C2 C2L

(H -> High, N-> Normal, L-> Low)

Fig.-20

Closed loop capacitor voltage balancing with capacitor voltage sensing


DC-link capacitor voltage balancingSo the both pair of capacitors will generate together nine controller states

1N 2N

1N 2H

1N 2L

1L 2N

1L 2H

1L 2L

1H 2N

1H 2L

1H 2H

C C ,

C C ,

C C ,

C C ,

C C ,

C C ,

C C ,

C C ,

C C

C4 > C1 (controller state)C1HC4 = C1 C1NC4 < C1 C1LC3 > C2 C2HC3 = C2 C2NC3 < C2 C2L(H -> High, N-> Normal, L-> Low)



C1NC2H C1NC2L

The switching state (01-1, -110) can be used as the corrective state for the controller state C1NC2L and

the switching state (1-10,0-11) can be used as the corrective state for the controller state C1NC2H

Fig.-21


Implementation of the Closed loop capacitor voltage balancing



Variation of capacitor voltage during enabling and disabling of the controller (Operation in 2-level)


Fig.-22

Fig.-23




Fig.-24


Fig.-25



Variation of capacitor voltage during enabling and disabling of the controller (12-step of Operation)

Fig.-27


Variation of capacitor voltage during enabling and disabling of the controller (operation in Over modulation region)

Fig.-26


Speed reversal


Speed reversal

Strategy of DC-link capacitor balancing during speed reversal

• Two comparators are used for the capacitor balancing in speed reversal of the motor.

• First comparator will check the unbalance in the capacitor voltages. Second comparator will check whether the error is increasing or decreasing.

• Initially the controller will select the switching states for the motoring mode, but if the error is increasing it will select the switching states for the generating mode.


1N 2H 1N 2L

1H 2N 1L 2N

1H 2L 1L 2H

1L 2L 1H 2H

C C C C ,

C C C C ,

C C C C ,

C C C C

Speed reversal

Switching states for the controller states will interchange

Strategy of DC-link capacitor balancing during speed reversal


Speed reversal

C2v

C3v

Fig.-27.(a) Voltage and current waveform during machine speed reversal. (b) Capacitor voltages

(a)

(b)


A Front end Switched Rectifier DC Source for Neutral Point Balancing of A NPC Three-

Level Inverter for The Full Modulation Range

K.Sivakumar , Sukumar de, K.Gopakumar , Gopal MondalCEDT, Indian Institute of Science,Bangalore-560012, INDIA

andKeith Corzine

Dept.of EE,University of Missouri, Rolla, USA


• Introduction

• Review of NPC three-level inverter

• Proposed circuit topology to reduce the DC- neutral point

fluctuations

• Simulation results and discussion

• Experimental verification of the proposed topology

• Conclusion

Contents


Capacitor balancing problems exists with a single DC Link

Two separate DC link can solve the problem of neutral point fluctuations, but with increased cost and complexity.

Conventional three-level NPC inverter


Space-vector combinations of three level NPC inverter


Group-A 000, ---, +++,+--, ++-, -+-, -++, --+, +-+

Group-B +0-, 0+-, -+0, -0+, 0-+, +-0

Group-C 00+, 0+0, 0++, +0+, +00, ++0, 0--, 00-, -0-, -00, --0, 0-0

Switching state groups based on the DC capacitor charging and discharging

Group-A switching states will not create any voltage unbalance problems in capacitors

Group-B and Group-C switching states will create voltage unbalance problems in capacitors, with a single DC Link


Proposed Switched Voltage Source Three level NPC Inverter

In the proposed topology only one active voltage source is used with a magnitude of Vdc/2

The rated DC link voltage can be obtained by switching the voltage source (Vdc/2) between the top (C1) and bottom (C2) capacitors with a

duty ratio of 0.5. The DC link switching is independent of the inverter switching control


Source capacitor C is parallel to the Capacitor C1 when S1 is ON


Source capacitor C is parallel to the capacitor C2 when S2 is ON


Top trace is output voltage of the diode bridge rectifier and bottom trace is gating pulse of the

extra switch S1 (Scale X axis: 2ms/div).

Top trace is output voltage of the diode bridge rectifier and bottom trace is gating pulse of the extra switch S1 X axis: 2ms/div), fsw=300Hz

For an ‘n’ pulse rectifier fsw =N* ((n * f1)/2)

The DC Link Voltage Control

Where fsw = minimum Switching frequency of extra switchesf1 = Supply frequency

N = odd integer


Simulation and experimental Results

The proposed topology is simulated with a 4kW three phase induction motor as load and experimentally verified on 1kW Induction motor.

It is tested for entire range of speeds by using V/f control

The inverter switching frequency is 1 kHz

the extra switches which are used to get full DC link voltage

are switched at constant frequency of 600Hz.

The value of each capacitor is 1000µF.

the gating signals are generated using TMS320 F 2812 DSP

and GAL22V10 platforms


Experimental Results for modulation index 0.4

Top trace is Pole voltage bottom trace is phase current [X-axis 10 ms/div Y-axis 50 V/div and 0.3A/div]

Top three traces are Capacitor Voltages bottom trace is Switched rectifier current to C1 [X- axis 2.5 ms/div, Y-axis 20V/div and 1A/div]


Top trace is phase voltage, Second trace is voltage across the switch S1, Third trace is phase current Fourth trace is Switched rectifier current to C1

[X-axis 10 ms/div, Y-axis 50V/div and 1A/div].


Top trace is phase voltage (Van) [Y-axis 50V/div], second trace is Pole voltage(Vao) [Y-axis 50V/div], third trace is line voltage (Vab)[Y-axis 100V/div] Fourth trace is Phase current [Y-axis 1A/div and X-axis 10ms/div]

Two level inverter operation



Top trace - Pole Voltage second trace - Phase current (Scale X-axis: 5ms/div, Y-axis: 50V/div and 0.5A/div)

Top Trace – voltage across the capacitor C, Second trace - voltage across the Capacitor C1 Third trace - voltage across the capacitor C2


Top trace - Phase voltage Phase Voltage, Second trace - Extra Switch voltage, Third trace - Switch Current

(Scale X-axis: 5ms/div, Y-axis: 50V/div and 2A/div)



Experimental Results for Over-modulation

Top trace is pole voltage bottom trace is phase current [ X-axis 2.5 ms/div Y-axis 50 V/div and 1A/div].

Top three traces are capacitor voltages bottom trace is switch (S1) current

[X- axis 10 ms/div, Y-axis 20V/div and 1A/div].


Experimental Results for Over-modulation

Top trace is phase voltage, second trace is voltage across the input switch, third trace is phase current Fourth trace is Switch current[X-axis 5 ms/div, Y-axis 50V/div, 1A/div (third trace) and 2A/div(fourth trace)].


Top trace is phase voltage bottom trace is phase current during the acceleration from 20Hz to 40Hz

[X-axis 500ms/div, Y-axis 50V/div and 2A/div]

Transient performance of the proposed drive topology.


Top trace is pole voltage bottom trace is phase current during the acceleration form 15Hz to 30Hz[X-axis 500ms/div, Y-axis 50V/div and 2A/div]




Top trace is capacitor voltage Bottom trace is phase current during the acceleration form 20Hz to 40Hz [X-axis 500ms/div, Y-axis 50V/div and 2A/div]


In the proposed topology the voltage fluctuations of the neutral point are considerably reduced by switching the voltage source between two capacitors at constant frequency independent of NPC inverter operation.

The DC link Voltage required is half compared to the conventional three level NPC inverter. The rating of all the devices used in proposed topology is equal to the source voltage (i.e. Vdc/2).

This configuration needs only one power supply compared to an H-bridge topology and cascading of two two-level inverters topology, which needs three isolated DC links and two isolated DC links respectively.

CONCLUSION

12-sided polygonal voltage space vector structure for induction motor

drive

ByProf. K. Gopakumar

CEDT, Indian Institute of Science, Bangalore


Motivation for the present research.

Some of the schemes to be presented Hybrid space vector PWM strategy in linear and over-modulation

region involving hexagonal and 12-sided polygonal space vector structure.

Development of two concentric 12-sided polygons using conventional 3-level inverters with capacitor balancing.

Further refinement of the above space vector structure into multiple 12-sided polygons with conventional 3-level inverters.

Discussion on experimental verification of the above schemes Steady state operation. Transient results with motor accelerated upto rated speed with

open-loop V/f control Harmonic performance of phase voltage and phase current under

these conditions

Conclusion

Flow of presentation


Current Technology- Multilevel inverters

• Multi level inverters are popular for high power drives because of low switching losses and low harmonic distortion in the output voltage.

• In conventional structure ,voltage vectors lie on the vertices of a hexagon. So in the extreme modulation range there is a possibility of producing (6n±1) harmonics in the phase current waveform.

•With low switching frequency for high power drives, the (6n±1) harmonics in the current waveform can produce torque pulsation in the drive . The problem is particularly severe in over-modulation region where the (6n±1) harmonics constitute a major portion of the total current.

• In this respect polygonal voltage space vector structures with

sides more than six, is very desirable for high power drives.


Proposed research schemes

• A 12-sided polygonal space vector structure for IM drive has already been proposed using conventional 2-level inverters. This has the advantage of eliminating all (6n±1) harmonics in the phase

current waveform throughout the modulating range. However, one drawback of the scheme is the high dv/dt stress on the devices, since each inverter switches between the vertex of the 12-sided polygon and the zero vector at the centre.

• In the proposed work, a multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the higher modulation region.

• In another scheme, a multilevel voltage space vector structure with vectors on the 12-sided polygon is generated by feeding an open-end winding IM drive by two three level inverters.

•In a third scheme, a high resolution PWM technique is proposed involving multiple 12-sided polygonal space vector structure, that can generate highly sinusoidal voltages at a reduced switching frequency.

A Hybrid Space Vector PWM involving Hexagonal and 12-sided

polygonal voltage space vector structures


Topology of a multilevel inverter for generation of 12-sided polygonal voltage space vector

R-phase

Pole voltage Level S11 S21 S31

1.366kVdc 3 1 1 1

1.0kVdc 2 0 1 1

0.366kVdc 1 1 0 1

0Vdc 0 1 0 0

• Consists of three cascaded 2-level inverters.

• The switch status for different levels of pole voltage are shown below. These are defined with respect to the lower rail of the dc bus.

Switch status for different levels of pole voltage

A

O

B

D

C

Pole voltage of overall inverter-vAO

Pole voltage of INV3- vBO

Pole voltage of INV2-vAB

Pole voltage of INV1-vCD


Transformer connection for generation of 12-sided polygonal voltage space vector

•Asymmetrical DC-links are easily realized by a combination of star-delta transformers, since 0.634kVdc=√3 x 0.366kVdc.


Voltage space vector structure of the proposed scheme

• Consists of four concentric hexagonal structures with different radii (0.366kVdc, 0.634kVdc, 1kVdc and 1.366kVdc)

• Operates in the inner hexagons at lower voltage to retain the advantages of multilevel inverter like low switching frequency.

• At higher voltage, the outermost hexagon and the 12-sided polygonal space vector structure is used resulting in highly suppressed 5th and 7th order harmonics.

• The leads to 12-step operation at rated voltage operation, leading to the complete elimination of 6n±1 harmonics. (n=odd) from the phase voltage.

End of linear modulation

OE: 1.225kVdc


•The modulation index (m), is defined as the ratio of the length of the reference vector to the length of the radius of the 12-sided polygon which extends upto 0.965 in linear modulation range and is equal to 1 at 12-step operation.

•The total dc link voltage for the inverter is 1.366kVdc and the radius of the 12-sided polygon is 1.225kVdc. If the radius of the 12-sided polygonal space vector structure is equal to the radius of a conventional hexagonal space vector structure, then the value of ‘k’ is taken as 1/1.225=0.816.

•For k = 0.816, the maximum phase voltage available in linear modulation is 0.637Vdc and equal to 0.658Vdc in 12-step mode of operation.

• For comparison purpose, if the maximum fundamental voltage available in 6-step mode and 12-step mode are made equal to 0.637Vdc, then ‘k’ is to be chosen as 0.789.

•For k = 0.789, in 12-sided polygonal structure, the maximum phase voltage available in linear modulation is 0.615Vdc and equal to 0.637Vdc in 12-step mode of operation. There is an increase in linear modulation range.

Some additional points on generation of space vectors


Modulating waveform

• The modulating waveform for phase-A for 35Hz operation (linear modulation range) is shown.

• The modulating waveform is synchronized with the start of the sector (sampling interval is always a multiple of twelve).

• Because of asymmetric voltage levels, three asymmetric synchronized triangles are used; their amplitudes are in the ratio 0.366:0.634:0.366.


Switching sequence analysis

• Three pole voltages are shown for a 60 degree interval at 35Hz operation.

•In ‘A’ phase the voltage level fluctuate between levels ‘3 ’ and ‘2 ’, and in ‘C’ phase the voltage level fluctuates between levels ‘1 ’ and ‘0 ’.

• The sequence in which the switches are operated are as follows: (200), (210), (211), (311), (321), (311), (211), (210), (211), (311), (321), (211), (221), (321), (221), (210), (220), (221), (321), (331), (221), (220), where the numbers in brackets indicate the level of voltage.

• This sequence corresponds to 2

samples per sector.


Experimental Setup

•A digital signal processor (DSP), TMS320LF2812 is used for experimental verification.

•For different levels of output in the pole voltage, three carriers are required. However, it is difficult to synthesize three carrier waves in the DSP, as such only one carrier is used and the modulating wave is appropriately scaled and level shifted.

• A 3.7kW induction motor was fed by the proposed inverter operating under open loop constant V/f control at no load. The motor was made to run under no load in order to show the effect of changing PWM patterns of the generated voltage on the motor current, particularly during transient conditions.

•In order to keep the overall switching frequency within 1 KHz, number of samples is decided as follow:Upto 20 Hz operation: 4 samples per sector.20 Hz-40 Hz: 2 samples per sector.Beyond 40 Hz: 1 sample per sector-extending up to final 12-step mode. Individual inverters are switched less than half of the total cycle.


Experimental results-Operation at 10 Hz

Pole voltage waveforms

Phase voltage and current waveforms

Phase voltage

Phase current

Overall inverter

INV3

INV2

INV1

• Switching happens within the innermost hexagon space vector locations.

• As seen from the pole voltage waveforms, only the lower inverter is switched while the other two inverters are off, hence the switching loss is low.

• Four samples are taken in each sector, so INV3 switching frequency is (12x4X10=480Hz). The first carrier band harmonics also reside around 48 times fundamental.

[Inverter Topology]

Normalized harmonic spectrum of Phase voltage

Phase current

[Space Vector]


Experimental results-Operation at 30 Hz

• The space vector locations that are switched lie on the boundaries of the second and third hexagon from the center.

• Number of samples are reduced from four to two, thus switching frequency is (fs=12X2x30=720Hz).

• INV3 and INV1 are switched about 1/3rd of the total cycle, while INV2 is switched about 20% of the cycle.



Phase voltage

Phase current

Overall inverter

INV3

INV2

INV1


Phase current

[Space Vector]

[Inverter Topology]

INV2 switches


Operation at 47 Hz ( end of linear modulation range)

• One sample is taken at the start of a sector, so switching frequency is only around (12X47=564Hz).

• The space vector locations that are switched lie between the outer hexagon and the 12-sided polygon.Pole voltage waveforms


Phase voltage

Phase current

Overall inverter

INV3

INV2

INV1


Phase current

[Space Vector]


Operation at 50 Hz ( 12-step operation)

Inverter Topology

• Complete elimination of 6n±1 harmonics (n=odd) from the phase voltage.

• One sample is taken at the start of a sector (fs=12X1x50=600Hz).

• Each inverter is switched only once in a cycle.



Phase voltage

Phase current

Overall inverter

INV3

INV2

INV1


Phase current


Input current at 50 Hz ( 12-step operation)

• The input current to the inverter is not peaky in nature, because of the presence of the star-delta transformers.

Phase voltage

Phase current

Input phase voltage

Input line current


Motor acceleration with open loop V/f Control

Transition of motor phase voltage and current from 24 samples to 12 samples per

cycle at 40Hz• Because of the suppression of the 5th and 7th order harmonics, the motor current changes smoothly during the transition when the number of samples per sector is reduced from two to one at 40Hz operation.

• As the speed of the motor is further increased, the inverter switching states pass through the inner hexagons and ultimately the phase voltage becomes a 12-step waveform.

• Under all operating conditions, the carrier is synchronized with the start of the sector.

Transition of motor phase voltage and current from outermost hexagon to 12-

step operation.

Phase voltage

Phase current


Total Harmonic Distortion upto 100th harmonic

•It is seen that voltage WTHD is quite low for all the operating conditions, as such the torque pulsation and harmonic heating in the

machine is minimized.

Harmonic performance of phase voltage and current

10Hz 30 Hz 48.25 Hz 50Hz

Voltage THD 57.59% 27.51% 14.67% 17.54%

Voltage WTHD 0.81% 0.7% 0.97% 1.04%

Current THD 12.31% 10.59% 15.6% 19.54%

Current WTHD 0.28% 0.45% 1.2% 1.5%

1002

2

1

nn

V

THDV

2100

2

1

n

n

V

nWTHD

V


• A simplified comparative study is made between the proposed topology and the existing multilevel inverter configurations viz. 3-level NPC and 4-level NPC inverters used for induction motor drives.

•The conduction and switching losses incurred in the inverter, and motor phase voltage harmonic distortions are numerically calculated by computer simulation for comparison.

•A linear turn-on and turn-off switching profile is used for loss calculation. Losses incurred in snubber circuits, protection circuits, gate drives and due to leakage currents are neglected.

•A 2.3kV, 373kW induction motor is driven by a 3-level NPC, 4-level

NPC and the proposed inverter. The inverter drives the induction motor under full load condition at around 0.85 p.f. lagging. Numbers

of samples in a cycle are taken as 24.

Comparison with conventional structures


Loss comparison with conventional structures

Phase voltage WTHD

IGBT Switchin

g loss

IGBT Conductio

n loss

Conduction loss in

anti-parallel diodes

Clamping diode conduction loss

Total Loss

unit % W W W W W

40 Hz Linear modulation

3-level NPC 0.68 95 2180 272 240 2787

4-level NPC 0.46 61 2400 414 350 3225

Proposed Inv 0.46 96 1884 306 0 2286

48 Hz Over modulation

3-level NPC 1.22 27 2370 165 130 2692

4-level NPC 0.89 20 2616 243 169 3049

Proposed Inv 0.55 25 1995 207 0 2227

50 Hz Square wave mode of operation

3-level NPC 4.64 6 2511 184 0 2701

4-level NPC 4.64 12 2730 258 0 3000

Proposed Inv 1.04 10 2034 180 0 2224


Observations

The phase voltage WTHD for the proposed inverter shows considerable improvement, particularly at higher modulation indices and the 12-step mode of operation, because of the suppression or elimination of the 6n±1 (n=odd) harmonics.

Conduction losses are more dominant than switching losses for IGBT made inverters. As such, presence of the clamping diodes in NPC inverters increases the total losses of the inverter. The proposed inverter does not have any clamping diode and is devoid of any such losses. The switching losses also remain low for the proposed inverter.

It is seen that the conduction losses in the proposed inverter are always less than the conventional inverters. This is because in the proposed inverter, for any ‘level’ of pole voltage output, two current carrying switches remain in conduction. This is not always the case in NPC inverters; e.g. for a four level inverter, at higher modulation indices, three switches per phase carry the phase load current when the total dc bus voltage is obtained at the pole. Conduction losses in the proposed inverter are further less in over-modulation region because of the fact that the r.m.s. current in the inverter is less compared to conventional NPC inverters, due to the suppression or elimination of the 6n±1 (n=odd) harmonics.


Synopsis

• A multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the higher modulation region.

• In the extreme modulation range, voltage vectors at the vertices of the outer 12-sided polygon and the vertices from the outer most hexagonal structure is used for PWM control, resulting in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at 50Hz where all the 5th and 7th order harmonics are completely eliminated.

• At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible.

• Apart from this, the switching frequency of the multilevel inverter output is always limited within 1 kHz. The middle inverter ( high voltage inverter) devices are switched less than 25% of the output fundamental switching period.

Multilevel 12-sided polygonal voltage space vector structures


O P

Q

R

SE

F

G

H

I

J K

L

1

2345

6

7

89

1011

12

Hexagonal space vectors.

12-sided polygonal space vectors.

Evolution of space vector structures (Hexagonal and 12-sided)


Multilevel 12-sided polygonal space vector structure

• This is an extension of the single 12-sided polygonal space vector structure into a multilevel 12-sided structure.

• Compared to conventional 12-sided space vector structure, the device ratings and dv/dt stress on them are reduced to half.

• The switching frequency is also reduced to maintain the same output voltage quality.

• Here the added advantage is the complete elimination of 6n±1 harmonics, n=odd, from the phase voltage throughout the modulation index.

• The linear modulation range is also extended compared to the hexagonal structure.


Multilevel 12-sided polygonal space vector structure

• Consists of two concentric 12-sided polygonal space vector structure.

• Unlike conventional hexagonal multilevel structure, here the sub-sectors are isosceles triangles rather than equilateral triangles.

• Each sector is thus divided into four sub-sectors as shown.


Inverter Structure

• In order to realize the proposed space vector structure, two conventional three level NPC inverters are used to feed an open ended induction motor.

• The two inverters are fed from asymmetrical dc voltage sources which can be obtained from the mains with the help of star-delta transformers and uncontrolled rectifiers.

• Because of capacitor voltage balancing of the NPC inverters, only two dc sources are used.


• Here, the timings for which adjacent vectors are switched are obtained as,

•This requires calculation of sine values through a look-up table, which takes unnecessary memory and time in a DSP.

• A better algorithm is proposed here which can calculate the timings by sampling the reference rotating phasor.

1 1

2 2

0 1 2

6* ;

6

* ;

6

;

sin

sin

sin

sin

ref

ref

s

s

s

V T T

V T T

T T T T

V

V

Algorithm for calculating switching times for multilevel 12-sided polygonal space vector structure


1. Any rotating phasor can be expressed as,

,ref jV v v t

2. Transform (α,β) into (a,b,c) and (a’,b’,c’) coordinates as

' ' '

2 2 3 2 3, ,3 3 2 2 3 2 2

2 2 2cos( ) sin ( ) , cos( ) sin ( ) ,3 6 6 3 6 6 3

a cb

a cb

v vv v v v v v

v v v v v v v v

3. Multiply va, vb, vc etc. with the sampling period Ts. Thus, / /. , . , .DC DCa s sba bV VT v T T v T etc

4. Calculate the following

' ' ' ' ' ' ' ' ' ' ' ' ' '

1

1

2

2

, , ; , , ;

, , ; , , ;

max , , mid , ,

max , , mid , ,

mid min

mid mina c a c a c a cb b b b

a c a c a c a cb b b b

T

T

T T T T T T T T T T T T T

T T T T T T T T T T T T T



5. Calculate the following

' ' ' '

' ' ' '

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1_12

2_12

3 13 1 *2 , , * , ,

12 2 2

33 * 1 , , 2 , ,

12 2

2 sin max , max ,

2 sin max , max ,

s

s

nd

nd

T

T

T T T T T T T T

T T T T T T T T

6. Since the timings change for each alternate sector, an additional step is needed for interchanging T1_12s and T2_12s.

Then interchange the values of T1_12s and

T2_12s.

OR

OR

OR

if AND ' '1 2 1 21 , ,max ,T T T T T ' ' '

1 2 1 21 , ,2 max ,T nd T T T T

if AND ' ' '1 2 1 21 , ,max ,T T T T T ' '

1 2 1 22 , ,2 max ,T nd T T T T

if AND

if AND ' ' '1 2 1 22 , ,max ,T T T T T ' '

1 2 1 21 , ,2 max ,T nd T T T T

' '1 2 1 22 , ,max ,T T T T T ' ' '

1 2 1 22 , ,2 max ,T nd T T T T



7. For determining the sub-sectors following comparison is made,

If T1_12s <= 0.5Ts If T2_12s <= 0.5Ts If (T1_12s + T2_12s ) <= 0.5Ts then

Subsector-1. else

Subsector-2. else Subsector-3.else Subsector-4.

8. In sub-sector 1, T1= T1_12s, T2= T2_12s, T0=Ts-T1-T2.

In sub-sector 2, T1= 0.5Ts – T1_12s, T2= 0.5Ts – T2_12s, T0=Ts-T1-T2.

In sub-sector 3, T1= T1_12s, T2= 0.5Ts – T2_12s, T0=Ts-T1-T2.

In sub-sector 4, T1= 0.5Ts – T1_12s, T2= T2_12s, T0=Ts-T1-T2.



Experimental results-15 Hz operation

Phase voltage

Pole voltage- high voltage inverter

Pole voltage-low voltage inverter

Phase current

• Four samples are taken in each sector and switching takes place entirely in the inner 12-sided polygon.

• The phase voltage harmonics reside at 15x12x4=720 Hz, which is 48 times the fundamental. However, the switching frequency of the pole voltage of INV1 is (24x15=) 360Hz, while that of INV2 is (32x15=) 480Hz.

• The higher voltage inverter switches about 50% of the cycle.

Normalized harmonic spectrum of Phase

voltage

Phase current



Phase voltage



Phase current

• Three samples are taken in each sector and switching takes place at the boundary the inner 12-sided polygon. All the 6n±1 harmonics, n=odd, are absent from the phase voltage, while the rest are highly suppressed.

• The switching frequencies of the pole voltage of INV1 and INV2 are respectively (18x23=) 414Hz and (24x23=) 552Hz, with output phase voltage switching frequency at 828Hz (=23x12x3).


voltage

Phase current



Phase voltage

Pole voltage- high voltage inverter Pole voltage-low voltage inverter

Phase current

• Two samples are taken in each sector and switching takes place between the inner and outer dodecagons.

• This is also seen in the phase voltage waveform, since the outer envelope of the waveform at lower frequency becomes the inner envelope at higher frequency.

• The harmonic spectrum of the phase voltage and current shows the absence of peaky harmonics throughout the range.


voltage

Phase current



Phase voltage



Phase current

• This is the end of the linear modulation of operation.• Here the number of samples per sector is two, as such the switching

frequency sidebands reside around 24 times the fundamental. The switching frequency of the pole voltages of INV1 and INV2 is respectively (48x12=) 576Hz and (48x16=) 768Hz, with an output phase voltage switching frequency of 1152Hz (48x12x2).


voltage

Phase current


•At the end of end over-modulation region, 24 samples are taken in a sector, corresponding to the vertices of the polygon. The figure shows 24 steps in the phase voltage.

Experimental results-49.9 Hz operation

Phase voltage



Phase current


voltage

Phase current



• This is the 12-step operation, where one sample is taken at the start of a sector. The phase voltage and current is completely devoid of any 5th and 7th order harmonics.


voltage

Phase current

Phase voltage



Phase current


Total Harmonic Distortion upto 100th harmonic

•It is seen that voltage WTHD is quite low for all the operating conditions, as such the torque pulsation and harmonic heating in the

machine is minimized.

1002

2

1

nn

V

THDV

2100

2

1

n

n

V

nWTHD

V

Voltage THD

Voltage WTHD

Current THD

Current WTHD

15Hz 75.4% 1.48% 24.49% 0.56%

23Hz 21.2% 0.54% 9.19% 0.48%

40Hz24.85

%0.71% 12.08% 0.65%

48Hz 9.67% 0.33% 5.52% 0.26%

49.9Hz

7.26% 0.28% 4.68% 0.24%

50Hz17.54

%1.04% 19.54% 1.5%

Harmonic performance of phase voltage and current


Acceleration of the motor

Transition of motor phase voltage and current from inner to outer 12-sided

polygon

Transition of motor phase voltage and current from over-modulation to 12-step

operation.

Phase voltage

Phase current

• In both the cases, the motor current changes smoothly as the motor accelerates. This happens because of the use synchronized PWM and total elimination of 6n±1 harmonics, n=odd, from the phase voltage throughout the modulation index.


Capacitor balancing scheme

• The inner 12-sided polygonal space vector locations ( points 1-12) have four multiplicities which are complementary in nature in terms of capacitor balancing.

• The outer 12-sided polygonal space vector locations ( points 13-36) either do not cause any capacitor unbalancing, or have complementary states to maintain capacitor balancing.


Inner 12-sided polygon-switching multiplicities for point-1

C2 is discharged, C4 is charged.




The four switching multiplicities are complementary in nature in terms of capacitor balancing.


Outer 12-sided polygon-switching multiplicities

C4 is discharged, C1 & C2 are

undisturbed.

Point-13, two multiplicities

C3 is discharged, C1 & C2 are

undisturbed.

Point-36: no multiplicity, no capacitor disturbance

Point-14: no multiplicity, no capacitor disturbance


Controller action takenDeliberate unbalancing

Vc1, Vc2

Vc3, Vc4

• Capacitor unbalance is done at steady state with the motor running at 20 Hz speed.

• Both side capacitors are deliberately unbalanced and after some time controller action is taken.

C1,C2 : higher voltage side capacitorsC3,C4 : lower voltage side capacitors

Experimental Results-capacitor unbalancing at 20 Hz


Experimental Results-capacitor unbalancing at 40Hz

Controller action taken

Deliberate unbalancing

Vc1, Vc2

Vc3, Vc4

• Both the sides are made unbalanced at the same time and are seen to come back to the balanced state.

• Compared to the 20 Hz case, it requires more time to restore voltage balance, since the number of multiplicities in the outer polygon is less.

C1,C2 : higher voltage side capacitorsC3,C4 : lower voltage side capacitors


capacitor balancing during acceleration

• Capacitor voltages, pole voltages and phase currents during acceleration, showing the capacitor voltages are balanced throughout the operation.

INV1 Pole voltage

Phase current

INV2 Pole voltage

vC1, vC2

vC3, vC4

vC1-vC2

Capacitor voltages


Publication

• Anandarup Das, K. Sivakumar, Gopal Mondal, K Gopakumar, “A Multilevel Inverter with Hexagonal and 12-sided Polygonal Space Vector Structure for Induction Motor Drive” , published in IECON 2008, Nov 2008, pp 1077-1082.

• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “Multilevel Dodecagonal Space Vector Generation for Open-end Winding Induction Motor Drive Using Conventional Three Level Inverters ”, accepted for publication in EPE 2009.

• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “A Combination of Hexagonal and 12-sided Polygonal Voltage Space Vector PWM control for IM Drives Using Cascaded Two Level Inverters”, to be published in May 2009 issue of IEEE Transaction on Industrial Electronics.

• Anandarup Das, K. Sivakumar, Rijil Ramchand, Chintan Patel and K. Gopakumar, “A Pulse Width Modulated Control of Induction Motor Drive Using Multilevel 12-sided Polygonal Voltage Space Vectors”, accepted for publication in IEEE Transaction on Industrial Electronics.


Multiple 12-sided polygons

• With the same power circuit as above, it is possible to have multiple 12-sided polygonal space vector structure.

• Consists of six concentric 12-sided polygonal space vector structure.

• Very low voltage THD can be achieved using low switching frequency.

• Suitable for high power drives.


Conclusion

1. A multilevel inverter topology is described which produces a hexagonal space vector structure in lower-modulation region and a 12-sided polygonal space vector structure in the over-modulation region. This leads to the complete elimination of 6n±1 harmonics (n=odd) from the phase voltage at higher modulation index.

2. A multilevel 12-sided polygonal space vector structure is proposed that does not have 6n±1 harmonics (n=odd) throughout the modulation index. Capacitor balancing scheme is also proposed for the above scheme.

3. These schemes result in improved voltage THD in the motor phase voltage and lower switching frequency operation which are very much desirable in high power drives.

A Hysteresis PWM Controller with Constant Switching Frequency for

Two-level VSI fed Drives with Operation Extending to the Six-Step

Mode

Prof. K. GopakumarCEDT, Indian Institute of Science

Bangalore, INDIA


ORGANIZATIONI. IntroductionII. Current Error Space Phasor in VC –

SVPWMIII. Parabolic Boundary for Current Error

Space PhasorIV. Vector Change Detection in

Proposed ControllerV. Sector Change Detection in

Proposed ControllerVI. Simulation Results & Experimental

ResultsVII. Conclusion


Introduction

PWM Voltage Source Inverter (VSI)

Voltage controlled PWM VSI Current controlled PWM VSI

Current Controlled PWM VSIAdvantages:

Simple, so can be implemented easily Excellent dynamic response

Disadvantages: Large current ripple in steady-state Generation of sub harmonic component

in the current Variation in switching frequency


IntroductionCurrent Controlled PWM VSI

Can be classified into two:

Hysteresis Current Controller based VSI

Ramp Comparison Controller based VSI

Predictive Current Controller based VSI

Other controllers On-off controller Neural network controller Fuzzy logic controller


Introduction

Hysteresis Current Controller based VSI

Fixed Tolerance band Hysteresis Current Controller based VSI

Variable Tolerance band Hysteresis Current Controller based VSI


IntroductionFixed Tolerance band Hysteresis

Current Controller based VSI Eliminates first two disadvantages of the

conventional CC – PWM VSI It’s drawback is the variation of switching

frequency in a fundamental cycle and with variation in the motor speed. Increased switching losses in the inverter Non-optimum current ripple Excess harmonic content in the load current

causing overheating of the machine


IntroductionVariable Tolerance band

Hysteresis Current Controller based VSIUses variable hysteresis band to keep the

switching frequency constant.Examples are: Adaptive hysteresis band Sinusoidal hysteresis bandDisadvantages: Complex to implement Stability problems Limitations in transient performance


Proposed Variable Band Hysteresis Current Controller based VSI

Continuously varying Parabolic Boundary for Current Error Space Phasor

A new sector selection logic eliminating the two outer parabolas used in earlier work is proposed in the present work. This method uses the change in direction of

the current error during sector change along any one of the orthogonal axes.


Current Error Space Phasor in VC – SVPWM

(a) Power schematic of a three-phase (b) Voltage space phasorstructure two-level VSI fed IM drive of the two-level VSI


Basic switching vectors and Sectors

Basic switching vectors and sectors.

6 active vectors (V1,V2, V3, V4, V5, V6)

Axes of a hexagonal

DC link voltage is supplied to the load

Each sector (1 to 6): 60 degrees

2 zero vectors (V0, V7)

At origin

No voltage is supplied to the load




0

0

0

sin(60,

sin 60

sin

sin 60

( )

mS

dc

m2 S

dc

0 S 1 2

1V θ)

TV

V θT T and

V

T T T T

T

*i i i

Δi j 2 3 j 4 3A B Ci i e i e



sd

R L ,dt k b

iV i V *where i Δi i

**

k bΔi i

V Δi i Vs sd d

R L R Ldt dt

**

k bΔi i

Δi V i Vs sd d

R L R Ldt dt

*

*k b

Δi iV i Vs

d dL R L

dt dt

sd

R Ldt

**

m bi

where V i V

k kV V

σ

dΔi ΔVdt= dt

dt L

Integrating both the sides

k

k

VV

σ

ΔVΔi = t

L

dL ,

dt k mΔi

V V



1 2 0here can beeither T or T or T depending uponσ

t ,L

t

kk

(V )(V )

k

ΔV Δi

V

1

2

0

T

T and

T

σ

σ

σ

= ,L

= ,L

=L

11

22

00

(V )(V )

(V )(V )

(V )(V )

ΔVΔi

ΔVΔi

ΔVΔi



(c) at end of the Sector-1 ( varies from 54 to 60 approximately)

(a) at start of the Sector-1 ( varies from 0 to 7 approximately)

(b) at middle of the Sector-1 ( varies from 27 to 33 approximately),

Movement of current error space phasor (on - plane) in a few sampling intervals of VC-SVPWM based two-level VSI fed IM drive when the reference voltage space phasor



Approximate theoretical boundary of current error space phasor for VC-SVPWM based two-level VSI fed IM drive for position of reference voltage space phasor in Sector-1 for different operating speeds:

(a) 10Hz operation, (b) 20 Hz operation, (c) 30 Hz operation, and (d) 40 Hz operation

(a) (b)

(c) (d)


Parabolic Boundary for Current Error Space Phasor

Four unique Parabolas acts as boundary for current error in sector-I.

This parabolic boundary varies with the frequency.

These parabolas are characterised by the equations

For other sectors the boundary defined by these parabolas will remain the same, but their orientation will change.(i.e., the X axis and Y axis will change)

2x-h =4p y-k

2y-k =4p x-h


Vector Change Detection in Proposed Controller

The amplitude of Δi is monitored along A, B, C, jA, jB and jC axes for vector selection

The X axis and Y axis for parabolas for different sectors are shown in table given below


Vector Change Detection in Proposed Controller

VECTOR SELECTION FOR SECTOR- I (BASED ON INNER PARABOLIC BANDS) FOR FORWARD DIRECTION OF ROTATION OF MACHINE


Sector Change Detection in Proposed Controller

Current error during sector-1 to sector-2 change

Simulation Results showing the variation of current error along jA axis during sector change for constant frequency VC SVPWM based two level inverter (sector-3 to sector-4 change)



The property of the current error space phasor that it will change it’s direction along one of the orthogonal axes jA, jB or jC during a sector change is utilized.



Proposed sector change detection logic for forward rotation of machine

Present sector

Presentvector “ON”

Axis along which there will be change in direction of

current error during sector change

Forward Rotation

jA jB jC

1 V2 or V7 or V8 * * 2

2 V3 or V7 or V8 * 3 *

3 V4 or V7 or V8 4 * *

4 V5 or V7 or V8 * * 5

5 V6 or V7 or V8 * 6 *

6 V1 or V7 or V8 1 * *

(‘*’ means continue with the same sector)


Block diagram of the experimental setup


Simulation Results

10Hz operation for VC-SVPWM


Simulation Results &Experimental Results

Simulation & Experimental results at 10Hz operation for Proposed Hysteresis Controller


Simulation Results



Simulation Results

Simulation results at 10Hz operation for Proposed Hysteresis Controller


Simulation Results




Simulation & Experimental results at 30Hz operation for Proposed Hysteresis Controller


Simulation Results




Simulation results at 30Hz operation for Proposed Hysteresis Controller


Simulation Results

Simulation results for Proposed Hysteresis Controller in over-modulation and six-step mode


Simulation Results

Simulation results for Proposed Hysteresis Controller in six-step mode


Simulation Results

Acceleration of the IM from stand still to 10Hz in 2 sec

Acceleration of the IM from 30Hz to 50Hz (six step) in 2.5 sec.


Simulation Results

Speed reversal of the IM from 10Hz to -10Hz in 4 sec.

Acceleration of the IM from stand still to 25Hz in 3.2 sec. and sudden loading of 5Nm at 4 sec.


Conclusion

Switching frequency pattern similar to that of VC-SVPWM is obtained.

Proposed new sector change detection logic is self-adaptive and takes the drive to six-step mode.

It keeps all the inherent advantages of space phasor based hysteresis current controllers adjacent voltage vector switching etc.

cedt, indian institute of science, bangalore, india 1 a r educed s witch c ount 5- l evel i nverter...

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