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Cadence PhysicalVerification System

Cadence Physical Verication System(PVS) integrates with industry-standardCadence Virtuoso ® custom/mixed-signal and Cadence Encounter ® digitaldesign ows. This provides designerswith an end-to-end design and signoff

solution from a single vendor.PVS is a trusted solution that enablesusers to achieve advanced node designsignoff in a quick total turnaroundtime. It provides efcient, effectivedebug tools to reduce debug timeand increase productivity. Thissolution supports advanced processnode technology (such as doublepatterning, 3D-IC, and advanceddevice extraction), and it ex tendsphysical verication technologyinto design reliability checking and

constraint validation. PVS also offers adistributed multi-threading processingcapability that greatly acceleratesthroughput without requiringspecialized hardware.

Seamless integration with theVirtuoso platform

As an integrated component, PhysicalVerication System works seamlesslywithin the Virtuoso custom IC designplatform. Through interactive mode,PVS provides dynamic and real-timesignoff design-rule checking (DRC) for

every edit. Through in-memory/batchfull-signoff verication mode, PVS candirectly read in design data from theVirtuoso environment, which elimi-nates redundant Pcell evaluation andstream out. PVS can rapidly check thedesign to maximize productivity withwhat-if analysis. The results can beviewed and debugged with either the

Virtuoso Annotation Browser or withthe PVS Results Manager. Intuitive PVSdebug tools (Interactive Short Locatorand Graphical LVS Debug) are availablein the Virtuoso platform. They canverify designs by using the technologyconstraints, design constraints, andsignoff rule deck.

In-line integration with theEncounter platform

Within the Encounter digital imple-mentation platform, PVS can inter-actively verify the design by directlyaccessing Encounter data and standardcell data from the OpenAccessdatabase. This means designers caninvoke PVS and browse its error

Proven on many successful production tapeouts in nanometer process technologies, Cadence ® Physical Verication System is the premier Cadence signoff solution enabling in-design andback-end physical verication, constraint validation, and reliability checking. It offers competitivedistributed processing performance for advanced nodes, and its le compatibility and ease-of-usemake it a drop-in replacement for existing physical verication technologies. Designed to preservedesign intent, ensure design convergence, and deliver a predictable debug cycle, Cadence Physical

Verication System provides a faster path to nal signoff.

Cadence Physical Verication SystemIn-design and back-end physical verication for faster nal signoff

Virtuoso Custom

IC PlatformIn-Design PVS

Encounter

Digital PlatformIn-Design PVS

Standalone PVS Pre-Tapeout Signoff

Faster Turnaround Time

Higher Productivity

Tight Integration

Figure 1: Used either in-design or standalone, PVS enables efcient design, implementation,and foundry signoff closure


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Cadence Physical Verication System

markers without converting data fromthe Encounter design environment. UsingPVS, they can generate regular metalll and advanced timing-aware metalll using the signoff rule le. Designerscan launch the PVS Results Manager andintuitive debug tools within the Encounterdesign environment.

Benefits• Trusted solution with production-

proven accuracy

• Single-vendor solution for implemen-tation and pre-tapeout signoff

• Quick turnaround time from designto signoff through integration with

Virtuoso and Encounter design ows• Innovative technology to support

advanced process node design

• Reduced debug time with powerful andintuitive debugging tools

• Simplied migration through compat-ibility with industry-standard formats

• Cost-effective parallel computingsystems, eliminating the need forhardware modications

Features

Interactive and batch verication

Physical Verication System (PVS) worksfor both interactive and batch modes.Interactive physical verication, integratedwithin the Virtuoso and Encounterplatforms, helps designers preservedesign intent to ensure design conver-gence. PVS also operates in DFII andOpenAccess environments. Fur thermore,

PVS integrates seamlessly with CadenceQuickView Layout and ManufacturingData Viewer. It also runs standalone toverify the nished chip.

Virtuoso DRCTraditional DRC use models involvepackaging up the layout (i.e. GDSII) andinvoking a DRC run. This requires the datapreparation, launching of the job, andthen pushing any error data/markers backinto the layout view. Virtuoso DRC is anew capability that integrates PVS DRCtechnology with Virtuoso Layout Suitein a real-time mode. This convenient usemodel enables layout designers to runDRC using a signoff-level DRC deck asthey complete each edit.

Layout designers can also leverage thistechnology to do interactive editingchecks by using the OA tech le. Fullsignoff verication can be done at the

block and chip levels by using the fullyfoundry-qualied signoff deck, and itcan be run from Virtuoso memory space.Using Virtuoso DRC, layout designerscan perform design, implementation,and in-memory signoff checks withinthe Virtuoso environment. With correct-by-construction and dynamic detection/ verication of the editing geometries,this DRC technology speeds turnaroundtime, brings signoff condence to layoutdesigners, and ultimately improvesdesign quality.

Programmable ElectricalRule Checker

The PVS Programmable Electrical RuleChecker (PERC) reduces the risk of lowreliability and provides a platform totranslate the designer’s intent into a setof rules. The PERC uses the designer’srules throughout the whole developmentprocess, at pre- and post-layout stages.It identies the place with high reliabilityrisk in the early stage of development,and it checks that the solution usedto reduce reliability risk satises thedesigner’s netlist-based and layout-basedrequirements.

The PVS PERC can be applied to nd ESDunprotected devices and pads, to checkthe ESD protection structure, and to ndcross-power domain interface struc turesand check them. The PERC can be usedto nd common errors (such as oatinggates or prohibited power domains) in the

Figure 2: The Virtuoso GUI displays the DRC debug environment

Figure 3: Virtuoso DRC technology


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pre-layout stage. It can also be used toverify that third-party IP blocks satisfy thedesigner’s reliability standards.

Constraint Validator

The PVS Constraint Validator shortenstotal turnaround time and improvesdesign quality by detecting design errorsin the very early stages of the IC devel-opment process, and by validating thedesign at the nal stage. This new PVStool is able to verify the correctness ofcreated layout according to speciedconstraints. For example, whether allnets that should be routed symmetricallyare indeed symmetrical, or whether halodistance is being taken into account. The

Constraint Validator can detect errors inthe implementation stage that conven-tional tools would only reveal during thevery last parasitic extraction stage (i.e.,symmetrical layout impacted by neighborparasitic effect). The Constraint Validatoris also used in the Cadence mixed-signalow to ensure mixed-signal routingintegration constraints are implementedcorrectly by the router.

Predictable debug cycle

Designers often spend more time ondesign rule checking (DRC) and layoutversus schematic (LVS) debugging. Theunpredictable debugging time cancause delays in schedule, leading toloss of product revenue. PVS providestwo innovative debug solutions to helpdesigners nd and x design issues in aforeseeable time period.

Interactive Short Locator

Shorts, especially power/ground shorts,are the most difcult debug issues.The PVS Interactive Short Locator facili-tates one-pass short isolation to deliveran efcient and intuitive LVS debugsolution that helps designers quicklydetect and solve short issues. Designerscan start debug analysis while the run isin progress, as soon as rst results areavailable.

Graphical LVS debug

Identifying the causes of complex LVSmismatches is extremely time-consuming.The PVS Graphical LVS Debug solutionaccelerates identication of complexLVS mismatches in cell /block designs.By showing all errors and warnings ina consistent and simplied graphicalview, users can easily debug complexLVS mismatches and identify differencesbetween schematic and layout infor-mation. PVS also features the industry’srst Verilog-compatible netlist-based LVSdebug capability.

Error results visualization andmanagement

The PVS Results Manager provides aneasy-to-use, interactive error-navigationsystem to efciently review, waive, andcorrect physical verication issues. The

Results Manager can be launched withinVirtuoso and Encounter environments. Aninterface with a high-performance, high-capacity design data viewer—CadenceQuickView—enables PVS users toefciently debug extremely large system-on-chip (SoC) designs with design-lesizes in the tens-of-gigabytes range.

Competitive performance for designthroughput

PVS delivers multi-processor perfor-mance that is highly competitive with

other physical verication solutions.Large designs can also take advantageof the PVS distributed multi-threadingprocessing architecture that leverageslow-cost, off-the-shelf compute platformsto greatly accelerate design throughput.

Drop-in compatibility with industry-standard formats

All PVS rule les and output les arecompatible with industry-standardformats. This allows PVS users to leveragetheir existing investments in rule decks

and infrastructure with less effort fortranslation or scripts. Rule decks executenatively on PVS, and PVS reports designerrors in an intuitive, predictable, andfamiliar way. This greatly accelerates tooland ow validation and integration.

Conventional Short Isolation

PVS Interactive Short Isolation

ERC Run Debug

ERC Run Debug

Run Debug

Run Debug

ERC Run Debug ERC Run Debug

3 hrs 8 hrs

One-Pass Closure = 2x Productivity

Figure 4: The Interactive Short Locator improves productivity by at least 2x

Figure 5: The Virtuoso GUI shows the graphical LVS debug environment


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Cadence is transforming the global electronics industry through a vision called EDA360.With an application-driven approach to design, our software, hardware, IP, and services helpcustomers realize silicon, SoCs, and complete systems efciently and protably. www.cadence.com

© 2012 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Encounter, and Virtuoso are registered trademarksof Cadence Design Systems, Inc. All others are properties of their respective holders.

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QRC ow compatibility

PVS can accelerate the physical veri-cation cycle time by streamlining thepost-layout simulation ow. It supportsCadence QRC Extraction ows, andprovides the TECHLIB set-up feature to

make the PVS-to-QRC parasitic extractionow easy to use. Both GUI and batchsupport are provided for SPICE, SPEF,DSPF, and extracted v iew outputs fromQRC Extraction.

Signoff-ready, production-provensolution

PVS is production-proven, with hundredsof successful customer tapeouts inadvanced nanometer process technol-ogies from multiple foundries.

Cadence Services and Support• Cadence application engineers can

answer your technical questions bytelephone, email, or Internet—theycan also provide technical assistanceand custom training

• Cadence certied instructors teachmore than 70 courses and bringtheir real-world experience into theclassroom

• More than 25 Internet Learning Series(iLS) online courses allow you theexibility of training at your owncomputer via the Internet

• Cadence Online Support gives you24x7 online access to a knowledgebaseof the latest solutions, technicaldocumentation, software downloads,and more

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