cathode strip chamber (csc) trigger primitive time synchronization

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7 May 2009 G. Rakness (UCLA) 1 Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization For the CSC Synchronization Taskforce: Greg Rakness University of California, Los Angeles CMS Electronics Week CERN 7 May 2009

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Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization. For the CSC Synchronization Taskforce: Greg Rakness University of California, Los Angeles. CMS Electronics Week CERN 7 May 2009. Some details specific to CSC. CSC Readout  CSC Trigger. - PowerPoint PPT Presentation

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Page 1: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 1

Cathode Strip Chamber (CSC) Trigger Primitive Time

Synchronization

For the CSC Synchronization Taskforce:

Greg Rakness

University of California, Los Angeles

CMS Electronics Week

CERN

7 May 2009

Page 2: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 2

Some details specific to CSC

Page 3: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 3

CSC Readout CSC Trigger

• CSC “zero-suppression” implemented by reading out data from a chamber which has a coincidence of

(L1A * Local Charged Trigger)

CSC must trigger in order to readout

This requires timing in the L1A to be coincident with the (delayed) LCT before data can be taken

Changes in the L1A latency require changes in L1A coincidence window timing

Page 4: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 4

Short CSC Synchronization History• Autumn 2006: CSC synchronization taskforce

created– https://twiki.cern.ch/twiki/bin/view/CMS/

CSCsynchronization• Summer 2007: Initial synchronization procedure

developed using cosmic rays on minus-side slice test– L1A coincidence windows opened up to 7bx on ALCT

and TMB• Note: Final goal = 3bx windows

– Trigger timed in on average– L1A coincidence window timing found

• 2008: Synchronization procedures used during commissioning of CSC’s in UXC

Page 5: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 5

Trigger Channel Relative Synchronization

Trigger Channel = CSC chamber

Page 6: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 6

CSC Trigger Primitive Relative SynchronizationOffline analysis of Local Charged Triggers at Sector Processor:

Plot bx for events with coincident LCTs for each chamber combination

(bxchamber A – bxchamber B)

CSC Local Run#539

S2C5-S3C6 S2C6-S3C5 S2C6-S3C4

S2C7-S3C6 S2C7-S3C8S2C8-S3C7

S2C8-S3C7 S2C9-S3C8

D. Wang (UF)

… extract centroids and errors of each distribution to form a matrix of chamber-to-chamber relative synchronization…

Some distributions:

Page 7: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 7

Relative Synchronization between Different Trigger Channels

D. Wang (UF)

Relative timing for chambers which trigger on the same cosmic ray muon is within ~0.15bx

Page 8: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 8

Adjustment of sampling time with respect to beam

During CRUZET-3 a shift of 50 ns was implemented for strip signals.

A. Kubik (Northwestern)

Page 9: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 9

Synchronization of Serial Links

Page 10: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 10

Serial Links in the CSC system• Serial links in the CSC system transport

information from UXC USC over optical fibers of different lengths…– Trigger path:

• Muon Port Card (CSC trigger primitive) Sector Processor (CSC Track Finder)

– Clock and BGo commands:• TTCci Clock and Control Boards (CCB)• CCB’s are in every CSC TF and CSC crate• TTCrq mezzanine board on CCB receives and interprets

clock and BGo commands• CCB distributes clock and BGo commands to system

Page 11: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 11

Synchronizing Serial Links: Cold Start

• At power-up, the TTCrq must be configured to set the delays and to correctly interpret BGo commands, using:– I2C (via VME in each crate)– “Broadcast long 0” (from TTCci)

Time for cold start ~ 5 minutes

Page 12: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 12

Synchronizing Serial Links: Warm start

• At TTC “Resync,” MPC sends stream of negative signals • Sector Processor firmware contains “Asynchronous FIFO” which

automatically aligns signals from all MPCs to correct for optical fiber differences in 80MHz steps of AFD delay (L. Uvarov, PNPI)

Fiber lengths from MPC to Sector Processor are equalized, assuming that TTC CCB fiber lengths are equal

CCB

MPC SP

TTC

Clock and Control Board

Timing, Trigger & Control Board

Muon Port Card

Sector Processor

Page 13: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 13

AFD Delay vs. MPCSP fiber length

J. Hauser (UCLA)M. Ignatenko (UCLA)

Follows “staircase” pattern, as expected for 80MHz AFD granularity

Page 14: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 14

Synchronization of Trigger Data with BC0

• The synchronization procedure established in 2007 has a specific order to achieve – Trigger synchronization– L1A coincidence timing

• Furthermore, TTC clock and signal distribution is needed…

• Now BC0 synchronization is becoming a priority for CSC

• The handles we have to make adjustments include… – Greg, fill in parameters from TMB and ALCT

Page 15: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 15

Topics to Cover

• Methods used for validation of the time synchronization with… – Test patterns – Cosmic ray data

Slide needs work…

Page 16: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 16

Latency

Page 17: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 17

CSC trigger latency• Currently have…

– Detailed breakdown of TMB latency at• https://twiki.cern.ch/twiki/bin/view/CMS/CSCTrigge

rLatency

– Measurements of trigger signals compared with other subdetectors, such as RPC and DT…

Page 18: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 18

Position of RPC data in TMB FIFO

Time (bx)

Ring +1/2

CLCT pretrigger

4 – 5 March 2009

MWGR

Position of RPC data in TMB FIFO = 4.7bx

… position of RPC data relative to the CLCT pretrigger = 2.7bx

Position of RPC data in TMB FIFO + CLCT pretrigger latency – RAT latency 2.7 + 17.4 – 7.7

RPC latency = 12.5bx

Page 19: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 19

RPC EstimateFrom a latency review in Nov. 2007:

• 1 = chambers + FEBs • 4 = cables • 3 = synchronizer• 2 = coder • 1 = slave-master transmission • 0 = data delay • 2 = muxer • 13 = TOTAL compared with 12.5bx

Data consistent with combination of • CLCT pretrigger latency estimate• RPC LB estimate• RAT latency estimate

Can any delay be removed from RPC Link Board firmware? …Same exercise should be performed for DT CSC trigger primitive exchange…

7

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7 May 2009 G. Rakness (UCLA) 20

How to go from cosmic rays to collisions…

• Open up the L1A coincidence window for the CFEB

• Trigger on the bottom

Slide needs work…

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7 May 2009 G. Rakness (UCLA) 21

Tools to monitor time synchronization

• During data taking…

• Actions to be performed on errors…

Slide needs work…

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7 May 2009 G. Rakness (UCLA) 22

Backup Slides

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7 May 2009 G. Rakness (UCLA) 23

Topics to Cover• Summary of the mechanisms in place to allow and guarantee time

synchronization…– Adjustment of sampling time with respect to beam – Time alignment between data of different trigger channels in the

subsystem – Synchronization of data with BC0 signal

• Procedures used to establish synchronization of serial links used in the system: – Cold start – Warm start

• Methods used for validation of the time synchronization with… – Test patterns – Cosmic ray data

• Methods used to validate the total latency of the trigger subsystem• Tools used for monitoring of the time synchronization during data

taking and actions taken on detected errors.

Page 24: Cathode Strip Chamber (CSC) Trigger Primitive Time Synchronization

7 May 2009 G. Rakness (UCLA) 24

CLCT Pretrigger Latency Estimate

• CFEB drift delay to last hit of 6 layers expected = 3.0– CMS setting assumed, CLCT lose ~10% of 6th hits, lower thresholds help

• Signal propagation on strips and CFEB cables = 0.8• Preamp latency = 1.0• Comparator delay for peaking time = 2

– Configurable parameter: should study comparator and CLCT efficiency vs. value• Comparator latency, clock to first triad = 2.0• CFEB mux to triads = 1.5• Average Skew Clear delay for ME+1/2-3 CSC’s = 2.1

– Computed based on cable lengths + revision type• TMB triad demux/synchronization = 0.0• TMB triad decoding to ½-strips = 2.0• TMB one-shots/pattern-matching = 2.0• CLCT pretrigger = 1.0

CLCT pretrigger latency = 17.4 bx

Starting from J. Hauser (UCLA) spreadsheet, using current TMB documentation, removing (common) Time-Of-Flight

3/17/2009 12Laria Redjimi CMS Trigger meeting

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7 May 2009 G. Rakness (UCLA) 25