calibration of current steering d/a converters - eindhoven...
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![Page 1: Calibration of Current Steering D/A Converters - Eindhoven ...alexandria.tue.nl/openaccess/Metis233129.pdftechnische universiteit eindhoven Self-calibration of MSB unary currents measurements](https://reader035.vdocuments.us/reader035/viewer/2022070212/6104755d6cabd577b84d13cb/html5/thumbnails/1.jpg)
Calibration of Current Steering Calibration of Current Steering
D/A ConvertersD/A Converters
ir. Georgi Radulov1, dr. ir. Patrick Quinn2, dr. ir. Hans Hegt1,
prof. dr. ir. Arthur van Roermund1
1Eindhoven University of Technology
2Xilinx
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Current-steering D/A converters
Applications demand performance;Applications demand performance;
Errors limit performance;
Small errors demand huge resources.
Correction methods:
Improve performance and
Relax design requirements
2
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Overview
• Mismatch problem;
• Current calibration method;
• MSB unary currents calibration in a 12b 250nm DAC
• All (MSB unary and LSB binary) currents calibration in a
quad-core 12b 180nm DAC;
• All currents calibration in a 12b-16b flexible 40nm DAC
• Conclusions
3
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Mismatch problem
• Elements’ real values deviate
• Deviation depends on:
– Area
– Tech. and Circuit parameters
• High resolution D/A require
I
PDF(I)
I
IMEAN
2Kσ
∼
4
• High resolution D/A require
– Many and accurate elements
– Large silicon areas
• Large silicon areas cause
– Systematic errors
– Drop of performance
( )I
I K
W LI
σ ×
∼~
maxIINL
In
σ⋅
∼~
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Ioffset
1-bit
ADCφφφφA: open φφφφA: closedFSM
Start-up calibration scheme
• Mismatch correction;
• Input offset cancellation;
• Two phases: φA, φB; ADC
ItempIrefIth(i)
temp
CALDACCALDAC(i)
φφφφA: open
φφφφB: closed
φφφφA: closed
φφφφB: openφA: Itemp=Iref - Ioffset;
φB: Ith(i)=Itemp + Ioffset=Iref;
with Iref=ΣIbin + ILSB;
• Simple logic: 8-state FSM.
5
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12bit self-calibrating DAC in 250nm CMOS,
see ESSCIRC’05
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• 12b current-steering DAC;
• Segmentation: 6LSB/6MSB;
• 63 thermo bits calibrated;
12bit DAC implementation
• 6 binary not calibrated;
• Reference: binary bits;
• 5bit signed CALDACs;
• CMOS 0.25µm; Vdd 2.5V.
7technische universiteit eindhoven
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Chip micrograph
Latches
&
Decoder
Latches
&
Decoder
Input
drivers
• CMOS 0.25µm, 1P5M;
• Coarse (main) current
sources designed for 10b
accuracy in 0.1mm2;
1.16mm
Coarse current sources
Array of CALDACs
FSM & 1bit ADC
Decoder Decoder accuracy in 0.1mm ;
• Fully integrated self-
calibration in 0.3mm2;
• 5 extra pads for calibration:
4 in & 1 out;
8
Cascodes M2, M3a, M3b
0.9
8m
m
technische universiteit eindhoven
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Self-calibration of MSB unary currentsmeasurements
SFDR = 81dBSFDR = 68dB
9
Before calibration After calibration+13dB
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Self-calibration of MSB unary currentsmeasurements
HD (2,3,4,5)
(max) improvement +18dB
SFDR
improvement +13dB
10
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Calibration potential
Distribution before calibration
• 3.5 LSB span, σ=1.06LSB;
• Tech. and design tolerances;
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Distribution after calibration
• 0.2 LSB span, σ=0.03LSB;
• Calibration step sets the span;
technische universiteit eindhoven
Unary
currents:
+4 bits
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-1.5
-1
-0.5
0
0.5
1
1.5
2
INL
[L
SB
]
2
• MSB unary part
dominate;
• INLmax = 1.5LSB;
Before
10b
Static performance
INL:-2
0 500 1000 1500 2000 2500 3000 3500 4000
Digital code
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 500 1000 1500 2000 2500 3000 3500 4000
INL
[L
SB
]
Digital code
After
12b
• LSB non-calibrated
binary part dominate;
• INLmax = 0.4LSB
12technische universiteit eindhoven
INL:
+2b
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Calibration of binary currents
Binary � no redundancy
New sub-DAC segmentation (M binary sets) �
redundancy
_
_
1
_
1
1
_
1
_
( )(1)
( )(2)
( )(
1: ( )(1) 1 :
2 : ( )(1) 1 :
1) ( )(2: :)3
ref bn
ref bn
B
bin ref u
i
I
B
bin ref u
bin
bin
b
i
I
refb n uin i
I i LSB I
I i LSB I
I
I B
I B
I B I B
−
=
−
=
+ + =
+ + =
+ =
∑
∑
��
���������
��
���������
��
13
equal
1/2
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12b-14b self-calibrating flexible DAC in
180nm CMOS,180nm CMOS,
see APCCAS’08
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Parallel sub-DAC units architecture
Current-steering DACs:
Parallel current sources (switch current cells),
which are switched in groups to create the
analog output;
a) Unary (Thermometer) grouping;
15technische universiteit eindhoven
b) Binary grouping;
c) Segmented grouping;
d) Our NEW grouping: parallel sub-DACs
(with an exemplary implementation).
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A 12-bit self-calibrated quad-core
current-steering DAC
recall:
1mm2 for the
presented 12b DAC
(250nm CMOS)
16
0,2mm2
per 12b DAC
(180nm CMOS)
(250nm CMOS)
-Large LSB binary part;
-Full calibration.
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Calibration of unary and binary currents, measurements
Before calibration After calibration
INL
17
Before calibration After calibration
DNL
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Calibration of all DAC currents, measurements
DAC accuracy depends only on a design parameter
18
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Calibration of all DAC currents, dynamic measurements
SFDR = 80dB
19
SFDR = 75dB
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12b-16b self-calibrating flexible DAC in
40nm CMOS,40nm CMOS,
unpublished yet
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A 12b-16b self-calibrated flexible DAC in 40nm CMOSA
nalo
g o
utp
ut Construction of the full transfer characteristic
Off-chip
calibration
engine;
Flexibility;
A
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A
BCDEFGHIJKLM
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BCDEFGHIJKL
M
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BCDEFGHIJK
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H
A
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G
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BCDE
F
A
BCD
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BCDEFGHIJKLMNOP
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MNOP
NOP
OP P
BOLD - sub-DACs set to full-scale ‘1’.Italic - sub-DACs convert the12 LSB input data;Narrow gray - sub-DACs set to full-scale ‘0’;
Digital input
Analo
g o
utp
ut Construction of the full transfer characteristic
12b output
12b output
14b output
13b output
15b output
0.047mm2 per
12b sub-DAC
(recall: 1mm2
for 250nm;
0.2mm2 for
180nm)
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+5 bits
Calibration of all DAC currents, INL & slow signals measurements
Before:
SFDR = 59dB
After:
SFDR = 79dB
+4 bits
Before:
SFDR = 63dB
After:
SFDR = 80dB
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Calibration of all DAC currents, dynamic measurements
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Conclusions
• Calibration:
– improves performance;
– relaxes design requirements;
– reduces product risks;
• 3 test-chip demonstrated:
– aggressive analog area reduction;
– high current accuracy;
– analog performance supported by digital.
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Acknowledgements
Xilinx Ireland, Mixed-Signal Design Group
25
Xilinx Ireland, Mixed-Signal Design Group
Financial support of Dutch Tech. Foundation STW
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Thanks for attention!
26
Discussion
technische universiteit eindhoven