cahcegane.pdf

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Memory Address

TAG LINE WORD

4bit

2bit

2bit

IMPLEMENTATION OF DIRECT MAPPED CACHE , IN BEHAVIORIAL VERILOG

ECE254 ASSIGNMENT 1 NEERAJ DHOTRE (perm:5483615)

1.

Introduction:Memory hierarchy is imperative due to prevalent highly pipelined and super scalar architectures. As main memoryaccess is lot slower compared to other tasks in the pipeline, data and instructions are stored closed to the processor ina small and comparatively faster memory, called cache. The main aspects of cache design are cache size, memorymapping function, write policy and replacement algorithm. In a direct mapped cache each block of memory ismapped to a particular row in the cache. The mapping function is simple to implement but performance of this typeof cache is not the best. The synchronization of the cache with main memory, handling read miss and write miss etc.make direct mapped cache a good candidate for this assignment, aim of which is to learn Verilog modeling anddesign simulation with Model Sim.

2. Cache Design:

2.1 Assumptions:The cache is designed with the following assumptions.

This cache lies between the Processor and the Main memory. The cache and processor run on the same fast clock. Main memory is a single port synchronous DRAM running on a slower clock.(4 times slower) Processor sends physical address to the cache. Processor sends/requests one word data (32 bits wide) at a time. The cache implements write through write policy with No write allocate i.e. on a write miss

data is written only to main memory.

2.2 Cache and Main Memory Size:To keep the cache size, memory size, data with etc. flexible for any cache module instance parameters are used.

Parameters define constants which can be changed during instantiation. The main parameters with the valuesspecified were used for simulations in this assignment.

parameter ADDR_SIZE = 8; meaning 8 bit address and 2 8 Main memory locations. parameter DATA_SIZE = 32; meaning processor is 32 bit and each main memory location is 32bit making it

256 x 4 byte or 1024B memory.

parameter LINE_BITS = 2; meaning 4 lines in the cache. parameter LINES = 1


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Cache Memorydata 8

rd_en7 addr

clk

reset

Chip_select

mem_addr

mem_wr

mem_data

rd_done

wr_done

8

busy

data_valid

2.3 Block Diagram:

The block diagram is shown in figure 2. Behavioral model is written for the cache and main memory blocks.The signals from processor are given as stimulus is tech bench. Table 2 lists the ports of cache.

Figure 2. Block Diagram showing signal connections.

Port Direction Descriptionclk input Common clock between cache and processor reset input Synchronous reset to the cacherd_en input HIGH for read from cache LOW for write to cachedata [31:0] bidirectional Data from/to processor Direction determined by rd_enaddr[7:0] input Address from the processor data_valid output Active high signal indicating output data to processor is valid

Busy output Active High signal indication that cache is busy. Processor will not send another request when cache busy.

mem_addr[7:0] output Address bus to main memorymem_wr output HIGH for read from main memory LOW for write to main memorychip_select output Signal to enable main memory accessmem_data[31:0] bidirectional Data from/to main memoryrd_done input Signal from main memory that requested read operation donewr_done input Signal from main memory that requested write operation doneTable 1. Ports of cache with direction and descriptions.

Processor

Cache

Cache memory

tag word 1 word 2 word 3 word 4

Main Memor


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Register Size Descriptioncache_hit_reg 1 bit Indicates a tag match, meaning requested address present in cacheline 2 bit To store line index to cache from input addresstag 4bit To store location tag from input address count 2 bit To keep track of number of main memory reads in case of read missdata_out 32bit Registered data out before driving it onto the bidir data bus to processor mem_data_out 32bit Registered data out before driving it onto the bidir data bus to Memorymem_data_reg0 to 3 32bit 4 registers to store data words read in from main memoryTable 2. Internal registers used in the behavioral model

3. Verilog Implementation

3.1 Verilog codeThe verilog code for the cache is given in appendix A. The design is implemented in 6 always blockswhich execute simultaneously. There are 2 combinational blocks and 4 sequential blocks. These blocks dothe following logical tasks and together model cache behavior.

3.1.1 Combinational Blocks:

I. Tag comparison: This block always checks weather the tag of line mentioned in input addressmatches with that in the address. It sets the cache_hit_reg if there is a tag match irrespective of reador write operation

II. Memory select: This blocks controls the enabling of Main Memory. The Main Memory needs to be enabled only when data is needed to be transferred to/from it. This gives better control over therd_done and wr_done signals given out by the Main Memory.

3.1.2 Sequential Blocks:

I. Cache Hit: Only if Tag comparison is successful this block executes and does the required datamanipulation.

II. Cache Miss : Only if Tag comparison is un successful this block executes and does the required datamanipulation.

III. Data Synchronizing from Memory: There two blocks, one runs on posedge clk and other on posedgerd_done. These are required to synchronize the reads from memory in case of a read miss, as cacheand memory run at different asynchronous clocks.

3.2 Test benchThe test bench code is present in appendix C. The test bench runs 4 test cases to test the functionality of the direct mapped cache. The clk signal is given a period of 10ns and mem_clk period is 40ns


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1) Write Miss: Initially there is nothing in the cache or Memory. Processor issues 4 writes toconsecutive memory locations all of which result in a cache write miss. The data is written only to mainmemory. As seen in the waveform data 56,57,58,59 were written to memory location 120,121,122 and123 respectively. Cache_hit_reg signal was always low meaning a cache miss and proper busy pulseswere given to the processor form every right.

Figure 3. Wave forms showing Cache write miss test case.

2) Read Miss: Now the test bench requests the data written in the previous step. This resultsin a read miss and cache brings the data from main memory. In this case as the memory has onlyone word at each location, cache has to do 4 reads to get a block of data and replace a line. Asseen in the waveform in figure 4 the processor requests data at location 120 resulting in a readmiss. This triggers 4 reads from main Memory. Required data is given to processor withdata_valid and the cache line 2 is written with 4 words (56,57,58,59).


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Figure 5. Wave forms showing Cache read and write hit test case


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4.

APPENDIX A CACHE Verilog code./*######################################################################---------------------------SIMPLE DIRECT MAPPED CACHE---------------------------Input address is broken like this [----TAG----| -----LINE------|---WORD----]

TAG ---> cache tagLINE --> index for the line in cache. 2^line = number of lines in cacheWORD --> bits to address word in cache line. 2^word = number of data words in cache line.

######################################################################*/

module cache (clk, //clock. same as cpu clock.addr, //address from cpu.rd_en, //HIGH for read from cache.LOW for write to cache.data, //bidir data from/to CPUmem_addr, //address to main Memory.mem_wr, //HIGH for write to Memory.LOW for read from Memorymem_data, //bidir data to/from main Memoryrd_done, //read done signal from main Memorywr_done, //write done signal from main Memorydata_valid, //Signal telling CPU data is valid to read.

busy, //telling CPI cache busy when read miss.reset, //reset to cache.chip_select //select signal to enable memory.);

parameter ADDR_SIZE = 8; parameter LINE_BITS = 2; parameter LINES = 1


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reg [DATA_SIZE-1:0] mem_data_out;reg [DATA_SIZE-1:0] mem_data_reg_0;reg [DATA_SIZE-1:0] mem_data_reg_1;reg [DATA_SIZE-1:0] mem_data_reg_2;reg [DATA_SIZE-1:0] mem_data_reg_3;reg cache_hit_reg;reg [LINE_WIDTH-1:0] memory [LINES-1:0];reg [LINE_WIDTH-1:0] line;

reg [LINE_WIDTH-1:0] tag;

wire [LINE_BITS-1:0] line_index;

assign line_index = addr[(WORD_BITS+LINE_BITS)-1:WORD_BITS];assign data = (rd_en) ? data_out:{DATA_SIZE{1'bz}};assign #5 mem_data = (!rd_en && chip_select) ? mem_data_out:{DATA_SIZE{1'bz}};

always @ (rd_done or wr_done or count ) begin

if (rd_done || wr_done && count == 2'b00) begin

chip_select = 1'b0; busy = 1'b0;

endelse if (!rd_done && !wr_done && (count != 2'b00) ) begin

chip_select = 1'b1; busy = 1'b1;

endend

//storing data red from main memory.always @ (posedge rd_done) begin

if (count == 2'b11) begin

count


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mem_wr


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always @ ( posedge clk )

beginif( wr_en && chip_select ) begin

memory[addr]


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