cadence spb: what’s new in 16.6 qir 5 (hotfix 22) · cadence spb: what's new in 16.6...

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5

Cadence SPB: What’s New in 16.6 QIR 5 (HotFix 22)

This document describes the new features and enhancements in Cadence® SPB products in 16.6 Quarterly Incremental Release (QIR) 5. The products covered are:

■ Allegro PCB Editor

■ Cadence SiP Layout and Allegro Package Designer (APD)

■ Allegro Design Entry HDL

■ Virtuoso SiP Architect

■ Allegro FPGA System Planner

■ OrCAD Capture

■ Cadence PSpice

© 2014 Cadence, Allegro, OrCAD, PSpice, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and/or other jurisdictions.

January 2014 11 Product Version 16.6

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Allegro PCB Editor

Allegro PCB Editor

This document describes the new features and enhancements in Allegro® PCB Editor16.6 QIR 5.

■ IPC-2581 Rev B Support on page 13

■ Interface Aware Design (Design Planning Option) on page 14

■ Route Interconnect Optimization on page 17

■ Productivity Enhancements on page 20



IPC-2581 Rev B Support

The 16.6 QIR 5 release begins the Allegro PCB Editors support for the IPC-2581 Rev. B format. Attributes and properties related to Assembly and Bill of Materials have been implemented to address:

■ Package Pin one identification: This requires that a property (PKG_PIN_ONE) attached to a pin indicates the primary pin of the footprint. This primary pin may be the actual pin 1, or may be the pin that identifies the pin for anode, positive, A1, Collector, and so on.

■ Package Pin One orientation: The property PKG_PIN1_ORIENTATION is assigned to a board or symbol drawing to designate the established zero (0) orientation for symbol rotation.

■ Polarity Marking: A new property MARKING_USAGE is attached to a symbol or drawing element (line/circle) to indicate the marking type required in IPC-2581.

■ IPC-2581 Configuration file: The configurations file contains BOM header information to populate data fields such as BOM name, revision, contact information, and so on.

For more information about IPC-2581 or Consortium updates, visit, http://ipc2581.com.


http://ipc2581.com


Interface Aware Design (Design Planning Option)

Today’s complex Interfaces such as DDRx present interconnect challenges for PCB Designers. Allegro tools have significantly advanced over the previous 16.6 quarterly increment releases to help increase productivity specific to timing aware routing. The suite of tools is referred to as ATE or Allegro Timing Environment which includes Timing Vision, Auto Interactive Phase Tune and Auto Interactive Delay Tune.

The Net-Group constraint object was introduced in the base 16.6 release targeted at replacing the Bus object. In a DDR3 memory system the signals can be divided into 4 groups: ADDR/CMD, CTRL, CLOCKS and DATA. The largest group, DATA, can be further broken down into sub-groups called Byte-Lanes. These Byte-Lanes lend themselves to be Net-Groups of their own while still remaining part of the bigger group called DATA.



Nested Net-Groups

In QIR 5, the Net-Group object supports this functionality in Constraint Manager by allowing one Net-Group to be a member of another Net-Group the same way DP+ and DP- are part of a Diff Pair object.

Interface Visibility

Net-Groups use special graphics to help you visualize the area that the nets of the group will consume. This helps you visualize space requirements for the interfaces in your design.



Net-Groups can be used as placement aids due to the polygon shape. The shape of the polygon encompasses the pins of the nets involved in the Net-Group. When you place or move components, the polygon will change shape dynamically and this lets you see polygons with odd shapes due to components that are not in the proper placement relationships for your interface. For example, a terminator that got pushed to the side would create a bulge in the view and you can find the component that is out of place.

View the different levels of the Interface structure from Top Level down to ratsnest using the Interface Visibility All command.



Route Interconnect Optimization

■ Scribble Mode Routing on page 17

■ Auto-Interactive Phase Tune update on page 18

■ Edit Vertex – Snap to 45 on page 18

■ Dynamic Rat Suppression on page 19

Scribble Mode Routing

Scribble is a simple routing mode that allows the user to scribble a route path onto the canvas. Once a click is made, the etch solution for the scribble path will be generated.

Scribble provides a quick two pick methodology to generate complex route paths, along with a very controlled usage of push/shove based on the scribble path.

The Scribble function is available from the pop-up menu when using the Add Connect command. Consider using the TAB key to toggle between conventional and scribble routing.

Scribble remains an unsupported prototype at this time and therefore requires enabling of the Unsupported Variable Enable Add Connect Scribble. Access to the variable setting is from the Route – Unsupported Prototypes menu.



Auto-Interactive Phase Tune update

New option Uncoupled Bump Creation now permits the use of accordion bumps for phase tuning Diff Pairs. Sawtooth Bumps remains the default style bump for the AiPT command.

Edit Vertex – Snap to 45

The Edit Vertex command now supports a new option to snap off angle routes onto 45 degree angles. This may be useful after moving components with the stretch etch option enabled. Often the results of this action produce routes on undesirable angles.

This new command option requires the enabling of the Enable Edit Vertex 45 Snapping variable located in Route – Unsupported Prototypes menu. Once enabled, the Snap to



45 will become available in the option’s panel. Note the CTL key can be pressed to toggle the behavior.

Dynamic Rat Suppression

When manually routing, you may wish to hide all rats to improve visibility as it relates to your routing path. Setting the variable, acon_auto_rat_blank will temporarily blank all rats during the Add Connect command.

All Rats Displayed Dynamic Rat Suppression

Use of Edit Vertex to adjust off-angle route to 45 degree angle



Productivity Enhancements

■ Move Component – Slide Etch on page 20

■ Split Views on page 21

■ Drafting Updates on page 21

■ Snap Pick Updates on page 22

■ Named Text Blocks on page 22

■ PADS Translator Updates on page 23

■ Layer-Based Optimization for bundle nets on page 23

■ Unsupported Prototype Functionality on page 24

Move Component – Slide Etch

The Move command has been enhanced to support a new Slide Etch option. When moving components with attached routes, the desire is to maintain the segments on octalinear angles. Prior to this release, the Stretch Etch option was the common method for moving routed components however the results were not desirable and required manual edits to restored the intent.

In 16.6 (QIR 5), the Move Component – Slide Etch functionality is offered as a prototype. Invoke the Move command then select Slide etch (prototype) from the options panel. Since the functionality is considered prototype, acknowledge the disclaimer. Click Do not show again to prevent this form from re-appearing during subsequent move operations.



Split Views

The Split View technology is a new capability that was introduced in 16.6 QIR 3 and allows the user to view another area of the design canvas, while still working with the standard main editing canvas. This technology is extremely effective for breakout routing solutions, where you can now see both end of the bus/interface and make decisions/edits to both ends at the same time. In 16.6 QIR 5, both split windows are now editable!

Drafting Updates

Two new commands have been added to the suite of drafting commands introduced over the 16.6 QIR releases. The new commands are:

Relative Copy & Move

These commands allow users to make copies of a variety of objects mirrored from the original(s) relative to a line. When invoked from the menu, the options dialog in the Allegro mini-status area is updated to provide a Relative Mode field that controls the line around which the copies should be mirrored, and the user is prompted Select object(s) to copy.



Horizontal Line or Vertical Line indicates that the mirror line will be fixed as such, whereas Odd Line provides for mirror lines at other angles.

Once objects are selected, the user is prompted for an origin point. Once this is provided, the potential object copies become dynamically visible in the canvas, and the user is asked to make one further pick to establish the actual point for the new objects, at which time the copies are created. At this point the command can continue by copying more objects or finish with Done/Cancel from the pop-up menu.

Relative Move works the same as Relative Copy, except that it provides a move rather than copy operation.

Snap Pick Updates

Three new options have added to the Snap Pick to command:

■ Pad Edge Vertex

■ Pad Edge Midpoint

■ Pad Edge

Named Text Blocks

Text blocks can now be identified by functional names such as Silk, Comp, and so on. Previously, a text block was identified by a non descriptive block integer.



PADS Translator Updates

GUI and use model improvement for PADS_IN layer mapping functionality has been made in QIR 5. The summary of changes include:

■ Reworked layer mapping controls to make it more usable.

■ Added separate tabs for each object type.

■ Load only those layers that are in ASCII file that reduces layer count.

■ Use actual PADS layer names in mapping table.

■ Added automatic layer mapping for all non-etch layers (solder, assembly, etc).

In addition, a new PADS Library translator is now available. The command is located in the File – Import – CAD Translators menu.

Layer-Based Optimization for bundle nets

The FSP - Allegro integration flow has been enhanced to support layer-based optimization.

You can now change the layer of individual nets of the bundles using Sequence – Edit – Change Layer menu. This command becomes available by enabling Route – Unsupported Prototypes – Enable Auto-Interactive breakout.

With FSP running in the background, you can perform pin-out optimizations on the bundle nets that are assigned to multiple layers.



Unsupported Prototype Functionality

PCB Editor users are reminded of functionality that is currently in a prototype state but mature enough for use in production. The suite of commands is available in the Unsupported Prototype menu under the Edit, View, Route, and Manufacture menus. Help document access is conveniently located on the last row of the menu.

Routing Prototypes Drafting Prototypes



RF PCB Enhancements

A major enhancement has been made in the RF PCB in QIR 5. The RF PCB now supports MWO libraries. You can now include MWO components in your design, export and import the IFF files to exchange the design with AWR tools. As a result many RF commands are also enhanced.

■ The rf_setup command checks the current design and determine which library to use.



■ The rf_add_component command now shows the library name.

■ The rf_iff_export and rf_iff_import commands now support the MWO components.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Cadence SiP Layout and Allegro Package Designer (APD)

Cadence SiP Layout and Allegro Package Designer (APD)

This section describes the new features and enhancements in Cadence® SiP Layout and Allegro® Package designer (APD) 16.6 QIR 5.

■ Moving Wire Bonds in Etch Edit Application Mode on page 28

■ Enhancements to Symbol Spreadsheet Export on page 29

❑ Including Keywords for Cell Data on page 30

❑ Appending and Updating Existing Spreadsheets on page 30

❑ Accessing Symbol to Spreadsheet from the Symbol Edit Application Mode on page 31

■ Preserving Formulas in Spreadsheets on page 31



Moving Wire Bonds in Etch Edit Application Mode

Now you can access the Move function of Wire Bond Edit application mode from within the Etch Edit application mode. In the Etch Edit application mode, select bond fingers or wires and choose Move wire bond from the pop-up menu.



Enhancements to Symbol Spreadsheet Export

The symbol to spreadsheet (File – Export – Spreadsheet) command has the following enhancements:

■ Including Keywords for Cell Data on page 30

■ Appending and Updating Existing Spreadsheets on page 30

■ Accessing Symbol to Spreadsheet from the Symbol Edit Application Mode on page 31



Including Keywords for Cell Data

You can now select the Include data labels in cells option to include keywords per line in the cells of the exported spreadsheet to indicate what each data represents. As shown in the following sample spreadsheet, PINNUMBER (Pin Number) and NET (Net Name) are included as keywords to identify the data.

Appending and Updating Existing Spreadsheets

You can now append or update existing worksheets while exporting a spreadsheet from a symbol. If the specified spreadsheet has a worksheet with a matching RefDes, it will be updated during export. The spreadsheet will be appended if there are no matching RefDes.



Accessing Symbol to Spreadsheet from the Symbol Edit Application Mode

You can now quickly export or update a spreadsheet from the Symbol Edit application mode by selecting a component, a subset of pins, or a group of pins and then choosing Write symbol spreadsheet from the pop-up.

Note: If you select a set of pins, only the selected pins will be exported.

Preserving Formulas in Spreadsheets

Any formula in a spreadsheet is preserved while exporting or importing information in SiP Layout.

Note that the formula syntax is not validated and formulas are not evaluated by the Cadence tools. You must evaluate or edit the cell contents in your spreadsheet editing tool, say Microsoft Excel.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Allegro Design Entry HDL

Allegro Design Entry HDL

This section describes the new features and enhancements in Allegro® Design Entry HDL 16.6 QIR 5.

■ Support for Interface Aware Design

■ Component Browser

Support for Interface Aware Design

It is a common design practice to use industry-standard interfaces, such as DDRx and PCIe, to connect components in a design. Starting this release, tools in the Allegro platform are enhanced to support these interfaces through a new design object called net groups. Using net groups, you can now connect components that support the same interfaces or protocols. This significantly speeds up the design capture process.

You can create net groups in Design Entry HDL or Constraint Manager, and then add constraints to these net groups in Constraint Manager. On running the Export Physical command, net groups as well as constraints, flow from Front to Back and are available in PCB Editor where they help in placement and routing of the design.

Net Groups

A net group is a hierarchical collection of net objects. A net group can have different type of net objects, such as Nets, Buses, Differential Pairs, XNets, and Net Groups, as its members. A net group that has a net group as one of its members is called a nested net group. Any net object can be a member of only one net group.

For more information, refer to Working With Net Groups.

Component Browser

There are changes in the UI terminology in Component Browser. Setup options have been renamed and reorganized; some options are now available in different tabs. The order of the tabs can be switched using drag and drop functionality. For more information, refer to Using Component Browser in Allegro Design Entry HDL User Guide.


http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=netgroup/netgroup16.6/ng.html#1070347

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=concepthdl/concepthdl16.6/sch_crea.html#compbrowser

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=concepthdl/concepthdl16.6/sch_crea.html#compbrowser

Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Virtuoso SiP Architect

Virtuoso SiP Architect

This section describes the new features and enhancements in Virtuoso® SiP Architect 16.6 QIR 5.

■ Compatibility with IC 6.1.6 release

Compatibility with IC 6.1.6 release

HotFix 22 of SPB 16.6 (16.60.022) is compatible with CIC release IC6.1.6.500.4 and later.

Going forward, on OA, only IC 616 will be supported with SPB 16.6 releases.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Allegro FPGA System Planner

Allegro FPGA System Planner

This section describes the new features and enhancements in Allegro® FPGA System Planner16.6 QIR 5.

■ The Work Flow Window on page 35

■ Support for Layer Based Optimization on page 35

■ Multi-Voltage Pins on page 36

■ Support for On-Chip Termination in Altera Devices on page 36

■ Enhancements to the DE-HDL Schematic Generation Process on page 37

■ Additional Enhancements on page 38



The Work Flow Window

In the current release, FSP introduces a new window, Work Flow. You can access the work flow window by choosing Window – Work Flow. The Work Flow window provides a step-by-step and easy-to-use work flow that assist you with setup and design tasks such as project setup, defining connections, verifying and checking design, and more. This flow ensures that the design accurately reflects your objectives.

The Work Flow window is categorized into different functional groups or sets. Each group represents different aspects of the design tasks. For example, Check Design group contains a list of options that assists you to check the design and power connectivity. You can also customize the structure of the work flow based on your convenience.

For detailed information about the Work Flow window, see the Work Flow section of the Allegro FPGA System Planner User Guide.

Support for Layer Based Optimization

In the current release, the FSP - Allegro Integration flow is enhanced to support layer-based optimization. With FSP running in the background, Allegro PCB Editor lets you perform pin out optimizations on the bundle nets that are assigned to multiple layers.

For more information, see the Working with Layer-Based Optimization document.



Multi-Voltage Pins

In the earlier release, after you run the design, FSP leaves some of the voltage pins such as VCCINT, VCCAUX of Virtex 7 devices, unassigned. This required the user to manually enter the correct voltage values for each of the pins. This can be a time consuming, tedious, and error-prone task.

To address this issue, FSP introduced a new feature, Multi-Voltage Pins. This feature lets you to seamlessly assign voltages to pins which are capable of accepting different voltages. In this release, Virtex- 7 devices are the only affected/supported devices.

Support for On-Chip Termination in Altera Devices

In the current release, FSP provides a flexible use model that you can use to design your boards using the Altera device OCT features. It provides you with greater control for choosing the pins/ports on which OCT is to be applied, the type of OCT to be applied, and the RZQ pins that need to be preserved for OCT calibration.

For detailed information about the Altera on-chip termination, see the Working with Altera On-Chip Termination standards application note.



Enhancements to the DE-HDL Schematic Generation Process

The following enhancements have been made in DE-HDL schematic generation process:

■ In the earlier release, FSP generated hierarchical schematics by default. The FSP design intent was encapsulated in FSP design block. The FSP design block is further captured into two levels of hierarchy, the FPGA block and rest of the design. FPGA block symbols and other interface components are placed at the same level of hierarchy and are interconnected. The FSP design is instantiated in a new page at the root level of the FSP design project.

In the current release, the root level block is no longer supported and cannot be generated using the current version of FSP.

Important

In the current release, to update a schematic design generated using earlier version of FSP, it is recommended to generate a fresh schematic with the current version of FSP. After you have generated schematic for the first time, for all other subsequent generations you can generate the schematic in the preserve mode.

■ In the current release, when you invoke the Generate Allegro DE-HDL Schematics dialog box for newly created DE-HDL designs, the flat schematic mode is enabled by default,



which means, the Generate FPGA Hierarchical Block option is unchecked. For existing FSP designs, FSP will continue to generate schematics in hierarchical or flat mode as per design setup.

Additional Enhancements

Significant enhancements have been made in the following sections:

The Component menu

In the current release, several new options are added to the Component menu. These menu options provides a quick and easy way to access the most commonly used dialog boxes and tasks. For instance, the Add FPGA option lets you add FPGA to the design and the Add Interface option lets you add interface.

The Process Options Editor

In the current release, the Advanced window of the Process Options Editor window supports a new feature, Do not defer to special pins (VREF/VRP/VRN). This option is available for Xilinx devices.

You can use this option when you want to give priority to the special pins such as VREF, VRP, VRN pins etc along with the IO pins for making connections at the beginning of the design run. If you deselect this option, the IO pins will have precedence over the special purpose pins for making connections.

The Help menu

The Help menu is enhanced in the current release. A new master help page pops up when you click the Help (HTML) option in the Help menu. You can use this master help page to access, browse, and view the entire set of FSP documentation, including user guide, known problems and solutions, TCL reference guide, flow guides, and application notes.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5OrCAD Capture

OrCAD Capture

This section describes the new features and enhancements in OrCAD® Capture 16.6 QIR 5.

■ PSpice Part Search on page 40

■ Associate PSpice Model Command Enhancement on page 41

■ PSpice Component Menu Accessibility Enhancement on page 42

■ PSpice Modeling Applications on page 43

❑ Modeling Transient Voltage Suppressors (TVS) on page 44

❑ Modeling Switches on page 45

❑ Modeling Independent Sources: Impulse Sources on page 46

❑ Modeling Voltage Controlled Oscillators (VCO) on page 47

❑ Modeling PieceWise Linear (PWL) Sources on page 48

■ Capture Lite and Capture Viewer Enhancements on page 49

❑ TCL command availability in OrCAD Capture Lite on page 49

❑ Capture Lite and Capture Viewer option in Start Menu on page 49



PSpice Part Search

Prior to 16.6 QIR 5, you could add PSpice Parts on the schematic page using the Place Part window only. From 16.6 QIR 5 onwards, Capture provides an easy option to search for PSpice parts using PSpice Part Search. The PSpice Part Search allows you to search for PSpice parts and place them on the schematic page.

This feature allows you to categorize different parts with respect to their function. You can also add new PSpice parts in PSpice Part Search, by adding their details in the PSpice Part Search database.

You can also add dynamic pop-up menus in Part table of PSpice Part Search by adding menu names and TCL callback procedures.

For more information, refer Searching and Placing PSpice Parts section in Capture User Guide.

Note: Choose Place –PSpice Component –Search to access PSpice Part Search in Capture.



Associate PSpice Model Command Enhancement

Prior to 16.6 QIR 5, the Associate PSpice Model command was only used to associate Capture Library Symbols to PSpice models. Now Capture supports instance-level PSpice model assignment in the schematic editor using Associate PSpice Model command.

You can associate PSpice models to Capture parts using the Associate PSpice Model command from the Tools menu or from the pop-up menu after selecting the part.

The PSpice Model Import Wizard will appear to guide you through steps to assign PSpice models.

For more information, refer Associating PSpice model to a Capture symbol or Capture Parts section in Capture User Guide.

Note: The Associate PSpice Model command is supported for homogeneous parts only.



PSpice Component Menu Accessibility Enhancement

In 16.6 QIR 5, the Place PSpice Component menu has been updated with new sub-menus to improve accessibility of the most commonly used Capture parts in Analog or Mixed A/D projects, such as:

■ PSpice Ground

■ Capacitor

■ Diode

■ Inductor

■ Resistor



PSpice Modeling Applications

If you are using Capture – PSpice flow to simulate the design and need PSpice models for simulation, you can use the new PSpice Modeling Application provided with 16.6 QIR 5.

This application can be used in two ways:

■ For creating new models and associated device instances

■ For editing model parameters of existing device instances

Note: Transformer, Zener, Inductor, and Capacitor applications are accessed from OrCAD Capture Market Place and will open the Market Place page in Capture, in case these are not already installed on your system. You can download the application from this page. The rest of the applications are installed with 16.6 QIR 5.



The online help accessible from the dialogs provide detailed examples for many of the models. OrCAD Capture has the following new PSpice Modeling Applications in 16.6 QIR 5.

■ Modeling Transient Voltage Suppressors (TVS)

■ Modeling Switches

■ Modeling Independent Sources: Impulse Sources

■ Modeling Voltage Controlled Oscillators (VCO)

■ Modeling PieceWise Linear (PWL) Sources

Modeling Transient Voltage Suppressors (TVS)

Use the TVS modeling application to create TVS (Transient Voltage Suppressor) or MOV (metal oxide varistor) devices. You specify the datasheet information directly into the application to create a device. The models support temperature effects, tolerances, and package parasitic.

You can specify temperature in either C or K.



Modeling Switches

Use Switch modeling application to create the following type of switches:

■ Time controlled: These switches change or toggle their state at a specified time. Here specified time is the simulation time.

■ Voltage controlled: These switches change their state at a specified voltage.

■ Current controlled: These switches change their state at a specified current.

Note: Refer to the PSpice Reference Guide in the Cadence hierarchy for more information on voltage and current controlled switches.

You can create simple switches or switches with hysteresis. The switch models have built-in checks for dynamic range of parameters.



Modeling Independent Sources: Impulse Sources

A lightning impulse voltage rises very quickly, in a few microseconds, to its peak value and then falls to 0 relatively slowly. You can use lightning impulse voltages to test the effect of external source of high voltages such as lightning stroke on your designs. Designs, such as power supply systems, are often required to be qualified against the effect of such transients. These sources, modeling critically damped lightning impulses, are available as both current and voltage types.

The available sources are: 1.2/50 µSec, 4/10 µSec,4/20 µSec, 8/20 µSec, 10/350 µSec, and 10/1000 µSec.



Modeling Voltage Controlled Oscillators (VCO)

VCO is simply an oscillator having an output whose frequency is proportional to an applied voltage. VCOs are widely used in a variety of applications such as Function Generators, PLLs, Frequency Synthesizers, and so on.

The modeling application allows you to create VCOs with sinusoidal, triangular, and square waveforms as output. You can enter the following parameters to define your model:

■ Maximum Operating Frequency

■ Minimum Operating Frequency

■ VCO Sensitivity (Hz/V)

■ Maximum Controlling Voltage

■ Initial Phase (PHASE)



Modeling PieceWise Linear (PWL) Sources

Use the PWL Sources modeling application to model time-dependent PWL sources. You can specify time and amplitude relationship to define a model with a large set of data points.

For more information, refer Modeling Application User Guide available at <INSTALLATION DIRECTORY>\tools\capture\tclscripts\capPSpiceModelApp.



Capture Lite and Capture Viewer Enhancements

TCL command availability in OrCAD Capture Lite

In Capture Lite, you can now use TCL to perform modify operations on the database.

Note: You cannot save the design on the disk using the TCL operations.

Capture Lite and Capture Viewer option in Start Menu

In 16.6 QIR 5, you can access two new options, Capture Lite and Capture Viewer from the Start Menu.

Capture Lite allows you to use Capture in demo mode.

Using Capture Viewer, you can view Capture designs as read-only. Capture Viewer is different from Capture Lite as it does not limit the size of the design being viewed.

Both Capture Lite and Capture Viewer do not require licences.


Cadence SPB: What's New in 16.6 Quarterly Incremental Release (QIR) 5Cadence PSpice

Cadence PSpice

This section describes the new features and enhancements in Cadence® PSpice® 16.6 QIR 5.

■ Random function support on page 51

❑ RND function on page 51

❑ RNDR function on page 51

❑ RNDC function on page 51

■ Modelling Application on page 52



Random function support

In 16.6 QIR 5, three new functions have been added in PSpice:

■ RND function

■ RNDR function

■ RNDC function

RND function

Returns a new random value at every time point.

RNDR function

Returns a new Random value at the start of any new analysis.

RNDC function

Returns a new random value at the start of each new analysis that involves step run

For more information, see PSpice Reference Guide.



Modelling Application

If you have created design in Capture and need PSpice models for simulation in Capture - PSpice flow, you can use new Modelling Application from Capture to create new models. The new Modelling Application is provided with 16.6 QIR5.

For more information, refer Modelling Application User Guide available at <INSTALL DIR>\tools\capture\tclscripts\capPSpiceModelApp.


cadence spb: what’s new in 16.6 qir 5 (hotfix 22) · cadence spb: what's new in 16.6...

Documents