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Virtual Addressing

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Virtual Address to physical address translation

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Use of TLB

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DRAM technology

Each elementary DRAM cell is made up of a single MOS transistor and a

storage capacitor (fig1). Each storage cell contains one bit of information. This

charge, however, leaks off the capacitor due to the sub-threshold current of

the cell transistor. Therefore, the charge must be refreshed several times

each second.

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DRAM technology

HOW THE DEVICE WORKS

The memory cell is written to by placing a 1 or 0 charge into thecapacitor cell. This is done during a write cycle by opening the cell transistor

(gate to power supply or VCC) and presenting either VCC or 0V (ground) at

the capacitor. The word line (gate of the transistor) is then held at ground to

isolate the capacitor charge. This capacitor will be accessed for either a new

write, a read, or a refresh.

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DRAM technologySimplified DRAM diagram

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DRAM access diagram

The gates of the memory cells are tied to the rows. The read (or write) of a

DRAM is done in two main steps as illustrated in the fig below. The row (X)

and column (Y) addresses are presented on the same pads and

multiplexed. The first step consists of validating the row addresses and the

second step consists of validating the column addresses.

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Second Step: Column Addresses

Following the first step, column addresses are present on the address pads and

are internally validated by the Column Address Access (CAS) clock. Each selected

memory cell has its data validated in a sense amplifier. Column access is fast. This

step consists of transferring data present in the sense amplifier to the Dout pin

through the column decode and the output buffer. On memory data sheets, the

access time from RAS is termed tRAC and the access time from CAS is listed astCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns and tCAC =

15ns.

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Refresh

To maintain data integrity, it is necessary to refresh each DRAM memory cell.

Each row of cells is refreshed every cycle. For example, if the productspecification states, Refresh cycle = 512 cycles per 8ms, then there are 512

rows and each individual row must be refreshed every eight milliseconds.

As explained before, during the row access step, all the cells from the same

row are read by the sense amplifier. The sense amplifier has two roles. Sinceit holds information within the cell, it is able to transmit this data to the

output buffer if it is selected by the column address. The sense amplifier is

also able to re-transmit (write) the information into the memory cell. In this

case, it refreshes the memory cell. When one row is selected, all the cells of

that row are read by the sense amplifiers and all these cells are refreshed oneat a time.

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Current DRAM varieties

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SRAM TECHNOLOGY

The SRAM cell consists of a bi-stable flip-flop connected to the internal

circuitry by two access transistors . When the cell is not addressed, the two

access transistors are closed and the data is kept to a stable state, latched

within the flip-flop.

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The flip-flop needs the power supply to keep the information. The data in an

SRAM cell is volatile (i.e., the data is lost when the power is removed).

However, the data does not leakaway like in a DRAM, so the SRAM doesnot require a refresh cycle.

HOW THE DEVICE WORKS

Read/Write

To select a cell, the two access transistors

must be onso the elementary cell (the flip-

flop) can be connected to the internal SRAMcircuitry. These two access transistors of a cell

are connected to the word line (also called

row or X address). The selected row will be set

at VCC. The two flip-flop sides are thus

connected to a pair of lines, B and B. The bitlines are also called columns or Y addresses.

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During a read operation these two bit lines areconnected to the sense amplifier that

recognizes if a logic data 1or 0is stored in

the selected elementary cell. This sense

amplifier then transfers the logic state to the

output buffer which is connected to the output

pad. There are as many sense amplifiers asthere are output pads.

Read Operation

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During a write operation, data comes from the

input pad. It then moves to the write circuitry.Since the write circuitry drivers are stronger

than the cell flip-flop transistors, the data will

be forced onto the cell.

When the read/write operation is completed,the word line (row) is set to 0V, the cell (flip-

flop) either keeps its original data for a read

cycle or stores the new data which was loaded

during the

write cycle.

Write Operation

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Different types of SRAM cells are based on the type of load used in the

elementary inverter of the flip-flop cell. There are currently three types of SRAM

memory cells :

The 4T cell (four NMOS transistors plus two poly load resistors)

The 6T cell (six transistorsfour NMOS transistors plus two PMOS transistors)

The TFT cell (four NMOS transistors plus two loads called TFTs)

MEMORY CELL

6T Cell

This cell offers better electrical

performances (speed, noise immunity,

standby current) than a 4T structure.

The main disadvantage of this cell is its

large size.

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Overview of SRAM Types

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Cache Tag RAMs

The implementation of cache memory

requires the use of special circuits that

keep track of which data is in both the

SRAM cache memory and the mainmemory (DRAM). This function acts like

a directory that tells the CPU what is or

is not in cache. The directory function

can be designed with standard logic

components plus small (and very fast)

SRAM chips for the data storage. Analternative is the use of special memory

chips called cache tag RAMs, which

perform the entire function.