c3_4 sedra
TRANSCRIPT
-
7/28/2019 C3_4 sedra
1/25
CMOS LogicINEL 4207 - Digital Electronics - Spring 2011
-
7/28/2019 C3_4 sedra
2/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.17 The CMOS inverter.
-
7/28/2019 C3_4 sedra
3/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.18
-
7/28/2019 C3_4 sedra
4/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.19
-
7/28/2019 C3_4 sedra
5/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.20 The voltage-transfer characteristic of the CMOS inverter when QNand QPare matched.
-
7/28/2019 C3_4 sedra
6/25
Qn and Qp are matched: kn = kpUse Vtn = Vtp = Vt.
VIH
Qp is in saturation, Qn is in triode region.
iDp =kp
2(VDD vi Vt)
2
iDn =
kn
2
2 (vi
Vt) vO
v
2
O
(VDD vi Vt)2 = 2 (vi Vt) vO v
2
O
-
7/28/2019 C3_4 sedra
7/25
2(VDD vi Vt) = 2vO + 2 (vi Vt)vO
vi 2vO
vO
vi
vO = VIHVDD
2
(VDD VIH Vt)2 = 2 (VIH Vt)
VIH
VDD
2
VIH
VDD
2
2
VIH = 18
(5VDD 2Vt)
-
7/28/2019 C3_4 sedra
8/25
Use symmetry on VTC
VIHVDD
2=VDD
2 VIL
VIL =1
8(3VDD + 2Vt)
NMH =18
(3VDD + 2Vt) = NML
-
7/28/2019 C3_4 sedra
9/25
IfQn and Qp are not matched: r =
kn/kp
VM
kp2
(VDD VM + Vtp)2 =
kn2
(VM Vtn)2
VDD VM + Vtp = r (VM Vtn)
VDD + Vtp + rVtn = VM (1 + r)
VM =VDD + rVtn |Vtp|
1 + r
-
7/28/2019 C3_4 sedra
10/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.21
-
7/28/2019 C3_4 sedra
11/25
-
7/28/2019 C3_4 sedra
12/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit duringthe capacitor discharge; (d) trajectory of the operating point as the input goes high and Cdischarges through QN.
-
7/28/2019 C3_4 sedra
13/25
Approach from Secs. 10.2.3/4.10 5th edition
Using piecewise integration
tPHL =1.6C
knWL
nVDD
tPLH =1.6C
kpWL
pVDD
-
7/28/2019 C3_4 sedra
14/25
Equivalent to eq.10.18 on 5th ed.
but more general
2nd approach using ave. currentDischarge
tPHL = C
VDD (VDD/2)
iav =
CVDD2iav
iav =1
2(iDN(E) + iDN(M))
iDN(E) =1
2
knW
Ln
(VDD Vtn)2
iDN(M) =1
2kn
W
L
n
(VDD Vtn)VDD
VDD
2
2
tPHL =
nC
knWL
nVDD
n =2
7
4
3Vtn
VDD+
Vtn
VDD 2
-
7/28/2019 C3_4 sedra
15/25
Charging
tPLH =pC
kp
WL
pVDD
p = 27
4
3|Vtp|VDD
+VtpVDD
2
tp =tPHL + tPLH
2
-
7/28/2019 C3_4 sedra
16/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLHof the inverter.
Another Alternative Approach
-
7/28/2019 C3_4 sedra
17/25
tPHL = 0.69RN
tPLH = 0.69RPCEmpirical expressions
RN =12.5
(W/L)nk
RP =30
(W/L)p
k
These apply for several CMOS processesincluding 0.25m, 0.18m and 0.13m.
3rd Alternative approach
-
7/28/2019 C3_4 sedra
18/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.28 Examples of pull-down networks.
Sec. 10.3 in 5th editionLogic Gates
-
7/28/2019 C3_4 sedra
19/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by
Q3 and Q4.
= 2 gd1 + 2 gd2 + db1 + db2 + g3 + g4 + w
Cg3,g4 = WL 3,4Cox + Cgsov3,gsov4 + Cgdov3,gdov4
f14.24
Sec. 10.2.3 in5th ed.
-
7/28/2019 C3_4 sedra
20/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.25 The Miller multiplication of the feedback capacitance Cgd1.
Cgd1,2, Cgsov3,4 and Cgdov3,4 areoverlap capacitances
-
7/28/2019 C3_4 sedra
21/25
Example: CMOS 0.25m process with Cox = 6fF/m2,
nCox = 115A/V2,pCox = 30A/V2,Vtn = - Vtp = 0.5V, and VDD = 2.5V.
(W/L)n = 0.375m/0.25m, (W/L)p = 1.125m/0.25m
Cgd, Cgsov, Cgdov 0.3fF/mW
Cdbn = Cdbp = 1fF , CW= 0.2fF
Find tp when the inverter is driving an identical inverter.
-
7/28/2019 C3_4 sedra
22/25
C= Cint + CextIncreasing W/L by a factor S increases Cint
C= SCint0 + Cext
and decreases Req = (RN + RP)/2 by S with respect tothe original Req0.
tp = 0.69
Req0S
(SCint0 + Cext)
= 0.69Req0Cint0 +
1SReq0Cext
Inverter Sizing
-
7/28/2019 C3_4 sedra
23/25
Example:
If the inverter in the previous example, find(a) Cint and Cext,(b) factor S to reduce extrinsic part of tp by 2,
(c) resulting tp, and
(d) factor by which the area is increased.
-
7/28/2019 C3_4 sedra
24/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.26 The current in the CMOS inverter versus the input voltage.
Ipeak =nCox
2(W/L)nVDD
2 Vtn
2
f14.26
-
7/28/2019 C3_4 sedra
25/25
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
Figure 14.27 Representation of a three-input CMOS logic gate. The PUN comprisesPMOS transistors, and the PDN comprises NMOS transistors.