c2 part 4: vlsi cad tools problems and algorithms
DESCRIPTION
C2 Part 4: VLSI CAD Tools Problems and Algorithms. Marcelo Johann. EAMTA 2006. Outline. THIRD PART Layout Compaction Logic Synthesis, BDDs Technology Mapping Simmulation vs Formal Verification Voltage Drop by Random Walks FOURTH PART High-Level Synthesis - PowerPoint PPT PresentationTRANSCRIPT
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C2 Part 4:C2 Part 4: VLSI CAD Tools VLSI CAD Tools Problems and AlgorithmsProblems and Algorithms
Marcelo JohannMarcelo Johann
EAMTA 2006EAMTA 2006
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EAMTA 2006 - Marcelo Johann - C21.2
OutlineOutlineTHIRD PART
• Layout Compaction• Logic Synthesis, BDDs• Technology Mapping• Simmulation vs Formal Verification• Voltage Drop by Random Walks
FOURTH PART•High-Level Synthesis•CDFG, Allocation, Scheduling, Generation
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EAMTA 2006 - Marcelo Johann - C21.3
Function representationsFunction representationsTruth Tables
Lists the output for every input combination
• For n variables, 2n lines
Formulas
F=x1.x2.~x5 + ~x3(x2.x4.x5 + ~x2) + x2.x3
• Not Canonical in general, canonical is large
BDDs
A graph that packs a truth table
• Average sized, powerful representation
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EAMTA 2006 - Marcelo Johann - C21.4
BDDsBDDs
Source: Wikipedia
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EAMTA 2006 - Marcelo Johann - C21.5
BDD - good orderingBDD - good orderingBDD graph for the Boolean formula x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8 using a good variable ordering
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EAMTA 2006 - Marcelo Johann - C21.6
BDD - bad orderingBDD - bad orderingBDD graph for the Boolean formula x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8 using a bad variable ordering
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EAMTA 2006 - Marcelo Johann - C21.7
Random WalksRandom Walks
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EAMTA 2006 - Marcelo Johann - C21.8
Random WalksRandom Walks
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EAMTA 2006 - Marcelo Johann - C21.9
IR DropIR Drop
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EAMTA 2006 - Marcelo Johann - C21.10
Random WalkRandom Walk
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EAMTA 2006 - Marcelo Johann - C21.11
The AlgorithmThe AlgorithmInitialize
• Compute conductance, px,i , mx
For each node in the circuit
Loop n times according to accuracy
Loop until reaching Supply – Add this node’s cost– Random select the next move
Make this node a new supply
Print the result
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EAMTA 2006 - Marcelo Johann - C21.12
AccuracyAccuracy
15876 VDD nodes15625 GND nodes1.2VLinux 2.8GHz CPUDelta controls error such that 99% of the nodes have less thenError Margin
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EAMTA 2006 - Marcelo Johann - C21.13
VLSI System DesignPart V : High-Level Synthesis
Lecturer : Tsuyoshi IsshikiVLSI Design and Education Center,
The University of Tokyo
Dept. Communication and Integrated Systems,
Tokyo Institute of Technology
[email protected]://www.vlsi.ss.titech.ac.jp/~isshiki/VLSISystemDesign/top.html
Jump to…Jump to…
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C2:C2: VLSI CAD Tools VLSI CAD Tools Problems and AlgorithmsProblems and Algorithms
EAMTA 2006EAMTA 2006
Marcelo JohannMarcelo Johann
www.inf.ufrgs.br/~johann
Thank you!