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VLSI Design IP Protection: Solutions, New Challenges, and Opportunities

Lin Yuan and Gang Qu

Electrical and Computer Engineering Departmentand Institute for Advanced Copmuter Studies

University of Maryland, College Park, MD U.S.A.{yuanl, gangqu}@glue.umd.edu

Lahouari Ghouti and Ahmed Bouridane

School of Computer Science and the Institute ofElectronics, Communications and Information

TechnologyQueen's University of Belfast, Belfast, UK

{L.Ghouti, a.bouridane}@qub.ac.uk

Abstract

It has been a decade since the need of VLSI design

intellectual property (IP) protection was identified[1,2]. The goals of IP protection are 1) to enable IP

providers to protect their IPs against unauthorized

use, 2) to protect all types of design data used to

produce and deliver IPs, 3) to detect the use of IPs,

and 4) to trace the use of IPs [3]. There are significantadvances from both industry and academic towards

these goals. However, do we have solutions to achieve

all these goals? What are the current state-of-the-artIP protection techniques? Do they meet the protection

requirement designers sought for? What are the (new)

challenges and is there any feasible answer to them inthe foreseeable future?

This paper addresses these questions and provides

possible solutions mainly from academia point of

view. Several successful industry practice and ongoing

efforts are also discussed briefly.

1. Introduction

The ever-increasing logic density has resulted in moretransistors on silicon than designers ability to designthem meaningfully. This creates the design

productivity gap between what can be built and whatcan be designed. Despite the design technologyinnovations in the last decade, this gap is becomingwider and wider. To close this gap, we need asignificant shift in design methodology. At the heart ofthis shift is the principle of design reuse, which is themost significant design technology innovation in the

past decade as one can see from Figure 1.

In this new design method, large previously designedblocks, such as bus controllers, CPUs, and memorysubsystems, will be integrated into an ASICarchitecture to deliver routine functions in a

predictable manner. Designers now can focus on whatthey do best to design new blocks, representing theirtrue design innovation, based on the systemrequirements. This not only makes it possible to havethe new products on market in a timely and cost

effective fashion, the newly developed blocks will alsobe tested, documented, and deposited as designintellectual properties (IPs) in the internal IP libraryfor future reuse.

There exist significant technical barriers to increasedesign productivity by design reuse. IP protection isamong the original six key enabling technologiesidentified by the Virtual Socket Interface (VSI)Alliance when it was founded in 1996 [1]. It was alsocited as a unique and one of the most challengingareas awaiting research breakthroughs.

What makes IP protection a unique challenge is the

new reuse-based design environment we justdescribed. It forces engineers to cooperate with othersand share their data, expertise, and experience. Designdetails (including the RTL HDL source codes) areencouraged to be documented and made public tomake reuse more convenient. But at the same time,this makes IP piracy and infringement easier than ever.It is estimated that the annual revenue loss in IPinfringement in IC industry is in excess of $5 billion.The goals of IP protection include: enabling IP

Figure 1. Design technologyinnovations in the past decade. (datasource: International TechnologyRoadmap for Semiconductors 2001 [4].)

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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providers to protect their IPs against unauthorized use,protecting all types of design data used to produce anddeliver IPs, detecting and tracing the use of IPs [3].

There have been significant advances from bothindustry and academic towards these goals. Highlightsinclude the VSIAs white paper on IP protection [3]

and its physical tagging standard [5] that has now beenwidely adopted by semiconductor and EDA industry;

practices on the protection of web-based collaboratedesign environment and FPGA design protection byindividual companies such as Xilinx(www.xilinx.com) and Altera (www.altera.com); andthe numerous protection mechanisms proposed byresearchers both from industry and academia onliterally every phase of the design procedure[2, 6-16,18,19,24-26]. Naturally, efforts from industry are onthe identify and trace of legal IP usage for the purposeof checking, updating, and royalty reporting amongothers. Research from academia concentrates on the

protection and deterrent of high-tech IP piracy, whichis a potentially critical, but not yet real problem insemiconductor and EDA industry. This interestingdistinction between industry and academia determinesthe fact that people will view the same question indifferent ways and provide different answers withindifferent but relevant context. They arecomplementary to each other and will collaborate toreach all the goals for IP protection in VLSI design.

In paper, we first provide a comprehensive review ofthe current state-of-the-art IP protection practice andadvances. We then discuss several key challenges,explain how people view these challenges differently

from academia and industry. We mention a couple ofsuccessful and current efforts from industry. Our mainfocus is on the directions and practical approachesfrom academic point of view on how to answer suchchallenges.

2. State-of-the-Art IP Protections

We restrict our survey to the non-law enforcement IPprotection practice and research.

VSIAs physical tagging standard [5] is by far the onlyofficial standard and has enjoyed tremendous successin the past few years. It describes a procedure on howto embed information into the graphical design systemII (GDSII) file. Such plain text information allowssemiconductor manufacturer to tag and trackcomponents used (reused) in a design at thefabrication process. This standard is designed tofacilitate the information sharing among lawful andhonest IP providers and users rather than protect theGDSII file from being misused by adversaries. Notethat the standard is open to the public, every foundry

can check the information from the GDSII file, andadversary can also easily modify it.

Standard encryption has been mentioned as one way toprotect design IPs (including design data) despite therather expensive decryption process [3]. Recently,several FPGA design tools provide users the

encryption choice. Alteras encryption softwareenables users to encrypt their design and any attemptto compile an encrypted IP will fail if the core is notdecrypted properly. Xilinx adds a decryption unit onits latest Virtex-II and Virtex-II Pro FPGA board. Itsdesign tool allows user to select up to six plaintextmessages and uses them as the key to encrypt theFPGA configuration bitstream file. The decryptionunit will decrypt it before configuring the FPGA

board.

On the other hand, protection mechanisms developedfrom academia serve as the deterrent for IP piracy.Most of these works are under the watermarking

framework proposed by Kahng et al. [2,15], which hasbeen applied to various aspects of the VLSI designprocess, from behavioral and logic synthesis tostandard cell place and route algorithms, to FPGAdesigns [2,7-10,12,15,17,24,25]. There are also severalstudies on IP fingerprinting techniques [6,14] andmethods to recover the embedded signatures[11,16,19,26].

Figure 2. Basic concept of the constraint-

based watermarking technique.

The constraint-based watermarking technique [2,15]translates the to-be-embedded signatures into a set ofadditional constraints during the design andimplementation of IP in order to uniquely encode thesignature into the IP. Considering IP invention assolving a hard problem where the requirements for theIP serve as constraints, this basic idea can be depicted


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in Figure 2, where we also show its key concept ofcutting solution space.

To hide a signature, the designer first creates anotherset of constraints using his secret key; theseconstraints are selected in such a way that they do notconflict with the constraints in the original problem.

Then the original and additional constraints arecombined to form a more constrained stego-problem.The stego-problem, instead of the original problem, issolved to obtain a stego-solution. Using informationhiding terminologies, we refer to the original problemas cover-constraints, and the signature as embedded-constraints. A stego-solution will satisfy bothconstraints.

To claim the authorship, the author has to demonstratethat the stego-solution carries information based on hissignature. The stego-solution unnecessarily satisfies aset of additional constraints that look random until theauthor regenerates them using his signature together

with his secret key. Cryptography functions such asone-way hash and stream cipher will be used togenerate the embedded-constraints. There are severalapproaches proposed to detect the embeddedwatermark. For several specific instances, Kahng et al.[11] choose signatures selectively and develop fastcomparison schemes to detect such signatures.Charbon and Torunoglu [26] discuss copy detectionunder a design environment that involves IPs frommultiply sources that requires IP providers to registertheir IPs in a trusted agent. Kirovski et al. [19] proposea forensic engineering technique to identify solutionsgenerated by strategically different algorithms.

3. Challenges

There seems to be an interesting and growing rift onthe objectives and approaches between industry andacademia on IP protection. In industry, design teamsare in dire need of techniques and standards thatenable them to build yield and risk assessment, checksrelease numbers, warn them when a problem arises,optimize future library for content definition andenables IP management such as royalty reporting.Being able to protect their IPs from being misused is anice feature, but unfortunately has not been really

considered by many design teams as a necessity. Boththe released VSIA physical tagging standard and thesoft IP tagging standard [27] look to identify ways toembed design-related plaintext messages into thedesign to achieve these goals.

In academia, being aware of the existence of powerfulreverse engineering tools, researchers are developingtechniques at various levels of the design process to

discourage any attempt of IP piracy from happening.Their approach is also based on the idea of embeddeddesign-related information into the design. However,such information is encrypted and hidden so theadversary cannot see it with ease.

Nevertheless, both sides have agreed, although again

they view the same problem in different ways, on thefollowing new major challenges for IP protection.

3.1 Restrain Design Overhead

Due to its nature of adding constraints, thewatermarking-based IP protection techniquesinevitably introduce design overhead. As it has been

pointed out originally, design overhead should be keptas low as possible [2,11]. Qu and Potkonjak [17] studythe random graph coloring problem and conclude thatit is possible to keep the overhead at the minimal levelwhile still providing strong protection. However, theyalso mention that if the number of watermarking

constraints is not selected carefully, the overhead canbe arbitrarily high. Furthermore, the randomness of thewatermarking constraints makes the design overheadhard to predict. For example, Lach et al. experimentthe timing and resource overhead for various FPGAwatermarking techniques. They report resourceoverhead from 0.005% to 33.86% and timing overheadfrom 25.93% to 11.95% [6,9]. Kirovski et al. developwatermarking protocols during the multi-level logicminimization and technology mapping phases. Thedesign overhead goes from negative to 8.12% [8].Oliveira proposes a technique to watermark sequentialcircuit designs where the area and delay overhead can

be negligible for large designs but are as high as2747% and 273%, respectively, for even very smalldesigns [10].

Currently, there is no watermarking technique thatguarantees the design quality or gives an upper boundon the design overhead. The lack of quality guaranteeremains one of the key obstacles for the watermarking-

based IP protection techniques to be adopted as anindustry standard.

3.2 Protect Soft IP

Soft IPs are delivered in the form of synthesizableHDL codes like Verilog or VHDL programs.

Although soft IPs have less predictable performanceand much higher protection risks, the emerging trendis that most IP exchange and reuse will be in the formof soft IPs because of the design flexibility they

provide [18]. On some occasions, IP provider may alsoprefer releasing soft IPs to leave customer-dependentoptimization process to the users.


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From security point of view, protecting soft IPs is amuch more challenging task than protecting hard IPssuch as GDSII files or fully placed netlist. Theflexibility makes soft IPs hard to trace and thereforedifficult to prevent IP infringements from happening.IP providers are taking a high risk in releasing theirIPs in the soft form before they protect their HDLcodes with techniques that are effective, robust, low-complexity, and low-cost. Unfortunately, suchtechniques or tools are not available and theirdevelopment is challenging.

Existing constraint-based watermarking techniques fornetlist [2,8,15] are applicable to protect gate-levelHDL code. Although it is synthesizable, gate-levelHDL code is just a plain description of the design anddoes not help users to understand and thus effectivelyreuse the design. Synthesizable behavioral-level HDLcode, on the other hand, gives a high level descriptionof the system. Its C-like programming syntax and

structure makes it friendly for reuse and hence themost valuable asset of soft IPs.

However, existing software protection techniques arenot applicable to HDL code protection either. Thereason is that these protections are either on theexecutables or syntax techniques such as removingcomments and renaming variables. HDL programs,first of all, do not have any executables or binarycodes. Second, they are suggested to have properdocumentations and to follow standard codingguidelines for better reusability [18].

3.3 Protect CAD Tool and Algorithm

CAD tools, algorithms, and design environment areyet another type of VLSI design IPs. They arecurrently being treated and protected as traditionalsoftware by mechanisms such as licensing agreementsand encryption. Despite the lack of enforcement oflicensing agreements and the security holes ofencryption protocols, these protections do not providethe ability to detect IP piracy. That is, if a tool or analgorithm is illegally used to generate an IP, onecannot tell from this piece of IP whether it is obtainedlegally. Because the (dishonest) IP designers can claimthat they obtain the IP by other tools or algorithms.Another characteristic on CAD tool and algorithm

protection is that piracy normally involves the misuseinstead of illegally redistribution of the tool oralgorithm.

The only known technique that detects possible CADtool and algorithm piracy is the forensic engineeringapproach proposed by Kirovski et al. [19]. It enablesthe identification of solutions generated bystrategically different tools and algorithms. First,

statistical data are collected from the solutionsgenerated by a pool of algorithms. Then they studycertain problem-dependent properties of the solutionsto put the pool of algorithms into clusters. To detectwhich algorithm has been applied to obtain a givensolution, they simply check the given solution for the

properties that the algorithm clustering has beenperformed and claim that the solution is obtained bythe algorithm that has the best fit. It has severallimitations: first, it is only applicable to distinguishstrategically different algorithms. Second, it requiresthe availability of a pool of candidate algorithms and alarge benchmark of problems as well as the computingresource to run each algorithm on each probleminstance. Third, characterization of the solutions tocluster the algorithms is not a trivial task.

The collaborated web-based design frameworks [20-22], including IBMs recent launched on demandcollaboration environment to verify chip designs

verification environ-ment [23], make CAD tools morevulnerable than ever to be used misappropriately.Given the important role that CAD tools andalgorithms play in the EDA society, particularly in theIP-based design era and the collaborated web-baseddesign environment, the need for effective CAD toolsand algorithms protection becomes obvious andurgent.

4. Opportunities

We discuss the possible directions to tackle the abovechallenges with emphasis on approaches fromacademia.

4.1 Design Overhead

In the original proposal of watermarking-based IPprotection, the pre-processing and post-processingmethods are discussed [2,15]. Pre-processingtechniques embed watermark before the synthesistools are applied to solve the (watermarked) problem.In post-processing, the original problem without anywatermark is first solved, and then the solution will bealtered based on the watermarking constraints. Toachieve high robustness of the watermark, the authorsargue that it is preferable to have pre-processing andthis vision has impacted almost all the follow-up work

on IP protection.As we have already mentioned in the section ofchallenges, pre-processing techniques add randomextra constraints to the initial problem and thusintroduces the unpredictable design overhead. Even inthe optimization-intensive version [24], no guaranteeon the watermarked IPs quality degradation can be

provided. However, in the post-processing approach,


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the best solution from the synthesis tool is knownbefore the watermarking process. It becomes possibleto embed watermark in such a way that the overheadcan be controlled, if not avoided completely. This is atthe cost of reduced robustness because adversarycould also make changes on the solution andeventually alter or remove the watermark.

To achieve limited overhead guarantee and highrobustness simultaneously, we propose a three-phasewatermarking embedded approach. In the first phase,synthesis tool is applied to the original problem to

produce the best possible solution. In the secondphase, we identify certain non-critical constraints inthe problem that will not affect the solution qualitydramatically and embed them as the watermark. In thelast phase, the synthesis tool is applied again to createa watermarked solution. Comparing to the pre- and

post-processing watermarking approaches, this newapproach has the following advantages and

disadvantages:1. Phase I conducts the design without any

watermarking. This allows us to obtain a designsolution with the best possible quality.

2. With the best quality design solution as areference, we can select constraints to tradesolution quality for robustness or otherwatermarking objectives in phase II. Note that thisis impossible for pre-processing because the bestdesign quality is unavailable.

3. Re-synthesis in Phase III makes it again difficultfor adversary to temper the watermark. Thisdistinguishes our approach with post-processing.

As one can see, the key step is Phase II where weactually perform the watermarking procedure. We

believe that 1) there exist plenty of redundancies inthe original design constraints, for a given solution,which can accommodate the watermark. We willdemonstrate this later in this section by the example offinite state machine state minimization problem. 2)watermarking constraints should be embedded close tothe end of the synthesis to reduce the complexity of(re-)synthesis and to increase the predictability of thesolution quality change due to watermarking.

As an example, we mention a recent FPGA

watermarking approach proposed Jain et al. [25] thatguarantees no design overhead in timing and systemresource. A design as usual is performed first to get allthe timing on all the nets. Then the required signatureis mapped to additional timing constraints on carefullyselected nets and the place and route is redone togenerate the FPGA configuration bitstream. Real lifeFPGA designs demonstrate that all the timing

requirements are met with no additional resource. Andthe watermarked designs have FPGA configuration

bitstreams significantly different from the originalones to provide strong proof of authorship (Table 1).

4.2 Soft IP Protection

The IP protection development and working group inVSIA is currently developing a specification/standardfor moving soft IPs between companies using a simpletagging or watermarking scheme. This effort is tohelp honest IP users to exchange IPs. However, it maycreate a huge security hole for IP protection. In the

physical tagging standard, plaintext information on the

IP is embedded in the GDSII file and only limitednumber of semiconductor foundries are capable tomisuse such information. An HDL code, on the otherhand, can be tweaked easily by any hardware designer.

Nevertheless, our belief is that soft IP protectionproblem, from academic point of view, is solvable.

First, the programming styles and variable namingconventions among other standards suggested byindustry experts [18] increase the readability andreusability of the HDL code. Meanwhile, it also limitsthe power of adversary. With the ongoing effort onsoft IP tagging standard, this can only become betteronce it is adopted. For example, a netlist of the designwithout documented HDL code makes itselfsuspicious. Second, technically, it is still possible tohide information into the soft IP. As we will see in the

protection of CAD tool and algorithm, every designerhas his or her design style that can be traced from theHDL code he or she writes. Moreover, recall that themotivation for soft IP exchange is to make reuse easierand more efficient. Resynthesizing the soft IP with

Table 1. Validation of zero overhead and

strength of watermark on benchmarkFPGA designs [25].

FPGA Designs Original Watermarked OverheadBitstrem

Difference

Resources 1083 1083 0%DAP(2,503,260

gates)fmax required:

40MHz 0%

1.13%

Resources 1522 1522 0%VIDEO(56,253gates)

fmax required:35MHz

0%2.15%

Resources 746 746 0%RISC(6,894gates)

fmax required:50MHz

0%5.47%

Resources 285 285 0%AddrGen

(2,862gates)

fmax required:40MHz

0%1.83%


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other blocks normally results in designs better than theones obtained by integrating the hard IP with other

blocks. However, certain parts of the soft IP, such as arather unique memory design, are very unlikely toshare resources with other blocks. In such case,

providing those parts as hard IP reduces the flexibilityof reuse, but it may not affect much of the designquality. Meanwhile, it opens room for hard IP

protection techniques. We believe that thiscombination of hard IP and soft IP will be a promisingdirection for soft IP protection.

In [28], the authors argue that any good HDL sourcecode watermarking technique should provide (1)strong proof of authorship, (2) low design overhead,(3) survivability from re-synthesis, (4) resilience, and(5) preserve IPs I/O interface. To reach these goals, itis necessary to have the documentation assumptionand the verification assumption. The first requiresthe designer to document the HDL modules properly

and give sufficiently detailed information on eachreusable modules input, output, and functionality. Itallows, however, designer not to document otherdetails on how each module is implemented. Thesecond requires all HDL design to follow thehierarchical modular fashion and not to mixcomplicated gate-level HDL code with RT-leveldescription. Based on these assumptions, severaltechniques have been proposed to embed informationinto HDL source code. However, these techniques aread hoc with limited watermark embedding capacityand may have large design overhead.

4.3 Design Tool and Algorithm ProtectionConceptually, it is possible to apply the constraint-

based watermarking technique to protect design tooland algorithm during the design and implementationof such tool and algorithm. (To see this, just treat thedesign tool and algorithm as IPs.) However, quality ofthe solutions obtained by such protected tool andalgorithm cannot be guaranteed. Furthermore, thisapproach cannot protect existing tools and algorithmswithout redesign them.

We argue that an effective CAD tool and algorithmprotection technique must be able to

identify with high accuracy that whether the givensolution is generated by the target tool oralgorithm;

retain the performance (e.g., CPU and memoryrequirements) of the tool and algorithm and thequality of the solutions it provides;

be robust against attempts to remove theprotection from the tool and algorithm, or todisguise the solutions obtained by them.

Note that although the design process may not bereversible, CAD tools and algorithms usually leave

plenty of traces in the design solution they find. The

forensic engineering technique attempts to collectthese unintentionally left trace to identify CAD toolsand algorithm by sampling over a large set ofrepresentative trials. We propose to intentionally"leave a trace of the tool and algorithm in the designsolutions generated by them. This enables us toquickly detect the usage of the protected tool andalgorithm with high accuracy. As an example, thefollowing scheme protects a 3SAT solver:

1. select a fixed set of clauses from the 3SATformula;

2. for each selected clause, x+y+z, append

(x'+y'+z')(x+y'+z')(x'+y+z')(x'+y'+z) to theformula;

3. solve the new formula to find a solution;

There are seven different ways to make clause x+y+ztrue. The addition of extra clauses in step 2 enforcesthat one and only one of the three literals x,y,z can beassigned to be 1. For any solution obtained by this(protected) solver, the fixed set of clauses (thoseselected in step 1) will have exactly one literalreceiving assignment 1. This unique feature of thesolver can be used to detect whether a given solutionis obtained from this solver and thus achieve our goalof CAD tool and algorithm protection.

Yuan et al. [29] propose a birthmarking method forCAD tool and algorithm protection. In their approach,they first use the tool/algorithm to find a designsolution with the best possible quality. Then theyconduct an additional design step to birthmark thedesign solution by changing it locally withoutaffecting the design quality. Such local changes can bedetected later as a proof of the tool/algorithm that has

been used during the design. This is similar to thepost-processing watermarking technique [2,15]. Theyuse a gate-level timing-driven gate duplication tool asexample to illustrate this approach and the extensiveexperimental results show that such birthmarkingtechnique incur very small overhead.

4.4 Redundant Design Constraints

To end our discussion, we use the finite state machine(FSM) state minimization problem as an example to


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demonstrate the concept of redundant designconstraint [30].

(a) (b)

Figure 3. (a) State transition graph for theFSM. (b) State transition graph for thereduced FSM.

Consider an FSM with eight states, one binary inputand one output. Its state transition graph is shown in

Figure 3 (a). This FSM can be reduced to one withonly four states, and there are two solutions:{{1,4},{2,5},{3,6},{7,8}} and {{1,4,7},{2,5},{3,6},{8}}. Figure 3 (b) is the state transition graph for thefirst solution.

Surprisingly, if we keep all the output information andonly the seven state transitions that have a dot on thearrow in Figure 3 (a), the solution remains the same.This suggests that these conditions are sufficient toobtain the above solutions. The absence of other fivestate transitions (i.e., replacing the next states of thesetransitions by don't care will not have any impact.Therefore we call them redundant design constraints.

There are very rich redundant constraints in finite statemachine synthesis as indicated by experiments on thestandard MCNC sequential circuit design benchmarks[30]. In addition, one can add redundant states, statesthat are equivalent to other states, and synthesize thenon-minimized finite state machines. When part of theredundant states are added, the synthesis solutionshave very little overhead, and very often are bettersolutions, in area and power consumption.

We can leverage this redundancy to hide informationby, for example, the following scheme: keeping theredundant constraint for a bit 1 and deleting it for a

bit 0. Note that we obtain the set of redundantconstraints from an existing solution and thismodification of the system specification will notchange the correctness of this solution. Thewatermarked design and non-watermarked design willstart from this same solution and therefore there willnot be any design overhead.

5. Conclusion

VLSI design intellectual property protection has beena hot topic since the late 90s and is cooled off in the

past couple of years. In this paper, we survey thecurrent status of IP protection, analyze the newchallenges and discuss the opportunities. Although

people from academia and industry have, in somesense, quite different viewpoints of this problem, it isour belief that the collaborated efforts will eventuallyfind ways to protect VLSI design IPs efficiently andeffectively.

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