by: vova menis-lurie sonia gershkovich advisor: mony orbach
DESCRIPTION
Out-of-Order OpenRISC 2 s emesters project Semester A : Implementation of OpenRISC on XUPV5 board Midterm Presentation. By: Vova Menis-Lurie Sonia Gershkovich Advisor: Mony Orbach. Spring Semester 2012. Content:. 1.Project Overview - PowerPoint PPT PresentationTRANSCRIPT
Out-of-Order OpenRISC2 semesters project
Semester A: Implementation of OpenRISC on XUPV5 board
Midterm PresentationBy: Vova Menis-Lurie Sonia GershkovichAdvisor: Mony Orbach
Spring Semester 2012
Content:
1.Project Overviewa. Background and the challengeb. Goals
2. Specificationsa. Working Environmentb. OpenRISC 1200
3. Our System:a. Block Diagramb. Implemented Designc. Simulation
4. Workflow5. Timetable – Gantt Chart
Project Overview Background
• OpenRISC is an OpenCores community project for developing RISC
architectures
• The only architecture till now: OpenRISC 1000
• Configurable implementation OpenRISC 1200
Our challenge is to configure the convenient architecture
implementation for XUP5 board, and create the
environment to ensure proper work and testability of the
system.
Project Overview Project Goals
Primary Goal:
• Implementation of Out-of-Order execution engine on the base of
OpenRISC architecture
Primary Goal – semester A:
• Creating a complete system-on-a-chip based OpenRISC, on XUP5
board, as a platform for further work, including:• Choosing Configuration for the CPU
• Simulation and Synthesis
• Implementation
• Debugging
• Testing the system
Project Overview Our Goals• Understanding of the fundamentals of computer architecture
• Acquiring computer designer’s skills, including experience in CPU
design, computer organization , hardware implementation and
debugging.
• Learning and practicing Verilog HDL (OpenRISC implementation
language)
Specifications of Working Environment Hardware – XUPV5 board
*Xilinx Virtex-5 XC5VLX110T FPGA (total Memory 2MB)
*Two Flash PROMs (32 MB each) *64-bit wide DDR2 DIMM
*On-board 32-bit ZBT SRAM )9MB)*Intel P30 Strata Flash
*Compact Flash controller
*10/100/1000 tri-speed Ethernet PHY *USB host and peripheral controllers
*Many I/O devices and ports
• Project Management
- PlanAhead (ISE)
• Simulation
- Icarus + or1ksim (requires Unix OS/CygWin)
• Synthesis
- XST(ISE)
• Debugging:
- long hours
Specifications of Working Environment Software
The OpenRISC 1200
The OpenRISC 1200
Simulation:Text to UART
Interrupt:Tx=ascii[x] -> Rx=ascii[x+1]
Simulation:Text to UART
Workflow:1. Choosing the configuration: what optional/configurable parts we will include.
2. Complete system compilation, including CPU and buses and other parts according to section 1.
3. Simulation and synthesis, pin-assignments.
4. Burning the system to the chip and basic debugging(here the work begins:).
5. Choosing a way to test the system, for example creating simple C program and executable file to be run on the OR1200 .
Achievements:
• Creating a complete system-on-a-chip based OpenRISC, on XUP5 board.
• Understanding of the fundamentals of computer architecture
• Learning and practicing Verilog HDL (OpenRISC implementation language)
• Acquiring computer designer’s skills, including experience in CPU design,
computer organization, hardware implementation and debugging.
• Learning the architecture an existing implementation of OpenRISC 1000
Challenges:
There were a number of challenges we had to deal with during our work
• Absence of documentation for the existing based Open RISC implementations.
• Requirement of using number of different work environments, that are not compatible to each other
• Significant challenge was an understanding of SoC’s software flow and a connection between Hardware and Software.
Conclusions:There are some possible improvements and new features that may be implemented in the future:
• Building more efficient system software loader, for example by using jtag bridge or by adding bootloader to SoC .
• Adding addition modules can be considered, for example usb, ethernet e.t.c.
• New Linus kernel supports OR1000 ISA so it’s possible to run Linux OS on this system. It will open a wide range of possibilities to actual use of this system.
• Platform of this project can be used for a multi-core systems, by adding additional openrisc cores to the system and building system scheduler for tasks.
• For future development of this project, allocation of computer with UNIX OS with full license for XILINX tool should be considered by the lab’s staff.
Thank you!