? FNALREPORT

PART II

~ ANALYSIS OFADVANCED DATA TRANSMISSIONTECHNIQUES

-

SEPTEMBER 1962

TO FEDERAL AVIATION AGENCY

CONTRACT NO. 'FAA/BRD-80lopeouad bV

NATIONAL TECHNICALINFORMATION SERVICE

Spebog"Kl Vs- 221,51

| I

GIIENERAL DYNAMICS I ELECTRONICS-ROCHESTER vro

FINAL REPORT

PART II

ANALYSIS OF ADVANCED DATA TRANSMISSION TECHNIQUES

S GENERAL OYNAMICS I ELECTRONICS-ROCHESTER

Rochester, New Yfork

September 1962

toFEDERAL AVIATION AGENCY

Contract No. FAA/BRD-80

"This report has been prepared by General Dynamics/Ejectronics-

Rochester for the Systems Research and Development Service, FederalAviation Agency, under Contract No. FAA/BRD-80. The conte:its ofthis report reflect the views of the contractor, who is responsiblefor the facts and the accuracy of the data presented herein, and donot necessarily reflect the official views or policy of the FAA."

PREPARED BY(G. C. PorterProject Engineer

L. M. LukeSection Head

APPROVED BY: 0, , g___;LA___

T. G. flameManagerCommunications and Electronics

Advanced Development Engineering

S]i

TM3LE OF CONTENTS - PART II

Page No.

INTRODUCTION 1

Section

3.0 TEST -ACILITY

3.1 Introduction 3-1

3.2 Function 3-1

3-3 Signal 3-1

3.4 Layout 3-2

3 5 Diagrams 3-3

3.6 Power Requirements 3-3

3.7 Facility 3-3

3.7.1 Clock Pulse Generator 3-3

3.7.2 Transmit Character Pu'.[se Generator 3-5

3.7.3 Receive Character Pulse Generator 3-6

[- 3.7.4 Pattern Generator 3-6

3.7.5 Receiving Register and Comparators 3-7

1 3.7.6 Mechanical Counters 3-8

3.7.7 Divide-by-10 Decimal Decoder and Meter Indicator 3-9

3.8 Facility Logic and Counter Functions 3-10

3.9 Facility Operating Procedure 3-10

3.10 Keyer and Converter 3-il

3.10.1 Keyer 3-121.

3.10.2 Band Pass Filters 3-13

1. 3.10.3 900 Phase Shift Integrator 3-13

3.10.4 Limiter Amplifiers 3-14

!!..

I °

V secTti• (IT? CONTENTS PART II (Cont :d.)

SSection Page No.

3.10.5 Driver Amplifiers 3-11.

3.10.6 Power Amplifiers 3-14

3.10,7 Phase Detector 3-15

3.10.8 Low Pass Filter and Emitter F',1lower Driver 3-15

3.10.9 Decision Circuit 3-16

3.10.10 Mixer Amplifier 3-16

3.11 Noise Feedback Control 3-16

3.12 Keyer and Converter Operating Proc dure 3-18

4.0 CONVERTER- DF,,IGN

4.1 Introduct Ion 4-1

4.2 Converter Operation 4-1

4.3 Converter Zrcuit Design 4-2

4.3.1 Mixer Ar olifier 4-2

4.3.2 Bandress Filters 4 34.3.3 Limiters 43

4.3.4 Integzretor 4-4

4.3.5 Driver azd Power Amplifiers 4-5

4.3.6 Phase Dtc.c 4-5

4.3.7 Low Pass riiver 4-6

k.j.• Deeision CLrcuit 4-7

4.4 Noise Source 4-7

4.5 Initial Converter Set Up 4-9

4.5 Converter Waveforms 4-10

4.7 Conclusions 4-12

iii

3

TABLE OF CONTk1TS - PART II (Cont'd.)

-ction

9.0 SCHEMATICS and BLOCK DIAGRAMS

S-1 Mechanical Conter Power Supply

S-2 Inverter, Two Input NOR Gate, Emitter Follower

S-3 Shift Register

S-4 Divide-by-10, NOR gate, AND Transistor Gate

S-5 Divide -by-2

S-6 AND Transistor Gates (Two)

S-7 ]MV and Driver

S-8 Divide-by-8, NOR Gate

S-9 Mechanical Counter Unit

S-10 Comparator 1 Bit

S-11 Comparator 5 Bit

S-12 4kc Oscillator; EF 15; INV. 1, 36, 38, 39; Diff. 1

8-13 Variable DMV

S-14 Differentiator

S-15 Shaper

S-16 Dual AND Transistor Gate

S-18 Flip-Flop

S-19 Fractional Bit Delay Switch

S-20 Manual Delay Adjust

S-21 DCN, EF, and SW 10-2

S-22 On-Off Test Switch

S-23 Keyer Tuned Circuit

S-24 Keyer

iv

4

TABLE OF CONTENTS - PART II (Cont'd.)

Section

S-25 Mixer Amplifier

S-26 Band Pass Filter

S-27 Limiter Amplifier

S-28 900 Phase Shift Integrator

S-29 Driver Amplifier

S-30 Phase Detector

S-31 Low Pass Filter

S-32 Decision Circuit

S-33 Power Amplifier 1 and 2

S-34 Buffer Amplifier

S-35 Noise Feedback Band Pass Filter

S-36 Band Limiteed Noise Amplifier #l

S-37 Band Limited Noise Amplifier #2

S-38 Noise Amplifier

BD-A Test Facility Coding System

BD-B Block Diagram Coding

BD-C Rack Area and Circuit Designation Layout

BD-D Keyer Converter Layout

BBD-l Clock Pulse Generator, Part 1 of 2

SBD-2 Clock Pulse Generator, Part 2 of 2

BD-3 Transmit Character Pulse Generator

BD-h Receive Character Pulse Generator

BD-5 Pattern Generator and Transmit Register

BD-6 Receiving Register and Comparators, Part 1 of 2

vC.

TABLE OF CONTENTS - PART II (Cont'd.)

Section

BD-7 Receiving Register and Ccmparators, Part 2 uf 2

BD-8 Mechanical C-inters

BD-9 Decimal Decoder and Meter Indicator

BD-I0 Test Fecility Counter Functions

BD-11 FSK Keyer and Converter

BD-12 Master Block Diagram

SIV

i''A

~vi

LIST OF FIGURES - PART II

Section

3.0 TEST FACILITY

Fig. 3.0 Test Facility Fnotograph

Fig. 3-.1 Pulse Sequence Tiagram

-Fig. 3.3 Keyer and Filter Table

Fig. 3.4 System Phase Table

Fig. 3.5 System Phase Characteristics

Fig. 3.6 Basic Phase Detector Wavefoiis

Fig. 3.7 Decision Circuits Waveforms

4. g

Fig. 4.1a Circuit Diagrams

Fig. 4.1b Circuit Diagrams

Fig. 4.1c Circuit Diagrams

Fig. 4.2a Band Pass Filter Characteristics

Fig. 4.2b Band Pass Filter Character'istics

Fig. 4.2c Band Pass Filter Characteristics

Fig. 4.2d Band Pass Filter Characteristics

Fig. 4.2e Band Pass Filter Characteristics

Fig. 4.2f Band Pass Filter Characamsritics

Fig. 4.3a Circuit Diagrams

Fig. 4.3b Circuit Diagrams

Fig. 4.4a Phase Detector Circuit

Fig. 4.4bo Phase Detector Circuit

Fig. 4.5 Phase Detectc'r Waveforms

Fig. 4.6 Phase Detector Cnaracteristic

vii

7

ILIST OF FIGURES - PART II (Cont'd)

Section

Fig. 4-.7a Low Pass Filter Curves

Fig. 4.-7b Low Pass Filter Curves

Fig. 4.7c Low Pass Filte! Curves

Fig. 4.7d Low Pass Filter Curves

Fig. 4.7e Low Pass Filter Curv3s

Fig 4.7f Low Pass Filter Curves

Fig. 4.8 FSK Converter Block Diagram

Fig. 4.9 Noise Feedback Control Block Diagram

Fig. 4.10a Wave Form Photos

Fig. 4.10b Wave Form Photos

Fig. 4.10c Wave Form Photos

Fig. 4-lOd Wave Form Photos

Fig. 4.11a Wave Form Photos--

Fig. 4.11b Wave Form Photos

Fig. 4.1-1c Wave Form Photos

Fig. 4.lld Wave Form Photos

Fig. 4 -.12a Wave Form Photos

Fig. 4.12b Wave Form Photos

viii

INTRODUCTION - PART II

The following pages, comprising Part II of the final report on

FAA/BRD-80 "Analysis of Advanced Data Transmission Tecaniques," consist

of detailed information relating to Sections 3 and 4 of Part i, according-

ly numbered Sections 3 and 4, and a supplementary group of schematics and

block diagrams designated Section 9. Part II contains no intervening

sections.

The report has been divided in this way tJ separate its total bulk

into two roughly equal parts and to improve its utility. For those prima-

rily interested in circuit design and layout and operating details relat-

ing to the Test Facility and experimental converters, Part II will serve

as a convenient reference.

Ic

SECTION 3.0 TEST FACILITY (PART II)

3.1 Introduction

The Test Facility was designed as a complete FSK binary infor-

mation link with provision for performance evaluation. Oper-

ation is based upon optimized circuit conditions with the ability

to present various data for each of several test parameters. It

has been constructed on tstandard relay racks with a plug-in cir-

cuit breadboard design. A description of the Facility and Keyer-

Converter along with their fiunction, layout, logic and operating

procedure follows. Fig. 3.0 is a picture of the Test Facility

and associated test equipment.

3.2 Function

The function of the Test Facility is to generate, transmit, and

receive a 6 bit test signal and to make a comparison of the trans-

mitted and received forms of that signal. The system is designed

to be used with Keyer-Converters capable of accepting pulse lengths

of 1 to 30 milliseconds. Included in the Facility are provisions

for error correction and null evaluation along with bit error rate

and character error rate measurement. These functions are per-

formed by 8 counters as indicated in Fig. BD-I0.

3.3 Signal %

The signal generated by the Facility is a repetitive 6 bit charac-

ter with odd parity injected in the sixth bit. The pulse l.engtb

can be varied in six steps: 1 ms, 2 ms, 5 ms, 10 ms, 20 ms, and

30 ms.

3-1

" ~10

30 ms. The message can be selected for any mark-space code

by the 5 bit-selection switches. In addition to the message

block, transmitter and receiver timing pulses are generated

for use in the logic circuits. These pulses, along with their

position in respect to the signal, are shown ira Fig. 3.1.

3.4i Layout

The Test Facility has been constructed on two standard relay

racks. Pictorial layouts appear in Fig. BD-C and Fig. BD-D,

showing rack area designations, their function, corresponding

circuit block diagrams, circuit and card functions, and lo-

cations.

The mair relay rack containing the Facility is designated by

areas coded A-1 through A-7. These areas include the clock

pulse generator, mechanical counters, shift registers and

comparators, pattern generator, and transmSt-receive pulse

generator. The auxiliary relay rack. is designated area A-8

and contains the optimized FSK Keyer-Converter portion of the

system.

The Test Facility uses si-andard X-Y coding nomenclature for

laeout location. See Fig. BD-A. Each eyelet, ocircuit board,

and area can be described by reference to a 9 digit code, based

on a combination of letters and numerals. Example designa-

tions are shown with their proper locations on the srea pic-

torial Fig. BD-A.

3-2

1'1

I

3.5 Diagrams

The operation of the Test Facility is covered ir the block

diagrams Fig. BD-l through Fig. BD-12. The coding of cirouits

on these block diagrams is given in Fig. BD-B. In addition,

area, location, and eyelet designations are given on each

block to facilitate locating circuits and circuit intercon-

nections. Each block is marked with a reference schematic

number "S", which refers to a schematic diagram in the sche-

matic section.

3.6 "ower Requirements

The Test Facility requires external DC power for operation.

The voltage and current requirements are as follows:

+ 10 volts @ 500 ma

- 10 volts @ 2 amps

In addition, an external audio noise source and an audio RMS

voltage reading instrument are necessary for hdjuisting SNR

ratios in the Keyer-Converter section for test purposes.

3.7 Facility

The operation of the Facility is covered in Fig. BD-12, a

Master Block Diagram of the Test Facility. Each major section

will be considered separately.

3.7.1 Clock Pulse Generator

The Clock Pulse Generator is located in Area A-1 aned

is covered on block diagrans in Fig. BD-1 and Fig. BD-2.

3-3IL

"The function of the Clock Pulse Generator is to create

a series of transmit and receive timing pulses with the

proper delays at six selectable bit rates.

The circuit operates from a stable crystal oscillator

(S-12) which produces 9 4 ke square wave output. The

pulse Length Selector Switch SW-lA selects this out-

put or a submulitple for use in creating the TB and

[ RB pulses. The TB pulses are formed directly by a

countdown of 4 and the proper differentiation, gating,

and inversion. The formation of the RB pulses is

identical with that of the TB pulses with the exception

of three input pulse delay ci-cuits.

V [Fractional Bit Delay Switch SW-2 (S-19) controls the

input to Shift Registers 1 and 2, allowing the RB

pulses to be shifted in four 1/4 bit steps. The 1/8' Bit Delay Switch SW-16 (S-12) provides an additional

1/8 bit delay in all positions of the Fractional Bit

1. Delay Switch. The Variable DMV.-1 (S-13) is controlled

by the second section of (SW-1B), the Bit Length Se-

lector Switch, and has a vernier control continuous

delay of 0 to 7.5 milliseconds. The combination of

these delay circuits is sufficient to produce the

required delay in the receiving pulses to correspond

* with the delay in the Keyer-Converter used with the

system.

3-4I 1

The following bit lengths are generated in the system

with the Pulse Length Selector Switch in the position

indicated:

Position Bit Length

* 1 i ms

2 2

3 5

S4 10

5 20

6 30

The TB and RB pulse lengths do not exceed 20 micro-

seconds in any position of the Pulse Length Selector

[ Switch.

3.7.2 Transmit Character Pulse Generator

The Transmit Character Pulse Generator is located in

Area A-7 and is covered on the block diagram in Fig.

BD-3. The function of the Transmit Character Pulse

Generator is to create the TL pulses (Fig. 3.1) from

the TBo pulse.

The TBo pulse is sent through a series of 3 counters

and is NOR gated in 6 combinations. This result is

AND gated with TB to set the transmit TL pulses in2

the center of the selected bit. The outputs of the

generator are tied to SW-4, the Phase Delay Selector

3-5

I¶

Switch on BD-4.

3.7.3 Receive Character Pulse Generator

The Receive Character Pulse Generator is located in

Area A-7 and is covered on the block diagram in Fig.

BD-4. The function of the Receive Character Pulse

Generator is to create the RL pulses frca the TL

pulses.

Phase Delay Selector Switch SW-4 selects a TL pulse

for triggering FLip-Flop-i (S-18). RBo is used to

reset F/F-l and shift the signal from Shift Register-4.

AND gating with the proper RB pulse produces the re-

quired character rate receive pulses. The Phase Delay

Selector Switch provides proper selection of system

character biming.

3.7.4 Pattern Generator

The Pattern Generator is located in Area A-6 and is

covered on the block diagram In Fig. BD-5. The

function of the Pattern Generator is to generate a

5 bit pattern and to inject Add parity in the 6th bit.

Manual pattern switches are provided to code into the

NOR gates a mark or space (ground or -10 volts). At

time TL6 2 these levels are gated and inverted and

passed into the Transmit %ift Register. Odd parity

(mark) is injected in the 6th time slot as a function

3-615

of Counter C-I4. The output of C-14 is sampled at

TL52 and gated into the Shift Register SR-15 at TL62,

which resets C-14 and reads the next cha 4ccer code

into the shift registers.

The outpu,; of the Pattern Generator Transmit Regis-

ter are sent to the keyer and 1 Bit Comparator-l. The

coded input levels are sent to the 5 Bit Comparators.

3.7.5 Receiving Register and Comparators

The Receiving Register and Ccmparatorf are located

in Areas A-4 and A-5 and are covered on block diagrams

Fig. BD-6 and Fig. BD-7. The function of the re-

ceiving registers is to place the incoming signal

timing in the correct phasing for comparison with the

transmitted signal and to provide logic outputs for the

various counters. The comparators receive the signal

from the receiving registers and compare it with the

transmitted code.

The signal from the detector (decision circuit) is

center sampled and shifted out of Shift Register SR-18

by RBo and into the receiving registertof 5 Bit Com-

parator-i. The output of this Comparator (COMP 1')

is negative when the comparison is correct.

If a null occurred d• :ing any bit the output of One

Bit Compa'ator COMP-2 will be inverted with respect

3-7

16

to the signal from the detector and this output will

be shifted through Correction Register SR-19 to the

receiving register of 5 Bit Comparator-2 by RBo. The

output of this Comparator (COMP 21) is negative when

the comparison is correct.

Null count logic is provided by IOOMP-3 output, sampled

at RB1 ' in AT-19. Bit error count is made by a one

bit comparison with the transmitted signal in COMP-I

and sampling by R1I 1 ' in AT-17. The number of marks

11 occurring are counted in C-15 and provide ERROR and

ERROR2 outputs. ERROR is negative for 1, 3, or 5F marks in a 6 bit block (odd parity check). A ONE NULL

signal is also provided from N-16 for use in the Me-

chanical Counter section.

3.7.6 Mechanical Counters

The Mezhanical Counters are located in Area A-2. Their

associated logic and driving circuitry is located in

Areas A-3 and A-4. The circuitry is covered in the

block diagram on Fig. BD-8. The function of this

section is to count mechanically the various logic

circuit outputs.

%

The mechanical counter units opcrate in the plate

circuits of 35C5 pentodes (S-9). Each 35C5 is driver

by a 2N597 transistor driver (S-7) which operatez from

a DMV (S-7), furnishing f3 15 to 20 millisecond driving

3-817

wavc!fonm. Three Counters (MC-i, MC-2, and MC-3) con-

tain divide-by-lO counters on their DMV inputs for

high speed operation. The remaining counters have

direct driven DMV's. The mechanical counter unit has

a self contained Power Supply (S-i).

I The function of the remaining logic circuits can best

V be explained by consideration of the input requirement

for eacb counting operation separately in Counter

Function Table, Fig. 3.2.

3.7.7 Divide-by-lO Decimal Decoder and Meter Indicator

The divide-by-10 Decimal Decoder and Meter Indicator

circuits are located in Areas A-3 and A-4 and are

covered on the block diagram in Fig. BD-9. The function

of this circuitry is to provide high speed operation of

Counters MC-1, MC-2, and MC-3 by dividing the inputs by

10 and providing a units readout meter.

The counters operate with the logic as indicated in the

logic diagram on Fig. BD-9. Automatic reset is pro-

vided by RL1 3 '1 A momentary toggle switch is provided

for manual resetting. Readout currentg are controlled

by individual fixed resistors in the counter outputs

A', B', C', and D'. A meter adjust vernier is provided

to control the meter current to give approximately

linear indications.

3-918

3.8 Facility Logic and Counter Functions

The Facility logic is shown in Fig. BD-10. Counter locations

are given in the pictorial provided. Reference should be made

to Master Block Diagram, Fig. BD-12, and Counter Fanction Table,

Fig. 3.2, for a complete analysis of system operation.

The ten counting functions shown in Fig. BD-1O are performed

by 8 mechanical counters and two simple arithmetic calculations.

If tests are being performed at high bit rates and low SNR ratios,

electronic counting must be used to supplement the mechanical

counters for accurate count. These may be connected into the

system at the inputs to DMV's 2 through 9. See Fig. BD-8.

3.9 Facility Operating Procedure

The following operating procedure covers the Test Facility

V• Areas A-1 through A-7 and all controls located therein. It

assumes a complete and fuActioning Keyer-Converter, as described

in Section 3.10 of this report, and proper input and output

connections to the Facility.

1 - Apply power to all circuits by operating the ex-

ternal supplies and the self-contained mechanical

counter supply in A-2.

2 - Select the proper pulse length for transmission

with Switch SW-I (AlL52).

3 - Salect a message on the 5 bit Code Selection

Switches SW-5 through SW-9 (A6L23). See pictorial

on Fig. BD-5.

3-10

i7

4- Adjust 1/4 Bit Delay Switch SW-2 (ALL62), 1/8 Bit

Delay Switch SW-16 (AIL1UR056), amd variable con-

trol on DMV-1 (AIL33R033) for center sampling of

the received signal by RBo at SR-18 (AfLl2), using

an cscilloscope to monitor the adjustment.

5 - Adjust Phase Delay Selector Switch SW-4 (A7L52) for

RL1 3 reset at Counter C-15 (A.L73) to occur during

the parity (6th) bit. (Note: Proper adjustment

of SW-4 will permit only Message Blocks with No

Error (MC-1) to count with a noise-free signal from

the detector and a message other than alternate mark-

space).

L 6 - Switch SW-1O is provided as an ON-OFF Test Switch

(A3L12) and should be operated to start and stop

the test.

7 - Switch SW-17 (A6L71) should be placed in keyed po-

sition for Test.

The Facility is now properly adjusted for Keyer-Converter evalu-

ation, Supplementary checks and adjustment of Counters C-16,

C-17, and C-18 can be made with the controls ?rovided (R156 on

Divide-by-lO Counter) for proper digits read-out on Counters

MC-1, MC-2, and MC-3. All counters should be reset with the

switches provided before each test.

3.10 Keyer and Converter

The Test Facility is provided with a complete matched set of

3-1120

tone keyers and optimized converters located in Area A-8. The

circuit parameters are based on those discussed in General

Dynamics/Electronics-Rochester Preliminary Report for Task I

and Interim Repoiu for Task II, "Analysis of Advanced Data

Transmission Techniques," Section 5.1.

A block diagram of the Keyer-Converter is shown in Fig. BD-11.

The series of plug-in units provided will adapt the unit for

operation at 6 different bit rates. Fig. 3.3 presents the

pertinent keyer and filter data for the test parameters. Each

block of Fig. BD--11 is referenced to a schematic "S" number.

Interconnections are shown on Fig. BD-11.

An external noise generator and RMS reading voltmeter must be

used with the system for evaluation.

3.10.1 Keyer4 The Keyer, shown on Schematic S-24., is a feedback

oscillator with provision for accepting plug-in tankcircuits (S-23). The tank circu.ts are so constructed

that a keying signal (-10 volts) into the keyer will

short the keying capacity to rGround and so lower the

frequency of oscillation. Voltage feedback stabilizes

the keyer output. Six tank circuits are provided with

the Keyer (Fig. 3.3) and tre tuned to give optimum per-

formance and balanced converter outputs.

3-12

21

3.10.2 Band Pass Filters

Two identical Band Pass Filters are provided for each

bit length (Fig. 3.2) and their basic configuration is

shown on Schematic S-26. These filters serve two pur-

poses in the operation of the converter.

Band Pass Filter #1 follows the Mixer Amplifier and

defines the system bandwidth, rejecting all noise com-

ponents outside this band. The design criteria for

this filter will be discussed in Section 4.

Band Pass Filter #2 follows Limiter #3 and provides a

matched phase characteristic with that of Filter #1 at

the center of the passband (within 20). In addition,

Filter #2 contributes a phase shift characteristic

throughout the band which contributes to converter

operation by establishing a reference channel.

5.10.3 900 Phase Shift Integrator

The 900 Phase Shift Integrator (S-28) is a modified

operational amplifier with capacitive feedback. This

amplifier provides a constant 900 phase shift over the

frequency of operation, thereby ccmpleting the phase

shift necessary in the reference channel for driving

the phase detector. The system phase table of Fig. 3.4

explains the phase relationship between the signal and

reference channel after the signal has passed through

3-1322

the band pass filters and che 900 Phase Shift Integ-ator.

Fig. 3.5 shows the phase detector drifing waveforms for

center frequency and the two keyed frequency conditions.

3 .i10. 4 Limiter Amplifiers

The Limiter Amplifiers (S-27) provided with the con-

verter are operated in cascade to provide a high system

¶ gain. Each Limiter is an operational amplifier with

voltage feedback in each section to provide a large dy-

namic range of input fo-r a constant square wave output

amplitade of approximately 1 volt peak-to-peak. The

LimiTers provide gain sufficient to operate the con-

{. verter with input levels (measured at the output of BPF #1)

of less than 1 millivolt.

3.10.5 Driver Amplifiers

The Driver Amplifiers ,S-29) receive the outputs of the

Limiter Amplifiers #4 and #6 and boost this waveform to

an amplitude of 7 volts peak-to-peak for use in driving

the AC coupled feedback power amplifiers.

3.10.6 Power Amplifiers %

The Power Amplifiers (S-33) used in the converter are

transformerless complementary symmetry feedback amplifiers

capable of furnishing a 4 volt peak-to-peak driving wave-

form into the 8 ohm primary winding of the phase detector

tiansformer. Peak powers of over 250 milliwatts can be

23-14~2 3

provided during detector conduction cycles. The output

gain control is in the feedback loop.

3.10.7 Phase Detector

The Phasep Detector (S-30 and S-17) combines the signal

and reference channels by transformer coupling in a

manner to provide diode conduction on a positive going

reference and signal waveform combination. fig. 3.6

shows the basic detector waveforms for a center Zre-

quency condition. Phase detector outputs are obtained

by the net difference in voltage developed across C1 and

C2 (S-17) over the period of a bit. This integrated wave-

form is referenced to + 5 volts and adjusted (gain control

on the Power Amplifiers) for t 5 volts output in respect

to this reference. The reference waveform is maintained

at an amplitude greater than one-half that of the signal

waveform.

3.10.8 Low Pass Filter & Emitter Follower Driver

The Low Pass Filter (S-31) is driven by the phase detector

and its output is referenced to + 5 volts. Six plug-in

Low Pass Filters are provided for operation at each pulse

length (Fig. 3.3). The Emitter Followers (S-32) provide

isolation and current gain for drIving the decision cir-

cuitry without shifting the reference potential signifi-

cantly.

3-15

24

3.10.9 Decision Circuit

The Decision Circuit (S-32) is designed to provide a mark-

space (Gnd. or - 10 volts) output, switched each time the

incomi::g waveform crosses the reference potential (+ 5 volts).

Fig. 3.7 shows the waveforms present in the decision cir-

ouitry on an alternate mark-space code. In addition to a

signal -,.itput, the decision circuit has an adjustable null

detection network, which provides an output (Gnd.) when the

signal fails to pass a preset level (positive or negative

in respect to the reference voltage). Signal and Null out.-

puts are used to drive the receiving regir.cers where they

are center sampled Dy RBo.

3.10.10 Mixer Amplifier

V" The Mixer Amplifier (S-25) provides a means of mixing noise

and signal and the- necessary isolation for SNR measurements.,

¶ Switches SW-14 and SW-15 (Fig. BD-II) select noise or sig-

nal inputs separately. The mixer gain control is located

in the feedback loop and controls the amount of signal and

noise driving BPF #1.

3.11 Noise Feedback Control

An external noise source must be used with the keyer-converter to

provide a white noise spectrum for SNP evaluation of the system.

H• General Radio Random Noise Generator type 1390B or similar type

audio noise source is recommended for use ith the system.

I The noise source should be fed through an external bandpass filter

SB3-16

S25

adjusted for a passband of t 1.2 kc at the center frequency used.

'The output of this filter is fed to the BNC connector input of the

Noise Amplifier on A8Lll as shown on Schematic S-38. This high

gain amplifier has been shielded and decoupled to provide maximum

isolation from supply line transients, associated circuitry, and

stray fields.

The noise input to the amplifier must be sufficient to provide a

nominal feedback voltage of 1.7 volts at point "X". A typical in-

put using the GR 1390B is 2 volts, read on the instrument output

meter. A feedback loop is provided to stabilize RMS noise amplitude

without destroying the Gaussian characteristics of the noise.

A noise output, obtainea at A8LllR086 and fed through a banana

Jack R051, is amplified by the Buffer Amplifier (S-34) on A8L23

with its input on R015. The output of this Operational Amplifier

(R043) is fed through a Bandpass Filter (A8L33). Four filters

(S-35) are provided for this function. They are used as follows:

Noise Filter

Pulse Length Center Freq. Bandpass

1 ms 8 kc 900 c/s

2 4 450

5 1.6 190

10 1.6 190

20 1.6 47.5

30 1.6 47.5

The Noise Feedback Filter output is fed to Band Limited Noise

3-1726

Amplifier No. 1 (S-36) (A8L.3R017), and its output (R028) is

taken to Band Limited Noise Amplifier No. 2 (S-37) (A8L23Rol6).

Both amplifiers are operational amplifiers. The output of

Amplifier No. 2 (RO47) is taken to R065 via banana plug ROIl and

transformer coupled to a Bridge Rectifier (S-38). The WC out-

put of this rectifier is filtered by a long time constant L-C

network and DC coupled to an emitter-follower. The output of

this emitter-follower is point "X" and provides a feedback

voltage, which is a function of the noise in a limited pass-

band.

Results show that this system of noise control appears to be

the only feasible means of making long term narrow band noise

measurements. A Flow Corporation Random Signal Voltmeter type

12A1 was used for noise measurements. This instrument has a

time constant of 16 seconds.

No gain controls are provided in the noise control system.

After adjustment of noise input level from the noise source

for the nominal DC feedback voltage at point "X", all measure-

ments are based on the existing noise level present out of the

Mixer Amplifier.

3.12 Ke'er and Converter Operating Procedure

The Keyer and Converter are supplied with six sets of plug-in

cards for operation of the system as indicated in Fig. 3.3.

These plug-in units consist of the following:

3-18

27

1. Keyrr Tuned Circuit

2. nTo Identical Band Pass Filters

3. Low Pass Filter

Each of the circuits has been adjusted for optimum conditions

under actual operation and test. The phase detector RC time

constant has been included on the Low Pass Filter card and

has been selected to minimize non-linearities existing in the

system under noise conditions. The keyer tuned circuit has

been adjusted to provide a specified shift and a reference

(+ 5 volts) output, from the phase detector on alternate mark-

space code.

The following procedure should be followed to place the Keyer-

Converter into operation or in changing Prom one set of plug-

in units to another:

1. Place plug-in cards in their proper positions as

follows:

Position Card

L 31 Keyer Tuned Circuit

L 71 Signal Filter

L 13 Reference Filter

L 62 Low Pass Filter

2. Apply power to the system.

3. With Jumper J-1 removed adjust the decision circuit

for reference (+ 5 volts) output (A8L72Ro4l).

4. Adjust the variable null control (A8L72R026) for

3-19

2 C

the null width desired by measuring between R015 and

Ro16.

5. Adjust the amplitude of the output of Power Amplifiers

#1 and #2 to provide t 5 volts (with respect to the

reference) at the output of the Low Pass Filter w..th

switch SW-17 (A6L71) in mark and space positions, re-

spectively (maintain reference output greater than 1/2

signal output). Return this switch to keyed position

after adjustment has been completed.

6. Connect an audio noise source to the BNC connector pro-

vided on LlI through an external bandpass filter with

a bandpass of t 1.2 kc/s of the center frequency of

operation. Using the correct Noise Feedback Filter

in L33, (see Section 3.11) adjust the noise source out-

put to give 1.7 volts DC at point V'" in the Noise Ampli-

fier.

7. Adjust the Test Facility as instructed in Section 3.9.

Measurement of SNR ratio can be carried out at the output of Band

Pass Filter #1 (A8L7mo4l) with a long term averaging RMS reading

voltmeter. Amplitudes can be controlled by the output control on

the keyer and mixer. It is advisable, however, since input noise

levels are limited by the feedback loop, to set the mixer control

fully clockwise (maximum) and to adjust SNR ratios by using the

keyer output control. Switches SW-14 and SW-15 are provided for

convpnience in making system measurements. These switches apply

signal and noise independently to the mi>er amplifier.

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SECTION 4.0 CONVERTER DESIGN (PART II)

4.1 Introduction

The converter section (Fig. 4.8) of the Test Facility was designed

to test the predictions of Montgomery 3 and to provide a set of opti-

mized data at each of six pulse lengths. In order to accomplish

this task, it was necessary to provide keyers able to accept an in-

put code and generate an FSK signal with the prescribed frequency

shift. A source of white noise was also necessary to correlate

the results with predicted performance. A highly de-,ailed analysis

of t'e converter is outside the scope of this report; presented

in this section are some of the more important design considera-

tions.

14.2 Converter Operation

Signal and noise can be selected individually by Switches S1 and [n

(Fig. 4.8) and their levels measured at point A, where the values

of signal-to-noise power ratio in the system bandwidth are defined.

After three stages of limiting, providing gain at low input levels

squaring action at high inputs, the signal splits into the sig-

nal and reference channels. In the signal channel more gain is

provided through another limiter, a driver amplifier, and a power

amplifier to drive the signal winding of a phase detector. In the

reference channel the phase shift filter alters the phase of the

signal, causing lead or lag of a magnitude proportional to the

difference between the signal frequency and the center frequency

of the phase shift filter. The reference signal now paszes through

4-1

I

an integrator, which produces a 900 phase shift in the reference

signal, and, after two stages of limiting, it is applied through

a driver amplifier and a power amplifier to the reference winding

of the phase detector.

At center frequency the signal and reference square waves are 900

out of phase at the input to the phase detector and there is no

output. As the frequency moves above and below the center value,

Sthe phase shift in the reference channel vari-:,s and the detector

output will go positive and negative, accordingly. A low pass

filter removes the carrier and a decision circuit centered about

zero output frcm the phase detector gives mark or space output, as

the frequency at the input varies above or below the center fre-

quency.

4.3 Converter Circuit Design

4.3.1 The Mixer Amplifier

In order to perform converter SNR measurements, a circuit

was required to mix signal and noise in a linear manner so

that each one could be measured separately and then added

to obtain the combined effect without change in the measured

value of either. The mixer amplifier was required to drive

a bandpass filter with a purely resistive source impedance

of 600 ohms. These requirements led to the selection of an

ope-ational amplifier (Fig. 4.1A) to sum signal and noise.

Fig. 4.1B shows the amplifier taodifVea for use a, a mixer.

Fig. 4.1C shows the basic circuit of the operational amplifier.

S4-2

This amplifier will supply voltage gains of 20 db, which

are independent for signal and noise. The output impedance

is of the order of 1 ohm and, therefore, the use of series

resistance provides ideal matching for all loads.

4.3.2 The Bandpass Filters

Fig. 3.3 shows a table of date pertinent to the design

specifications of the bandpass filters. Section 4.3, Part I,

discusses the design criteria for these filters. The response

characteristics are shown in Fig. 4.2A through Fig. 4.2F. The

filters (S-26) are two branch L-C units with bandwidths shown

on each curve to the 3 db points. These filters provide phase

shift characteristics of t 900 across the bandpass. The first

bandpass filter of Fig. 4.8 defines the noise bandwidth of the

converter and maximizes SNR ratio. The second bandpass fil-

ter is matched to within 20 of the first and establishes areference phase (Fig. 3.4).

4.3.3 Limiters

The function of a limiter amplifier in an FM system is to

remove amplitude variations from the received signal. Two

requirements for a limiter are operation bver a wide range

of input voltages and mainten-ince of a symmeLrical waveform

over this dynamic range. A circuit which meets these require-

ments is a modified operational amplifier with a non-linear

feedback network, consisting of two diodes in parallel with

opposite polarity. Fig. 4.3A shows the basic circuit con-.

4-3

figuration.

The diode selected for the feedback network was chosen for

a minimum forward voltage drop change for a given change in

current. The 1N81.6 diode used for this function exhibits

a forward voltage change of 0. volts to 0.8 volts (2X) for

a change in current from 10 microamps to 10 milliarips (1000K).

At very low levels the circuit acts as a P'imple amplifier.

As the input is Increased, limiting starts to take place and

with further increases very little change in peak-to-peak

output will occur. The slope of the leading and trailing

edge of the waveform will increase to the limit of the cir-

cuit elements when limiters are cascaded. These amplifiers

are responsible for the sensitivity (less than 0.5 millivolts

at all pulse lengths) and wide dynamic range (70 db voltage

gain) of the converter.

The function of the integrator in Tche converte.r is to pro-

vide a fixed 900 phase shift throughout the freq~uency range

of operation. The basic operat'",onal amplifier with a capaci-

tive feedback loop was selecteei to perforqi this function.

Fig. 4.3B shows a schematic of this amplifier. Rl was made

equal to 600 ohms to terminate the filter correctly, and

l/W C was made equal to 600 ohms at 8 kc, giving unit gain

at that frequency and a gain of 5 at 1.6 kc. The phase shift

through the integrator was within 20 of 900 over the frequency

44-

range of operation.

4.3.5 Driver and Power Amplifiers

The output of the limiter amplifiers after squaring is only

1.2 volts peak-to-peak, which is inadequate to drive a

saturating transistor stage directly. The driver amplifiers

were designed for use at this point in the system to provide

a gain of approximately 6 and an output centered about

ground. The power amplifiers are ccmplementary-symmetry

emitter-follower output devices with the ability to furnish

a 4 volt peak-to-peak output into 8 ohms for driving the

phase detector.

4.3.6 The Phase Detector

The phase sensitive detector is shown in Fig. 4.4A with

reference symbols. Fig. 4.5 presents wave form diagrams for

a square wave input, total signal and reference amplitudes,

ana a linear charge and discharge characteristic assugmed for

the capacitors. As the phase of the reference Fnd signal

changes from the 900 (center frequency) condition depicted,

longer or shorter charge and discharge times will anply for

the Capacitors Cl and C2 , and a net DC level change in the

output E with respect to F will take place in an amount

proportional to the phase change. Transformer coupling is

necessary in a detector of this description for two major

reasons: (1) to provide a step-up and sumning effect large

enough to give the desired output voltage swing and (2) to

,*4-5

enable the insertion of a convenient reference voltage

level on the output.

An investigation of the circuit after design showed some

peculiarities of loading on the power amplifiers. It was

determined that Capacitors C1 and C2 were continuing to

charge long after such charge should have ceased. Fig.

.4.AB shows a sketch of the expected voltage function and

the actual voltage function observed at point A when point

D is grounded. Ringing shown was due to lack of load on

the transformer and is apparently not detrimental. The

reasons for the effect shown were not immediately obvious,

but experiment showed that a reduction in the capacitive

load cut down this excess charge time. Too small a ca-

f pacity was undesirable since the maximum voltage would

then be reached with an exponential curve. A compromise

of values was effected so that near-linearity was obtained

with very little excess ciarge time showing. The excellent

linearity of the resulting phase detector is shown for one

set of parameters (30 ms) by the oatput voltage vs. fre-

quency input curve in Fig. 4.6.

4.3.7 The Low Pass Filter

A simple two element low pass filter was designed for each

pulse length, assuming zero source impedance and a 10 K

load resistance. The filters were designed for the 3 db

4-6

L_3

cutoff shown in Fig. 3.3 and were constructed to have no

over-shoot in their frequency characteiistic. Response

curves for these filters are shown in Fig. 4.7A through

Fig. 4.7F.

The low pass filter and the phase detector are referenced

to +5 volts, established by a bleeder in the decision cir-

cuitry. A pair of emitter followers are used for isolation

and to minimize reference level changes due to the loading

of the decision circuit.

4.3.8 The Decision Circuit

The decision circuit is a voltage comparator circuit de-

signed to give a mark-space or space-mark output change as

the signal from the detector crosses the reference potential

eo (+5 volts). A potentiometer is provided for adjusting the

voltage comparator to provide an output which is neither mark

nor space under no signal conditions. A second control pro-

vides adjustment of a null zone ew from 0 to 70% of the peak-

to-peak signal amplitude centered about eo.

4.4 The Noise Source

A General Radio Random Noise Generator type 1390B was used as a

noise source.• Examination of the output of this generator in a

narrow bandwidth showed amplitude fluctuations of a magnitude that

made setting up for a long test run impossible. Examination of the

characteristics of random noise showed that the envelope of the out-

;-7

ELL

put of a narrow band Gaussian random process contains frequency

components down to very low values and that these components were

causing variations in the RMS voltmeter readings, even though the

unit employed (Flow Corporation Random Signal Voltmeter Model 12Al)

had a time constant of 16 seconds.

It was determined that the output of a low pass filter following

rectified narrow band Gausaian random noise is a function of the

RMS value of input. Therefore, if a bandpass filter ou~put were

rectified and fed through a low pass filter with a time constant of

one second, the resulting output could be used to control the gain

in the noise channal. Variations less than I c/s would be greatly

Sreduced., depending upon the gain in the feedback loop.

This system of feedback control (Fig. 4.9) was used with go.-d

success. The necessary amplifiers were employed in conjunction

with an available bandpass filter to furnish a narrow band AC noise

voltage to a bridge rectifier and low pass filter. A large time

constant (several seconds) was used in the low pass filter and

the resulting DC voltage was used to control the gain of a linear

amplifier.

A commercial bandpass filter (Spencer Kennedy Laboratories Variable

Electronic Filter Model 302) was used to limit the bandwidth of the

noise source. The filtered output was fed through the gain con-

trolled amplifier to the mixer. Reduction in the noise bandwidth

allowed operation at a much higher noise level without clipping

4-8

41'

and eliminated self-resonent responses of the main system filter

at undesired high frequencies. With a noise bandwidth out of the

commercial filter 2.4 kc/s centered about the converter bandpass

mid-frequency and a level of 680 millivolts, the resistive attenu-

ator at the noise feedback bandpass filter was adjusted to give

-1.7 volts bias to the main noise amplifier at, point "X" (S-38).

Under these conditions, changes of -50% and +100% in noise produce

an output change measured after the main system bandpass filter of

less than t4.0%

4.5 Initial Converter Set Up

A single tone signal was fed through the mixer at the approximate

working level of the converter and the waveforms at the output of

the power amplifiers in each channel were examined. Adjustments of

DC operating level were made at point A and point B (Fig. 4.8) so

that the waveform on both channels was symmetrical. These adjust-

ments were effected by means of bleed resistors to the power supply

lines and were made once only, at the beginning of tests. Noise

alone was fed into the system and the output of the low pass filter

was examined on a DC meter with a long time constant. In general,

the reading was not zero, and the resistors in the two halves of

the phase detector were unbalanced slightly to produce a mean read-

ing of zero.

A keyed signal consisting of alternate mark-space tones was applied

which approximated the right amount of shift (Pig. 3.3). The low

pass filter output was examined with the DC meter. The keyed fre-

4-9

quencies were adjusted to give the right amount of shift and

zero output from the low pass filter. Each of the two keyed

frequencies was fed in separately and the gain of the power

amplifiers was adjusted to give a maximum deviation of +5 volts

out of the low pass filter. The converter was then considered

ready for operation at the chosen message rate.

4.6 Converter Waveforms

The operation of the converter is shown in a series of waveform

pictures taken under accual operating conditions at a pulse

length of 20 ms. Center frequency fo for this set of filters

is 1.6 kc/s with mark fl and space f2 t 17.5 c/s of center fre-

quency. A description of the photographs follows:

Fig. 4.10 al Input and output of the first bandpass filter at

F fo with SNR = 20 db.

Fig. 4.10 a2 Input and output of the first bandpass filter at

with SNR = 0db.

Fig. 4.10 a3 Output of limiter #4 at fo with SNR = 0 db and

20 db, respectively. Output amplitude is 1.2

volts peak-to-peak.

Fig. 1.l0 bl Input and output of first bandpass filter at fo

(no amplitude scale preserved).

Fig. 4.10 b2 Input to limiter #1 at fo with ein = 0.5 volts

peak-to-peak and output from limiter #2 with out-

put voltage eo = 1.2 volts peak-to-peak.

Fig. 4.10 b3 Input and output of 900 phase shift integrator at

14-i0

fo (no amplitude scale preserved).

Fig. 4.10 cl Output frou limiter #4 at fo for six SNR conditionsto c3

from top to bottom: No noise, 20 db, 15 db, 10 db,

5 db, and 0 db, respectively.

Fig. 4.10 dl Output waveforms from power amplifiers for fo, fl,to d3

f2, respectively, with eout = 3 volts peak-to-peek.

Fig. 4.11 al Output (mark) of decision circuit for No noise, SNRto a3

20 drb, and SNR = 15 db, respectively (leading and

trailing edges of waveform shown only).

Fig. 4.11 bl Output (mark) of decision circuit for SNR = 10 db,to b3

BNR = 5 db, and SNR = 0 db, respectively (leading

and trailing edges of waveform shown only).

Fig. 4.11 cl Output of low pass filter and decision circuit for

mark, mark, space, space, mark, space and 10 volt

amplitude.

Fig. 4.11 c2 Output of phase detector at fo and output of signal

power amplifier.

Fig. 4.11 c3 Phase detector waveforms across diodes DI and D2.

Fig. 4.11 dl Null circuit, decision, and sampling waveforms forto d3

null widths of 50%, 30%, and 10%, respectively.

Fig. 4.12 al Integrated output waveform of phase detector vs.to a3%

input 6ignal and reference waveforms for fo, fl, and

f 2 , respectively.

Fig. 4.12 bl Phase detector diode waveforms for fo, fl, and f 2 ,to b3

respectively, where total amplitude is 60 volts

peak-to-peak.

48 4-11

L 48

4--7 Conclusions

This section has presented some of the more important design

considerations and methods used to cope with them. A description

of the overall operation of the converter was given with special

emphasis on the more difficult concepts. Several waveforms were

photographed and appear here to demonstrate operation of the

converter and show the effects of noise. Although design of the

circuits is limited in many respects, proper adjustment of the

system will yield results which are close to the ideal.

The relationship between SNR ratio and pulse edge jitter (for-

tuitous distortion) is shown in a qualitative way in Fig. 4 .11a

and 4.11b.

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