burn-in & test socket workshop · plating thickness has the biggest effect on load board life....
TRANSCRIPT
March 3-6 , 2002Hilton Phoenix East/Mesa Hotel
Mesa, Arizona
Sponsored By The IEEE Computer SocietyTest Technology Technical Council
Burn-in & TestSocket Workshop
IEEE IEEE
COMPUTERSOCIETY
COPYRIGHT NOTICE• The papers in this publication comprise the proceedings of the 2002BiTS Workshop. They reflect the authors’ opinions and are reproduced aspresented , without change. Their inclusion in this publication does notconstitute an endorsement by the BiTS Workshop, the sponsors, or theInstitute of Electrical and Electronic Engineers, Inc.· There is NO copyright protection claimed by this publication. However,each presentation is the work of the authors and their respectivecompanies: as such, proper acknowledgement should be made to theappropriate source. Any questions regarding the use of any materialspresented should be directed to the author/s or their companies.
Burn-in & Test SocketWorkshop
Session 2Monday 3/04/02 10:30AM
Managing High Frequency Requirements
“Optimizing Load Board Design And Modeling For High FrequencyContactors”
Jeff Sherry - Johnstech International Corporation
“The New YieldPro Array Series Contactor”Julius Botka - Agilent Technologies
“Electrical And Mechanical Performance Characterization Of High FrequencyTest Sockets”
Lisa Steckley - IBM MicroelectronicsDr. Hanyi Ding - IBM Microelectronics
Technical Program
1
Optimizing Load BoardDesign and Modeling
forHigh Frequency
Contactors
Jeff Sherry, RF EngineerJohnstech International
2
Discussion Topics Modeling & its importance
Designing load boards for optimalperformance
Load board effects
Grounding schemes
Crosstalk improvements
Load board pad size and placement
Model validation & performance examples
3
Modeling & Its Importance
Determine potential problems beforebuilding hardware
Determine expected performance
Determine trends and sensitivity of circuits
Determine effects of tolerances
Determine interaction between componentsin system (device, contactor, handler, etc.)
Design for the device, form, fit, andfunction of the end application
4
Designing Load Boards forOptimal Performance
Microstrip and Coplanar Effects Substrate thickness ↓↓↓↓ Impedance ↓↓↓↓
Trace width ↓↓↓↓ Impedance ↑↑↑↑
Permittivity (ε(ε(ε(εr) ↓↓↓↓ Impedance ↑↑↑↑
Trace thickness ↓↓↓↓ Impedance ↑↑↑↑
Coplanar Waveguide Effects Spacing (pitch) ↓↓↓↓ Impedance ↓↓↓↓
Adding ground plane Impedance ↓↓↓↓
5
Load Board Effects Loss tangent affects insertion loss more at higher
frequencies
Uniformity of εεεεr and loss tangent vs. frequency
Substrate thickness affects inductance to ground
Increased frequency means thinner substrates
Substrate thickness and dielectric constant (εεεεr),along with line width, are major parameters incontrolling impedance
Plating thickness has the biggest effect on loadboard life
6
Load Board Effects Things to improve load board design
Eliminate right angles
Eliminate changes in line width
Separate high frequency traces with ground
Move clock traces away from other signallines
Place decoupling components close to thedevice
Use matched impedance traces up to thedevice or test contactor
7
Grounding Schemes Length and area of the ground path is very
important
Ground inductance should be minimized
Resistance of ground should be low (tominimize power supply voltage drop)
Grounding controls crosstalk between signals
8
Crosstalk Improvements
Increase the spacing (S) between traces
Minimize substrate height (H) while achievingmatched impedance
Route signals orthogonally between layers
Minimize parallel runlengths between signals
Use differential routing for clock or critical nets
9
Load Board Pad Size andPlacement
10
Load Board Pad Size andPlacement
11
Model Validation &Performance Examples
Validating the Model
Explain test results
Confirm if contactor will meet customer needs
Identify improvements to contactor
Identify improvements to load board (i.e. padsizes)
Determine equivalent circuits
Investigate changes to contactors to meetcustomer specific needs
12
Model Validation &Performance ExamplesLeaded Series Return Loss (S11) Data
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1 2 3 4 5 6 7 8 9 10Frequency (GHz)
Ret
urn
Loss
(dB)
Measured Test Data Taken by GigaTest Labs for.010" Thick ContactEquivalent Circuit Modeled Data for .010" ThickContactOptimum Load Board Layout Match Using HFSS
-20 dB Point 10.6 GHz from Measured Data
13
Model Validation &Performance ExamplesLeaded Series Insertion Loss (S21) Data
-2
-1.75
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0 1 2 3 4 5 6 7 8 9 10Frequency (GHz)
Inse
rtion
Los
s (d
B) Measured Test Data Taken by GigaTest Labs for.010" Thick ContactEquivalent Circuit Modeled Data for .010" ThickContactOptimum Load Board Layout Match Using HFSS
14
Model Validation &Performance Examples
10GBit/s BGA Non-Optimized Load Board Layout
15
Model Validation &Performance Examples
10GBit/s BGA Optimized Load Board Layout
16
Model Validation &Performance Examples
10GBit/s BGA With Non-Optimized Load BoardLayout
17
Model Validation &Performance Examples
10GBit/s BGA With Optimized Load Board Layout
18
Model Validation &Performance Examples
-40
-35
-30
-25
-20
-15
-10
-5
0
1 2 3 4 5 6 7 8 9 10Frequency (GHz)
Ret
urn
Loss
(dB)
Previously Standard Pad with Optimum Contact
Optimum Load Board Pad and Contact
Return Loss (S11) of Enhanced Pad Series Contact withPrevious Standard Pad and Optimal Load Board Pad
19
Model Validation &Performance Examples
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8 9 10Frequency (GHz)
Inse
rtion
Los
s (d
B)
Previously Standard Pad with Optimum ContactOptimum Load Board Pad and Contact
Insertion Loss (S21) of Enhanced Pad Series Contact WithPrevious Standard Pad and Optimum Load Board Pad
-1 dB point @ 20+ GHzAll data modeled in HFSS
20
Conclusion Modeling trends can determine how to
improve load board layout
Load board layout can greatly affect test data
Good microwave design principles apply toload board design
Modeling and test data have shown thatsignificant improvement can be attained bybetter matching load board and contactorimpedance to the Device Under Test (DUT)
Ball Series contributions from QuakeTechnologies indicated with the Quake logo
The New YieldPro Array Series Contactor
Patent USP# 6,299,459
Julius Botka, Master [email protected]
Julius BotkaBITS.ppt 10/31/01 Page 2
Brief History• Semiconductor manufacturers and
test houses are required to testdevices with multiple functions
• Packages vary in type, size and pitch• Contactors provide the final crucial
link to testers• First YieldPro contactor patented in
1997• Lowest parasitics with
independently compliant wiping contacts
• Path length is 0.037”,performance up to 18GHz Simple
SOIC-8Housing
Frame andSlider
mounted onelastomer
Frame withslider
inserted
Julius BotkaBITS.ppt 10/31/01 Page 3
Original YieldPro Contactor for LeadedComponents
Patent USP# 5,609,489
Julius BotkaBITS.ppt 10/31/01 Page 4
Today’s evolution of thebusiness:• Size and pitch keep getting smaller, number of
contacts increasing• Move from leaded to leadless BGA/LCC packages (Ball
Grid Array and Leadless Chip Carrier)
Leaded YieldPro Contactor YieldPro Array ContactorUSP#6,299,459
Julius BotkaBITS.ppt 10/31/01 Page 5
The New YieldPro Array Contactor• A new solution is needed for
contacting new chip scalepackages, such as BGA andLCC
• Agilent’s new YieldPro Arraydesign addressestechnologies, Bluetooth®,Wireless LAN and highspeed digital components
• All are heading towardhigher frequencies andrequire good performance inhigh speed digital, and at the3rd harmonic of the RFfundamental
Patent USP# 6,299,459
Julius BotkaBITS.ppt 10/31/01 Page 6
Problem:Lack of reliable/repeatable contact between tester andcomponent to be tested
• Two parallel contactpaths from solderball/contact pad to DUTboard
• Contacts do not wear theDUT board
Solution:Slider
Design Considerations
Julius BotkaBITS.ppt 10/31/01 Page 7
Problem:
Unwanted and unmanageable inductive or capacitanceparasiticsSolution:
CSPSLIDER
BGASLIDER
• Parasitic inductanceand capacitance arereduced bycontrollingimpedance to becloser to 50ΩΩΩΩ
• Parasitics are furtherreduced byminimizing height ofthe contactor
• If increasedimpedance isrequired, adjacentground contacts canbe removed
Julius BotkaBITS.ppt 10/31/01 Page 8
Problem:Excessive andundefined contactresistance sensitive tocontaminants
• Resistance is lowered byhaving two parallelcontact paths
• The slider can follow theball, always maintainingtwo contacts to pad orthe sides of the ball
Solution:
Contact at onepoint/line only or
through the spring
Top View
BreakawaySide View
*Initial Agilent Design
Consideration
Julius BotkaBITS.ppt 10/31/01 Page 9
Problem:No wiping contact to ball/pad
• Slider wipes the sides ofthe ball, while barbspierce through the oxidelayer without gougingeither the ball or the pad
• CSP Head contacts flexand wipe contact padtoward each other
Solution:
Flexibleheads
providewipingaction
Slider wipes thesides of the ball,barbs pierce the
oxide layer
Julius BotkaBITS.ppt 10/31/01 Page 10
Problem:Damage to the bottom of the solder ball/pad due todirect hit and excessive pressure from contact
• No sharp pointsassociated with the topof the contact.Therefore, no gougingor re-shaping canoccur. The ball/pad isnot damaged by theYieldPro Arraycontactor.
Solution:
Julius BotkaBITS.ppt 10/31/01 Page 11
Large gapsin betweencontacts
Problem:Given there is always contamination in a test operation,it becomes very difficult to clean the contactor due tonarrow open spaces on the top surface wherecontamination can lodge
Solution:• Housing designed for easy
removal of contaminatesusing low pressurecompressed air
• Complete contactor can bethoroughly cleanedultrasonically
Julius BotkaBITS.ppt 10/31/01 Page 12
Problem:After 100,000 plunges, excessive wear requires costly andfrustrating contactor component maintenance or replacement
Solution:
• New designsupportsoperation withoutreplacement ofparts throughhundreds ofthousands ofcycles
Slider TorlonHousing
Solder ball on bottom ofDUT (Device under Test)
One of two wipe andpierce contacts to ball
One of twowipingcontactinteractionsof frame andslider
Frame One of two contactlines to PC Boardpad
Elastomer LCC Contact
Julius BotkaBITS.ppt 10/31/01 Page 13
Problem:Life of some contactors is limited to a few tens ofthousands plunges, offsetting the initial lower price
• Typical life of a newYieldPro Arraycontactor is well overa million cycles
• Contacts can beeasily replaced onsite
Solution:
Julius BotkaBITS.ppt 10/31/01 Page 14
Problem:Plating will wear away, oxidation may occur
• Metal contactcomponents of theYieldPro Arraycontactors are madeof solid precious andsemi-precious metals
• No increase in contactresistance with wear
Solution:
Julius BotkaBITS.ppt 10/31/01 Page 15
Problem:Part handler alignment is difficult.Solution:
• Sliders shown in fully compressedposition
BGA SLIDERCSPSLIDER
• Generous individualindependent contactcompliance, up to0.011”
• With the contactorattached to the DUTboard, there is noforce between thebottom of thehousing and theDUT board. Thiseliminates housingdistortion over time
Julius BotkaBITS.ppt 10/31/01 Page 16
Problem:Usability issues revolvingaround scaled down versions oflarge designs, first developedfor lower frequency applications
Solution:
• The YieldPro Array designconcept is not subject toproblems associated withscaled down designs
• Performs at high RF andmicrowave frequencies indemanding applications
Scaled down springuncoils with use, and cansplit the housing sleeveretaining contaminantsand losing compliance
Initial Agilent designconsideration
Julius BotkaBITS.ppt 10/31/01 Page 17
Fixture for Contactor EvaluationThe two opposingcoplanar waveguide linesoverlap for the length ofthe contacts
0.275” wide and 0.010”thick alumina coplanarwaveguide line with0.015” air gap under themid 0.230” of width
FR4 supportboard
Julius BotkaBITS.ppt 10/31/01 Page 18
Coplanar waveguide substrate with gated short at contactor plane.Measurement yields 2 x loss and dispersion. (Shift phase 180° before saving)
FrequencyDomaindata
TimeDomaindata Gate
Markers
Julius BotkaBITS.ppt 10/31/01 Page 19
Fixture S-parameters measured
MARKER 13 GHz
MARKER 26 GHz
MARKER 312 GHz
Julius BotkaBITS.ppt 10/31/01 Page 20
Fixture time domain is computed from S-ParametersHousing and contacts gated
GateMarkers
Julius BotkaBITS.ppt 10/31/01 Page 21
S-Parameter of fixture with gates “on”
MARKER 13 GHz
MARKER 26 GHz
MARKER 312 GHz
MARKER 3(Return Loss)
Julius BotkaBITS.ppt 10/31/01 Page 22
S11 Gated, coplanar substrate electrical length isremoved with port extension, no loss or dispersioncorrection
m1freq=1.000GHzS(1,1)=0.041 / -102.526impedance = Z0 * (0.979 - j0.079)
m2freq=3.090GHzS(1,1)=0.110 / -115.386impedance = Z0 * (0.893 - j0.180)
m3freq=11.67GHzS(1,1)=0.073 / -166.014impedance = Z0 * (0.868 - j0.031)
freq (1.000GHz to 12.00GHz)
S(1,
1)
m1
m2
m3
Scale = 0.25
Port Extension = 348 ps, 104.33 mm, 125.196 degrees
Julius BotkaBITS.ppt 10/31/01 Page 23
m1freq=1.000GHzData_minus_loss=0.044 / -98.862impedance = Z0 * (0.983 - j0.085)m2freq=3.090GHzData_minus_loss=0.121 / -104.742impedance = Z0 * (0.916 - j0.217)m3freq=11.78GHzData_minus_loss=0.087 / -124.213impedance = Z0 * (0.898 - j0.130)
freq (1.000GHz to 12.00GHz)
Dat
a_m
inus
_los
s
m1
m2
m3
Scale = 0.25
S11 gated of contacts and housing with 2x loss anddispersion removed by vectorially dividing measuredand gated S11 bystored data from Page 18, thereby correcting for lossand dispersion
Use this data togenerate model
Julius BotkaBITS.ppt 10/31/01 Page 24
CSP 0.5 mm
TLINTL2
F=1 GHzE=2.2 noopt 1.4 to 2 Z=34.5 Ohm opt 32 Ohm to 36 Ohm
OptimOptim1
Use AllGoa ls=ye sUse AllOptVa rs=ye sSa ve AllIte ra tions=noUpda teDa ta se t=ye sSa ve OptimVa rs=noSa ve Goa ls=ye sSa ve Solns=ye sSe e d= Se tBe stVa lue s=ye sSta tusLe ve l=4De s iredError=0.0P=2Ma xIte rs=25ErrorForm=L2OptimType =Gra die nt
OP TIM
TLINTL3
F=1 GHzE=-9.18889 opt -13 to -7.5 Z=50.0 Ohm
TLINTL5
F=1 GHzE=9.38041 opt 8 to 11 Z=43.0871 Ohm opt 40 Ohm to 50 Ohm
TLINTL4
F=1 GHzE=7.11405 opt 6 to 13 Z=48.5497 Ohm opt 40 Ohm to 50 Ohm
Goa lOptimGoa l1
Ra nge Max[1]=Ra nge Min[1]=Ra nge Var[1]=We ight=Ma x=.000001Min=SimIns ta nce Na me ="SP1"Expr="mag(Da ta _minus_loss -S55)"
GOAL
Te rmTe rm6
Z=50 OhmNum=6
Te rmTe rm5
Z=50 OhmNum=5
Model of Contacts with Effects of Housing Overlay
TL3: Its negative electrical lengthresets the phase to zero fromthe contacts to the edge ofhousing.
TL4 and TL5: Represent lowerimpedance of coplanarwaveguide lines underhousing to contacts.
TL2: Is the transmission linerepresenting the contacts,one signal and two groundson either side
Julius BotkaBITS.ppt 10/31/01 Page 25
Data to 1 GHz and above 12 GHz is discarded due to expected inaccuracies of time domain conversion.Good agreement is shown over 3.5 octaves. Evidence of a “good” model!
Measured S11 of gated housing and contactsand computed S11 (S55) from model is shown.
Scale = 0.2
freq (1.000GHz to 12.00GHz)
S(5,
5)D
ata_
min
us_l
oss
2 4 6 8 100 12
-26
-24
-22
-20
-18
-16
-28
-14
freq, GHzdB
(S(5
,5))
dB(D
ata_
min
us_l
oss)
CSP 0.5mm
Measured Data Model
Julius BotkaBITS.ppt 10/31/01 Page 26
S11 of contact region from model
2 4 6 8 10 12 14 160 18
-35
-30
-25
-20
-15
-40
-10
freq, GHz
dB S
11
Scale = 0.25
Z1 = 34.5 OhmsElec trical Length @ 10 GHz = 22 degreesC (distributed over the contact length) = 0.177 pFL (distributed over the contact length) = 0.211 nHMax Current = 1A
CSP 0.5 mm Contactor
freq (1.000GHz to 18.00GHz)
S11
Use this data toset specs with
guardband
Julius BotkaBITS.ppt 10/31/01 Page 27
Best DUT Board Practices at High Frequencies
• Coplanar waveguide to contactor is best transmissiontype, use on top surface of the board above 6 GHz
• In microstrip, minimize lengths of vias to pads undercontactor
• Use blind vias, not to have the signal via extend downto or through the ground plane
• Control impedance between pads under contactor• Compensate signal path extending below contactor
housing, to achieve desired impedance/compensationfor best contactor match
Julius BotkaBITS.ppt 10/31/01 Page 28
*
Accounting for housing effects
*
• This transmission line represents a reduced impedance segment of theZo transmission line due to the overlay of the housing from the edge tothe contacts
• A reduction from 50 Ohms to ~ 40 Ohms was seen due to the overlay ofthe housing on a coplanar waveguide transmission line on the top layerof the DUT board; Less reduction is expected for microstrip lines
• The effect of the housing overlay can be mitigated by accounting for thehigher effective overall permitivity under the housing material
• Adjusting the dimensions of the transmission line accordingly canmaintain Zo to the contacts
• This same region’s impedance Z2 can be adjusted to values other thanZo to transform/improve the contact’s specified impedance over thedesired frequency range
Julius BotkaBITS.ppt 10/31/01 Page 29
Con
tact
Pr
essu
re
Con
tact
Wid
th
Rec
omm
ende
d B
all S
izes
Rec
omm
ende
d Si
ze P
ad M
in.
Con
tact
C
ompl
ianc
e
DC
Res
ista
nce
Leak
age
Impe
danc
e
Zo
Elec
tric
al
Leng
thM
ax. C
urre
nt
Car
ryin
g C
apac
ity
Cap
acita
nce
Indu
ctan
ce
Phys
ical
Le
ngth
Effe
ctiv
e D
iele
ctric
C
onst
ant,
Contactor Type & Pitch
3 GHz 10 GHz 18GHz
Alo
ng th
e Le
ngth
of
Con
tact
s
@ 1
0 G
Hz
in D
egre
es
Cen
ter
Con
tact
to
Gro
und
Note 1 Note 2 Note 4 Note 6
YieldPro 1.25 mm 40 gr 0.020" 0.007" <40m Ohm <I nA >21 dB >12 dB >8 dB 26.3 Ohm 18 3 A 0.190 pF 0.131 nH 0.927 mm / 0.0365" 2.65Note 7 70 gr max
YieldPro 0.8 mm 25 gr, 0.015" 0.007" <40m Ohm <I nA >18.5 dB >9.5 dB >5.9 dB 22 Ohm 18 2 A 0.227 pF 0.11 nH 0.927 mm / 0.0365" 2.65Note 7 40 gr max
YieldPro 0.5mm 20 gr, 0.010" 0.007" <40m Ohm <I nA >16.25 dB >7.25 dB >4.5 dB 17.6 Ohm 18 1 A 0.284 pF 0.088 nH 0.927 mm / 0.0365" 2.65Note7 28 gr max
YieldPro 0.4mm 15 gr, 0.007" 0.007" <40m Ohm <I nA >18.45 dB >9.45 dB >6.15 dB 21 Ohm 18 0.75 A 0.238 pF 0.105 nH 0.927 mm / 0.0365" 2.6520 gr max
For CSP: BGA/LGA PackagesYieldPro Ultra 30 gr, 0.6-0.762 0.5 x 0.5 0.011" <40m Ohm <I nA >27.5 dB >17.8 dB >14 dB 38.5 Ohm 22 2 A 0.159 pF 0.235 nH 1.438 mm / 0.0566" 1.65BGA/LGA 1.0mm 50 gr max mm mm
YieldPro Ultra 25 gr, 0.48-0.54 0.35x0.35 0.011" <40m Ohm <I nA >20.75 dB >11.5 dB >8 dB 28.6 Ohm 22 2 A 0.213 pF 0.175 nH 1.438 mm / 0.0566" 1.65BGA/LGA 0.8mm 40 gr max mm mm
YieldPro Ultra 20 gr, 0.3-0.42 0.2 x 0.2 0.007" <40m Ohm <I nA > 24.5 dB >15 dB >11.2 dB 34.5 Ohm 22 1 A 0.177 pF 0.211 nH 1.438 mm / 0.0566" 1.65BGA/LGA 0.5mm 28 gr max mm mm
Note 1: Resistance measured on a clean contactor. Note 5: Capacitance and Inductance are distributed over the contact length.Note 2: Leakage current measured w ith 10V applied to signal contact. Note 6: Physical length is show n fully compressed.Note 3: Assumes 50 Ohm environment. Note 7: Agilent YieldPro contactors for leaded/LCC packages support: SOT, SOIC, SSOP, Note 4: Apply current only after making contact. TSSOP, MSOP, QFN, TQFP, MLF, and MLP device package requirements.
For leaded packages/LCC
Values in this table pertain to center contact with ground contacts on two sides
Return Loss
Note 3 Note 5
εε εε eef
Julius BotkaBITS.ppt 10/31/01 Page 30
Economic Benefits:• Increase the yield by not
rejecting good parts. Smallerguard bands can be usedbecause of less uncertainty inthe measurement
• Contacts are made of preciousmetal and will not oxidize.Good performance ismaintained due to lack ofcorrosion
• The longer life of the contactorreduces cost per parts tested
Electrical and MechanicalPerformance
Characterization of HighFrequency Test SocketsAuthors: Dr. Hanyi Ding
and Lisa Steckley,IBM Microelectronics
Presented by: Lisa Steckley
March 3-6, 2002 BiTS Workshop 2
Introduction
This presentation summarizes the ongoingwork at IBM to understand the factorsaffecting both the electrical performance andmechanical durability of several commercialRF test sockets.
March 3-6, 2002 BiTS Workshop 3
Objective
Purchase from a single source to reduceCOST
Choose best socket for specific application;PERFORMANCE
Deliver ROBUST manufacturing solution
March 3-6, 2002 BiTS Workshop 4
Socket Requirements for Testing RFModules
High frequency – to 12 GHz Low inductance Repeatability High manufacturing precision – fine pitch High volume test – ease of maintenance Heat dissipation
March 3-6, 2002 BiTS Workshop 5
Socket Qualification Process
Determinepackage
Collect multiple socketcontactor technologies
Test socketsmechanically
Test electricalcontinuity
Perform RFanalyses
Compare withelectrical
simulations
March 3-6, 2002 BiTS Workshop 6
Qualification Process:Determine package
Leadless Plastic Chip Carrier (LPCC) 20lead-tin leads, 4x4mm, 0.5mm pitch, exposedpaddle ground
March 3-6, 2002 BiTS Workshop 7
Qualification Process:Contactor technologies studied
Pogo-style Spring loaded, gold plated, BeCu pogo, torlon housing
S-geometry Gold plated, BeCu contact, torlon and elastomer housing
Low-profile interconnect Conductive interconnect simulating plunge-to-board, torlon
housing Conductive elastomer
Gold plated contact set plus conductive elastomer, torlonhousing
March 3-6, 2002 BiTS Workshop 8
Qualification Process:Test Sockets Mechanically
Build packages with shorted die Build board for continuity test Inspect packages, contacts, and board Cycle packages through handler, testing for
DC contact Re-inspect for contact and board wear
March 3-6, 2002 BiTS Workshop 9
Mechanical Analysis:Pogo-style socket before test
March 3-6, 2002 BiTS Workshop 10
Mechanical Analysis:Pogo-style socket after test
(picture after 5000, 10000 parts cycled)
Lead-tin from package collects on gold pogo
Inexpensive maintenance
Further testing required to determinecleaning frequency
March 3-6, 2002 BiTS Workshop 11
Mechanical Analysis:S-contact socket before test
March 3-6, 2002 BiTS Workshop 12
Mechanical Analysis:S-contact socket after test
(picture after 5000, 10000 parts cycled)
Lead-tin debris on elastomer; potential forshorting
Little to no damage on contacts
Inexpensive maintenance
Further testing required to determinecleaning frequency
March 3-6, 2002 BiTS Workshop 13
Mechanical Analysis:Low-profile interconnect socket before test
March 3-6, 2002 BiTS Workshop 14
Mechanical Analysis:Low-profile interconnect socket after test
(picture after 5000, 10000 parts cycled)
Lead-tin debris visible
Contact scrubbing points show little wear
Expensive maintenance; further testing todetermine mechanical life
Further testing required to determinecleaning frequency
March 3-6, 2002 BiTS Workshop 15
Mechanical Analysis:Conductive elastomer socket before test
March 3-6, 2002 BiTS Workshop 16
Mechanical Analysis:Conductive elastomer socket after test
(picture after 5000, 10000 parts cycled)
Lead-tin collects on gold contact set
Expensive maintenance; further testing todetermine mechanical life
Further testing required to determinecleaning frequency
March 3-6, 2002 BiTS Workshop 17
Mechanical Analysis:Board wear after test Pogo-style socket
Little wear on board; consistent witness marks
S-contact socket Evident wear from wiping action
Low-profile interconnect socket Visible wear on board; can be improved by usingelastomer added for compliance
Conductive elastomer socket Little wear on board
March 3-6, 2002 BiTS Workshop 18
Qualification Process:Test socket continuity
Yield using pogo socket:
March 3-6, 2002 BiTS Workshop 19
Qualification Process:Test socket continuity
Yield using s-contact socket:
March 3-6, 2002 BiTS Workshop 20
Qualification Process:Test socket continuity
Yield using low-profile interconnect socket:
March 3-6, 2002 BiTS Workshop 21
Qualification Process:Test socket continuity
Yield using conductive elastomer socket:
March 3-6, 2002 BiTS Workshop 22
Electrical Performance Simulations
Socket companies typically providecharacterization reports based on a verysimple equivalent circuit.
Our goal is to verify the performanceparameters they claim using:Momentum, a 2.5D electromagnetic simulatorAnsoft HFSS, a 3D modeler and simulator
March 3-6, 2002 BiTS Workshop 23
Electrical Performance Simulations
Equivalent circuit for socket pins
March 3-6, 2002 BiTS Workshop 24
Electrical Performance Simulations
Structure setup for pogo pin type socket modeling using Momentum
March 3-6, 2002 BiTS Workshop 25
Electrical Performance Simulations
Structure setup for pogo pin type socket modeling using HFSS
March 3-6, 2002 BiTS Workshop 26
Recognition of Support
John Blondin – IBM, Front-End-Hardware Ronald Clarke – IBM, Test Applications Eng. Dr. Hanyi Ding – IBM, RF Board Design John Ferrario – IBM, Manager RF Test
Development Gene Patrick – IBM, Front-End Hardware Kevin Potasiewicz – IBM, RF Test Engineer Randy Wolf – IBM, RF Board Design