built-in logic block observer - organization zarchitecture
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C. Stroud 10/06 BILBO 1
BuiltBuilt--In Logic Block Observer In Logic Block Observer -- OrganizationOrganization
ArchitectureArchitectureOperationOperationTest Session SchedulingTest Session SchedulingBIST ControllerBIST ControllerConcurrent BILBOConcurrent BILBOBenefits & LimitationsBenefits & Limitations
C. Stroud 10/06 BILBO 2
BuiltBuilt--In Logic Block Observer (BILBO)In Logic Block Observer (BILBO)by by KoenemannKoenemann & & MuchaMucha, 1979, 1979
1st BIST approach proposed1st BIST approach proposedBIST logic added to all BIST logic added to all FFsFFs
plus logic for characteristic polynomialplus logic for characteristic polynomialBILBO control leads B1 & B2 facilitateBILBO control leads B1 & B2 facilitate
system mode system mode -- normal operationnormal operationreset mode reset mode -- initializationinitializationLFSR mode LFSR mode -- TPGTPGMISR mode MISR mode –– ORAORA
Scan mode neededScan mode neededBIST results retrievalBIST results retrievalInitialization of Initialization of TPGsTPGs
to nonto non--0 values0 valuesTestTest--perper--clock BISTclock BIST
Exhaustive testing of combinational logicExhaustive testing of combinational logic
Zi
B1B2
Qi-1
D Q
CK Q
Qi
Qi
CombLogicaddedto FF
BILBO FF
BILBO
BILBO
CombLogic
Z
B1B2
Q
C. Stroud 10/06 BILBO 3
BILBO EvolutionBILBO EvolutionOriginal implementationOriginal implementation
Required mode pin B1 Required mode pin B1 to control TPG vs. to control TPG vs. MISR mode during MISR mode during testingtesting
Forcing logic 0s on Z Forcing logic 0s on Z inputs causes MISR to inputs causes MISR to function as LSFR for function as LSFR for TPGTPG
Used external FB LFSRUsed external FB LFSRLater implementation added Later implementation added control signal B3control signal B3
To control TPG vs. To control TPG vs. MISR modesMISR modes
C. Stroud 10/06 BILBO 4
BILBO EvolutionBILBO EvolutionModified BILBO was Modified BILBO was introduced for practical introduced for practical ASIC implementationsASIC implementations
NAND gates used NAND gates used for CMOS for CMOS ““friendlyfriendly””standard cellsstandard cellsOnly two control Only two control signals neededsignals neededMinimizes area Minimizes area overheadoverheadMost frequently used Most frequently used BILBO approachBILBO approach
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BILBO OperationBILBO OperationAt least 2 test sessions requiredAt least 2 test sessions required
Test session 1:Test session 1:CktsCkts A & C are CUTsA & C are CUTsBILBO 1 = MISRBILBO 1 = MISRBILBO 2 = LFSRBILBO 2 = LFSR
Test session 2:Test session 2:CktCkt B is CUTB is CUTBILBO 1 = LFSRBILBO 1 = LFSRBILBO 2 = MISRBILBO 2 = MISR
Need scan mode toNeed scan mode toRetrieve BIST results from Retrieve BIST results from MISRsMISRsInitialize Initialize LFSRsLFSRs to nonto non--0 values0 values
Works well for pipelined architecturesWorks well for pipelined architecturesOtherwise, problems with feedbackOtherwise, problems with feedback
Requires test session schedulingRequires test session scheduling
CUT A
CUT B
CUT C
LFSR
MISR
BILBO 1
BILBO 2
TestSession
1
MISR
LFSR
TestSession
2
LFSR
MISR
Scan In
Scan Out
C. Stroud 10/06 BILBO 6
Test Session SchedulingTest Session SchedulingPractical application Practical application of BILBO typically of BILBO typically requires scheduling requires scheduling of multiple test of multiple test sessions based on sessions based on interconnection of interconnection of registers and registers and combinational logiccombinational logic
C. Stroud 10/06 BILBO 7
Register SelfRegister Self--AdjacencyAdjacencyCommon in Common in FSMsFSMs
Next state is function of current stateNext state is function of current stateBILBO must simultaneously function as TPG and ORABILBO must simultaneously function as TPG and ORA
Signatures act as test vectorsSignatures act as test vectorsLoose pseudoLoose pseudo--exhaustive nature of test vectorsexhaustive nature of test vectors
One solution One solution –– the Concurrent BILBO (CBILBO)the Concurrent BILBO (CBILBO)Doubles #Doubles #FFsFFs to create independent TPG and ORAto create independent TPG and ORA
Register R1
Register R2
CombinationalLogic
system operation
R1=TPG(LFSR)
R2=ORA(MISR)
CombinationalLogic
BILBO operation CBILBO operation
R1=TPG(LFSR)
R2=ORA
CombinationalLogic
R2=TPG
C. Stroud 10/06 BILBO 8
Concurrent BILBOConcurrent BILBOAdds additional register to allow TPG and MISR to operate Adds additional register to allow TPG and MISR to operate independently in cases of register selfindependently in cases of register self--adjacencyadjacency
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BILBO SummaryBILBO SummaryNot practical but historically significant since it got BIST staNot practical but historically significant since it got BIST startedrted
Led to pseudoLed to pseudo--exhaustiveexhaustive selfself--test (PEST)test (PEST)Led to Circular BISTLed to Circular BIST
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BILBO SummaryBILBO SummaryAdvantagesAdvantages
TestTest--perper--clock clock archtecturearchtecturePseudoPseudo--exhaustive testingexhaustive testing
No need for fault simulationNo need for fault simulationWorks well for pipelined applicationsWorks well for pipelined applications
DisadvantagesDisadvantagesDifficult to implement in practical applicationsDifficult to implement in practical applications
Multiple test sessions requireMultiple test sessions requireTest session scheduling can be difficultTest session scheduling can be difficult
Requires multiple primitive polynomials of varying degreesRequires multiple primitive polynomials of varying degreesRegister selfRegister self--adjacency difficult to overcomeadjacency difficult to overcome
Higher area overhead than other BIST approachesHigher area overhead than other BIST approachesMore than two gate delays in every critical pathMore than two gate delays in every critical path