building a vlsi neuron - university of california, san...
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Building a VLSI Neuron
Brad Aimone, Stephen Larson and David Matthews
BGGN 260 ProjectWinter, 2006
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What is VLSI?
Very-Large-Scale Integrated• Generating large circuits on a single chip by
creating transistors• Transistors are created by impurity doping• Analog vs. Digital
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How VLSI works subthreshold
courtesy Gert Cauwenberghs
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Benefits of VLSI
• Efficient modeling (using single transistors rather than software) allows on-line updating of parameters during real-time modeling
• Inherent system noise • Involves biologically relevant constraints
– available space (limited wiring)– power is at a premium– computations must be reliable and robust
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Hodgkin-Huxley Model
Graph of HH-Neuron from Matlab
( ) ( ) ( )
( )
( )
( ) hhdtdh
nndtdn
mmdtdm
IVEgVEngVEhmgdtdVC
hh
nn
mm
DCLeakLeakKKNaNa
βα
βα
βα
+−=
+−=
+−=
+−+−+−=
1
1
1
43
…where α’s & β’s are functions of voltage
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HH-Simulated
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Goals in designing a HH Neuron
• For any given dynamical state {V,m,h,n}– System must calculate and apply instantaneous
dynamics to calculate state variables• dV/dt = f(V,m,h,n); • dm/dt=f(a(V),b(V),m); …
– Therefore, a(V), b(V)’s must be continuously calculated and fed into dm/dt, dn/dt, dh/dt
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Practical considerations
• Transmit information through circuit as voltages or currents?– Some math operations are easier in current, others easier in
voltage– Currents can be ‘mirrored’ and reversed easily– Voltage operations are often more precise
• In our system, most circuit subunits output information as current
• Key state – Vneuron – is a voltage
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Alpha/Beta Circuit
• Need to fit unique HH equations for α and β for m,h,n
• Input is Vneuron
• Circuit should be general
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Alpha/Beta Circuit
• Can fit with “Bump Circuit”
• Multiple “bumps” can be used to emulate α and βcurves– Each has different
Vreference and Ibias
Picture of Bump Circuit
Delbruck, 1991
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Alpha/Beta Circuit
• Bump circuit implemented
• 4 bumps used to form circuit
Simulations?
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Alpha/Beta Circuit
Simulations?
a_n
b_n
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Alpha/Beta Integrator
• Need to calculate dm/dt=B*m-A*(1-m)
• Input is a’s and b’s
• Output should be ‘m’,’h’, and ‘n’
Effect of a_n and b_n on dn/dt
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-85 -35 15
Voltage
a_n,
b_n
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
dn/d
t
a_n
b_n
dk/dt
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Alpha/Beta Integrator
• Need to calculate dm/dt=B*m-A*(1-m)
• Input is a’s and b’s
• Output should be current representing ‘m’,’h’, and ‘n’
Hynna & Boahen, 2006
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Alpha/Beta Integrator
• Need to calculate dm/dt=B*m-A*(1-m)
• Input is a’s and b’s
• Output should be current representing ‘m’,’h’, and ‘n’
Circuit diagram
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Alpha/Beta Integrator
Simulation
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Multiplier circuit
• Need to combine m’s, h’sand n’s into m3h and n4
n^4 vs n
00.10.20.30.40.50.60.70.80.9
1
-85 -35 15
Voltage
a_n,
b_n
, n
n
n^4
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Multiplier circuit
• Need to combine m’s, h’sand n’s into m3h and n4
• Can use translinear ‘floating gates’ to multiply currents
Minch BA et al., 2001
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Multiplier circuit
• Need to combine m’s, h’sand n’s into m3h and n4
• Can use translinear‘floating gates’ to multiply currents
• diode current charges to capacitors (relative weights are exponents) ‘Mirrored’ output current is a function of input currents and capacitive differences
Minch BA et al., 2001
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Multiplier circuit
Our Circuit
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Multiplier circuit
Results / Simulation
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Reversal Potential Scaling
• Current due to conductance and channel states (gNa*m3h and gK*n4) weighted by (ERev-V)
• Implemented by a “transconductanceamplifier”
Diagram of TCA
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One whole channel
n^4
IK
n
a
B
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K+ channel simulated
n^4
IK
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Na+ Channel
m
h
m^3*h
I_Na
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Whole Neuron
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Whole Neuron
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Results & Conclusions
• Designed and Implemented circuits to calculate– alphas and betas from voltage– m,h, and n from alphas and betas– multply m, h, and n’s; scale by conductances– reference currents to reversal potential and neuron
voltage– Combine INa, IK, and ILeak to simulate neuron
dynamics• Simulated and began to tune parameters to
accurately model HH behavior
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Future Directions
• Solve remaining dynamical problems• Optimize bump circuit approximations
– Generate more accurate a(v)’s and b(v)’s• Tune other parameters (gNa, gK, gLeak,
capacitors) to optimize HH behavior• Work on layout of circuit on chip
Special Thanks:Gert CauwenberghsJon Driscoll
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Optimization of Bumps