b.sc. thesis 1 - mems vibratory gyroscope and readout circuit
DESCRIPTION
Undergraduate Graduation Project Documentation - Faculty of Engineering, Ainshams University, Egypt.TRANSCRIPT
[I]
[I]
MEMS Vibratory Gyroscope
Graduation Project Thesis (1)
Faculty of Engineering - Ain Shams University
In Partial Fulfillment of the Requirements for the Degree
Bachelor of Science in Communication Systems Engineering
Submitted by
Abdel Rahman El-Naggar, Ahmed Magdy, Ahmed M. Hussien,
Amr Atef, Haidy El-Medany, Islam Ayoub, Shady Ashraf
Communication Systems Engineering
Credit Hours Engineering Programs (CHEP)
Fall 2012
Supervisors
Dr. Mohamed El-Sheikh
Dr. Maged Ghoneima
ECE Department
[II]
ABSTRACT The report presents our surveys and work about MEMS Vibratory Gyroscope Devices and
Systems as part of the graduation project, a brief outline for the thesis is shown below:
Chapter 1 is an introduction to MEMS technology, MEMS applications and gyroscopes. The
discussion is based on the early survey we did when we started the project.
Chapter 2 describes the back ground and theory of Coriolis effect gyroscopes; the physical
principle of operation, driving and sensing, mechanical and electrical design basics, and
fabrication technologies.
Owner: A. M. El-Sayed, A. M. Hussein, A. A. Hussein.
Chapter 3 discusses the Tuning Fork Gyroscope (TFG). The main features of TFG, design
concept, and the equation of motion. This chapter will contain also a hand analysis for a TFG
design and a verification of this design with a finite element analysis (FEA) using ANSYS.
Owner: A. A. Hussein.
Chapter 4 discusses another architecture which is the vibrating ring gyroscope (VRG). The
features of the architecture, the vibrating modes of the structure and some of the vibration
induced errors in the vibrating ring gyroscope. At the end of the chapter, a famous design done
by Dr. Najafi and Dr. Ayazi (A HARPSS Polysilicon VRG) is redesigned using another model, finite
element analysis (FEA) verified the design.
Owner: A. M. El-Sayed.
Chapter 5 explores the interfacing system and its main loops and types, also this chapter
contain an overview on previous work done regarding the interfacing system.
Owner: A. Y. El-Naggar, S. A. El-Sayed.
Chapter 6 in this chapter the system is divided into main blocks starting from the capacitive
interface, the analog to digital converting, then the demodulation, the drive loop automatic
control and the clock generation of the system.
Owner: A. Y. El-Naggar, A. M. Hussein , H. K. El-Medany, S. A. El-Sayed. I. A. Ayoub.
Chapter 7 briefly summarizes the thesis and shows our conclusions from this semester’s work.
Finally we explain the next semester plan (future work).
[III]
Table of Contents
1. INTRODUCTION ................................................................................................................... 1
1.1. MEMS Technology............................................................................................................................... 1
1.1.1. MEMS Applications ...................................................................................................................... 1
1.2. Gyroscopes.......................................................................................................................................... 1
2. BACKGROUND AND THEORY ............................................................................................ 3
2.1. Coriolis Force....................................................................................................................................... 3
2.2. Vibrating Two Modes Gyroscope ........................................................................................................ 3
2.2.1. Drive Mode Operation ................................................................................................................. 4
2.2.2. Sense Mode Operation ................................................................................................................ 4
2.3. Mechanical Design of MEMS Gyroscopes ............................................................................................ 5
2.3.1. Flexure Elements ......................................................................................................................... 5
2.3.2. Mode Coupling ............................................................................................................................ 9
2.4. Electrical Design of MEMS Gyroscopes .............................................................................................. 10
2.4.1. Capacitive Detection .................................................................................................................. 10
2.4.2. Electrostatic Actuation............................................................................................................... 12
2.5. Fabrication Technologies ................................................................................................................... 14
2.5.1. Microfabrication Techniques ..................................................................................................... 14
2.5.2. Bulk-Micromachining Processes ................................................................................................. 15
2.5.3. Surface-Micromachining Processes ............................................................................................ 16
2.5.4. SOI-MUMPs ............................................................................................................................... 16
3. TUNING FORK GYROSCOPE ............................................................................................ 21
3.1. Features of Tuning Fork Architecture ................................................................................................ 21
3.2. Design Concept ................................................................................................................................. 21
3.3. Equations of Motion.......................................................................................................................... 22
3.3.1. Drive-Mode Actuation ............................................................................................................... 24
3.3.2. Sense-Mode Detection: ............................................................................................................. 24
3.4. Mechanical Design ............................................................................................................................ 25
3.5. Finite Element Simulation ................................................................................................................. 25
3.6. Summary of Tuning Fork Gyroscope .................................................................................................. 26
3.6.1. Advantages of Tuning Fork Gyroscope ....................................................................................... 26
3.6.2. Disadvantage of Tuning Fork Gyroscope..................................................................................... 26
4. VIBRATING RING GYROSCOPE ...................................................................................... 27
[IV]
4.1. Vibration Modes of the Ring Structure .............................................................................................. 27
4.1.1. Normal Mode Model ................................................................................................................. 27
4.1.2. Mode Shapes............................................................................................................................. 27
4.1.3. Equations of Motion .................................................................................................................. 29
4.2. Vibration Induced Errors in Ring Gyroscopes ..................................................................................... 31
4.2.1. Vibration Induced Errors due to Non Proportional Damping ....................................................... 31
4.2.2. Vibration Induced Errors due to Non Linearity of Sense Electrodes ............................................. 32
4.3. A HARPSS Polysilicon Vibrating Ring Gyroscope ................................................................................ 32
4.3.1. Mechanical Design..................................................................................................................... 33
4.3.2. Finite Element Simulation .......................................................................................................... 34
4.3.3. Electrical Design ........................................................................................................................ 35
4.4. Evaluation of Vibrating Ring Gyroscope ............................................................................................ 36
4.4.1. Advantages of Ring Architecture ................................................................................................ 36
4.4.2. Disadvantages of Ring Architecture ............................................................................................ 36
5. INTERFACE ELECTRONICS ............................................................................................. 37
5.1. System Components ......................................................................................................................... 37
5.1.1. Drive loop .................................................................................................................................. 37
5.1.2. Sense loop ................................................................................................................................. 38
5.2. Overview of sense and drive electronics ........................................................................................... 38
6. BUILDING BLOCKS ........................................................................................................... 43
6.1. Capacitive interface........................................................................................................................... 43
6.1.1. Theory of Operation .................................................................................................................. 43
6.1.2. Capacitive sensing VS Resistive sensing ...................................................................................... 43
6.1.3. Main ruling Specs ...................................................................................................................... 45
6.1.4. Electronic Noise Sources ............................................................................................................ 45
6.1.5. Capacitive Sensing configurations .............................................................................................. 46
6.1.6. Comparison of Different Capacitive Sensing Architectures ......................................................... 52
6.2. Analog / Digital converter ................................................................................................................. 53
6.2.1. Introduction .............................................................................................................................. 53
6.2.2. General Specifications ............................................................................................................... 53
6.2.3. Analog to Digital converters ....................................................................................................... 58
6.2.4. Decimation Filters...................................................................................................................... 64
6.2.5. Digital to Analog Converters ...................................................................................................... 71
6.3. Demodulation block .......................................................................................................................... 76
6.3.1. Coherent detection ................................................................................................................... 76
6.4. Frequency synthesizer (PLL) .............................................................................................................. 85
6.4.1. Theory of PLL ............................................................................................................................. 85
6.4.2. Terminology of PLL .................................................................................................................... 88
6.4.3. Types of PLL............................................................................................................................... 88
[V]
6.4.4. Non Ideal Effects in PLL .............................................................................................................. 89
6.4.5. Applications of PLL..................................................................................................................... 90
6.4.6. Limitations of Simple PLL architecture........................................................................................ 91
6.4.7. Phase frequency detector .......................................................................................................... 92
6.4.8. The Charge Pump ...................................................................................................................... 93
6.4.9. Voltage Controlled Oscillator ................................................................................................... 100
6.4.10. Frequency divider .................................................................................................................... 101
6.4.11. Mixed PLL/DLL ......................................................................................................................... 102
6.5. Automatic Gain Control Loop (AGC) ................................................................................................ 105
6.5.1. Design 1 .................................................................................................................................. 106
6.5.2. Design 2 .................................................................................................................................. 111
6.5.3. AGC Sum up ............................................................................................................................ 112
6.6. Design Flow will be used ................................................................................................................. 113
6.6.1. Analog ..................................................................................................................................... 113
6.6.2. Digital ...................................................................................................................................... 114
7. CONCLUSION AND FUTURE WORK ............................................................................ 115
BIBLIOGRAPHY ....................................................................................................................... 116
APPENDICES ............................................................................................................................ 119
Appendix A – ANSYS Script to Calculate the Stiffness of a Fixed-Guided Straight Beam ............................... 119
Appendix B - ANSYS Script to Calculate the Stiffness of Fixed Guided Curved Beam .................................... 121
B.1 Horizontal and Vertical Stiffness ......................................................................................................... 121
B.2 45o Stiffness ....................................................................................................................................... 122
Appendix C - ANSYS Script for Modal Analysis of Tuning Fork Gyroscope .................................................... 123
Appendix D - Plotting Vibrations of the Ring Structure using SciLAB ............................................................ 125
Appendix E - ANSYS Script for Modal Analysis of Ring Gyroscope ................................................................ 126
Appendix F: Project Timeline ....................................................................................................................... 128
[1]
1. Introduction
1.1. MEMS Technology Micro-electromechanical systems (MEMS) technology is a process technology used to create
tiny integrated devices or systems that combine mechanical and electrical components. They
are fabricated using integrated circuit (IC) batch processing techniques and can range in size
from a few micrometers to millimeters. These devices (or systems) have the ability to sense,
control and actuate on the micro scale, and generate effects on the macro scale. While the device
electronics are fabricated using ‘computer chip’ IC technology, the micromechanical components
are fabricated by sophisticated manipulations of silicon and other substrates using
micromachining processes. Processes such as bulk and surface micromachining, selectively
remove parts of the silicon or add additional structural layers to form the mechanical and
electromechanical components.
MEMS technology has several distinct advantages as a manufacturing technology. First, the
interdisciplinary nature of MEMS technology and its micromachining techniques, as well as its
diversity of applications has resulted in an unprecedented range of devices and synergies across
previously unrelated fields (for example biology and microelectronics). Second, MEMS with its
batch fabrication techniques enables components and devices to be manufactured with
increased performance and reliability, combined with the obvious advantages of reduced
physical size, volume, weight and cost. These factors make MEMS potentially a far more
pervasive technology than integrated circuit microchips.
1.1.1. MEMS Applications
MEMS applications are diverse; the oldest application is pressure sensors [1]. The other major
sensor market is the inertial sensors. This market has been dominated by the automotive
industry, but recently the reduction in price has enabled adoption of MEMS inertial sensors
(accelerometers and gyroscopes) in consumer devices like digital cameras, mobile phones, and
Laptops.
For average consumers, the inkjet print heads may be the most familiar micro-device. Each
replacement inkjet cartridge has a micromachined inkjet nozzle head. The inkjet print heads are
frequently regarded as the largest MEMS market in terms of revenue. Texas Instruments holds
the key patents of the field of digital micro-displays (DMD). In projection displays, the high
contrast ratio of mechanically actuated mirrors enables the micro-mirrors to compete against
the common LCD technology.
Silicon microphones are the latest entry to the mass market. The growth is driven by cell phone
industry that is increasing rapidly. The microphones are an encouraging example of a MEMS
product that only a few years ago was deemed too expensive, but now gaining a market share
rapidly. [1]
1.2. Gyroscopes The word gyroscope was coined by the French scientist Leon Foucault and is derived from the
Greek words “Gyros” meaning rotation, and “Skopien” meaning to view. Simply, gyroscope is the
sensor that measures the rate of rotation of an object. It can be used for example for inertial
navigation, image stabilization, and automotive chassis control and rollover detection.
[2]
Historically, the angular rate has been measured with rotating
wheel gyroscope. The spinning wheel conserves the angular
momentum resisting the change in the rotation axis orientation.
The angular velocity can now be sensed by measuring the force
on the spinning wheel due to rotation [2].
Mechanical gyroscopes are comprised of a spinning wheel
mounted on two gimbals which allow rotation along all three
axes. Due to conservation of angular momentum, the spinning
wheel will resist change in orientation. Hence when a
mechanical gyroscope is subjected to a rotation, the wheel will
remain at a constant global orientation and the angles between
the adjacent gimbals will change. To measure the orientation of
the device, the angles between the adjacent gimbals is read
using angle pick-offs. It must be noted that a mechanical
gyroscope measures orientation directly. The disadvantage of mechanical gyroscopes is that
they comprise
of moving/spinning parts, which lead to friction. This eventually causes drift over time.
Optical gyroscopes encompass more recent technology. They are based on Sagnac effect which
states that a certain rate of rotation induces a small difference between the time it takes light to
traverse the ring in the two directions. These gyroscopes are not subject to a mechanical wear
and are the most precise ones [1]. Consequently, they are the most expensive gyroscopes, and
are used in aircraft navigation systems and missile guidance.
MEMS gyroscopes, fabricated using silicon micromachining technology, have low part counts
and are relatively cheap to manufacture in commercial quantities. They enable new applications
that are not possible with the classic optical or mechanical gyroscopes. Nearly all MEMS
gyroscopes are based on two orthogonal vibration modes. The drive-mode is orthogonal to the
sense-mode meaning that the two modes do not normally interact and the drive-mode
movement does not result in movement in sense-mode direction. The resonator is excited to
vibrate in the drive-mode in the x-direction. The Corilois force due to a rotation around z-axis,
excites the resonator sense-mode in y-direction. Thus, the sense-mode vibration amplitude is
proportional to the angular rotation rate. [2]
Figure 1-2 The Operation Principle of Vibrating Two Mode Gyroscope
Figure 1-1 One of the first examples of the gyrocompass
[3]
2. Background and Theory The underlying physical principle of vibratory gyroscopes is that a vibrating object tends to
continue vibrating in the same plane as its support rotates. This device is also known as a
Coriolis vibratory gyroscope because it is based on the principle of “Coriolis Effect”.
2.1. Coriolis Force The Coriolis force is the perpendicular deflection of a moving element that arises in connection
with rotation. Figure 2-1 illustrates how rotation affects the travel path of a freely moving object:
A particle is thrown from the center of a rotating wheel in the radial direction. If no forces acted
on the particle, it would have reached the point ‘B’. However, the wheel has rotated, so the
particle will not reach the point ‘B’, but a point ‘A’. [2]
Figure 2-1 Illusration of Coriolis Effect
The vector formula for the magnitude and direction of the Coriolis acceleration is [1]:
2-1
where is the acceleration of the particle in the rotating system (coriolis acceleration), is the
velocity of the particle in the rotating system, and is the angular velocity vector of the wheel
which has magnitude equal to the rotation rate ω and is directed along the axis of rotation of the
rotating reference frame, Thus, the coriolis force ( ) acting on a particle of mass is:
2-2
2.2. Vibrating Two Modes Gyroscope The basic architecture of a vibratory gyroscope is comprised of a drive-mode oscillator that
generates and maintains a constant linear or angular momentum, coupled to a sense-mode
Coriolis accelerometer that measures the sinusoidal Coriolis force induced due to the
combination of the drive vibration and an angular rate input. The vast majority of reported
micromachined rate gyroscopes utilize a vibratory proof mass suspended by flexible beams
above a substrate. The primary objective of the dynamical system is to form a vibratory drive
oscillator, coupled to an orthogonal sense accelerometer by the Coriolis force. The drive mode is
orthogonal to the sense mode means that the two modes don’t normally interact [2].
[4]
2.2.1. Drive Mode Operation
The Coriolis Effect is based on conservation of momentum; every gyroscopic system requires a
mechanical subsystem that generates momentum. In vibratory gyroscopes, the drive-mode
oscillator, which is comprised of a proof-mass driven into a harmonic oscillation, is the source of
momentum. The drive-mode oscillator is most commonly a 1 degree-of-freedom (1-DOF)
resonator, which can be modeled as a mass-spring-damper system consisting of the drive proof-
mass , the drive mode suspension system providing the drive stiffness , and the drive
damping consisting of viscous and thermoelastic damping. With a sinusoidal drive-mode
excitation force, the drive equation of motion along the x-axis becomes:
2-3
The scale factor of the gyroscope is directly proportional to the drive-mode oscillation
amplitude. Therefore, the drive mode is usually excited at resonance to obtain maximum
displacement with small driving force (lower actuation voltage).
It is extremely critical to maintain a drive-mode oscillation with stable amplitude, phase and
frequency. Self-resonance by the use of amplitude regulated positive feedback loop (Figure 2-2)
is a common and convenient method to achieve a stable drive-mode amplitude and phase. The
positive feedback loop destabilizes the resonator, and locks the operational frequency to the
drive-mode resonant frequency. An Automatic Gain Control (AGC) loop detects the oscillation
amplitude, compares it with a reference amplitude signal, and adjusts the gain of the positive
feedback to match the reference amplitude. Operating at resonance in the drive mode also
allows minimizing the excitation voltages during steady-state operation [2].
Figure 2-2 A typical implementation of an Automatic Gain Control (AGC) loop, which drives the drive-mode oscillator into self-resonance and regulates the oscillation amplitude.
2.2.2. Sense Mode Operation
The Coriolis response in the sense direction is best understood starting with the assumption that
the drive-mode is operated at drive resonant frequency , and the drive motion is amplitude
[5]
regulated to be of the form with a constant amplitude . The Coriolis force that
excites the sense-mode oscillator is:
2-4
where is the portion of the driven proof mass that contributes to the Coriolis force. Similar to
the drive-mode oscillator, the sense-mode oscillator is also often a 1-DOF resonator, the sense
mode equation of motion is:
2-5
Thus, the system’s equations of motion can be written in matrix form:
[
] [ ] [
] [ ] [
] * + [
] 2-6
We notice that the off diagonal elements on the matrices of damping [ ] and stiffness [ ] are
equal to zero, this means that no mode coupling happens except by the influence of the Coriolis
effect.
2.3. Mechanical Design of MEMS Gyroscopes
2.3.1. Flexure Elements
In linear micromachined gyroscopes, the suspension systems are usually designed to be
compliant along the desired motion direction, and stiff in other directions. Most suspension
systems utilize narrow beams as the primary flexure elements, aligning the narrow dimension of
the beam normal to the motion axis.
2.3.1.1. Fixed Guided Linear Beam
In purely translational modes, the boundary conditions of the beams that connect the
components of the gyroscopes are most commonly the fixed-guided end configuration (Figure
2-3), in which the moving end of the beam remains parallel to the fixed end. Many complete
gyroscope suspension systems can be modeled as a combination of fixed-guided end beams.
Figure 2-3 The fixed-guided end beam under translational deflection – (a) Beam Dimensions (b) Guided Boundary Condition
If we define the length of a beam (L) as the x-axis dimension, width (w) as the y-axis dimension,
and the thickness (t) as the z-axis dimension, the stiffness values of the fixed-guided beam along
the three principle axes become (assuming a linear case) [2]:
[6]
2-7
2-8
2-9
For example, for a fixed-guided beam with the dimensions L = 500μm, w = 4μm, and t = 25μm.
Assuming an elastic modulus of E = 150 GPa, the stiffness in the y direction is calculated from
equation 2.7 to be 1.92N/m. However this stiffness changes with the amount of deflection
practically due to the increase in reaction forces causing a nonlinear behavior by the beam.
The stiffness of the beam in the previous example was verified by Finite Element Analysis (FEA),
using a linear solution, and the deflection for a force of 10μN was about 5.208μm, therefore is
F/x approximately equals 1.92N/m. Performing nonlinear analysis, the stiffness reached
4.86N/m at a load of 10μN and deflection of 3.428μm as shown in Figure 2-4.
Figure 2-4 FEA Results - (a) Load - Deflection Plot (b) K - Displacement Plot
An ANSYS script for plotting the load-deflection graph is shown in appendix A.
2.3.1.2. Curved Beam
Curved (or semicircular) beams are widely used in vibrating ring gyroscopes (to be explained in
chapter 4. The stiffness of a curved beam is highly dependent on the direction of the applied
force. We will consider the 3 main stiffness in the horizontal, vertical, and 45o directions (KHA,
KVA, and K45) as shown in Figure 2-5.
0.00
1.00
2.00
3.00
4.00
5.00
6.00
0.00 5.00 10.00
Dis
pla
cem
ent
(μm
)
Load (μN)
Load-Deflection Plot
0.00
1.00
2.00
3.00
4.00
5.00
6.00
0.00 2.00 4.00 6.00
k (N
\m)
Y-Discplacement (μm)
K - displacement Plot
[7]
Figure 2-5 Stiffnesses of a semicircular spring in three directions
(a) Horizontal stiffness (KHA), (b) vertical stiffness (KVA), (c) stiffness along 45 direction (K45).
As proved in [3] the stiffness for a beam of radius , and moment of area
⁄ , in the three directions are given by:
(
)
2-10
(
)
2-11
(
) (
)
2-12
Where w is the width of the beam, t is the thickness of the structure.
For example, for semicircular beam with the radius r = 235μm, w = 4μm, and t = 80μm as in [4]
Assuming an elasticity modulus of E = 150 GPa, the stiffness in the horizontal direction is
calculated from equation 2.10 to be 16.573N/m, in vertical direction from equation 2.11 is
3.139N/m, and that in the 45o direction is 9.856N/m. However this stiffness also changes with
the amount of deflection practically, as in the case of straight fixed-guided beams, due to the
increase in reaction forces causing a nonlinear behavior by the beam.
The stiffness of the beam in the previous example was verified by FEA (Figure 2-6), using a
linear solution, the deflection for a force of 1mN was about 61.91μm in the horizontal direction,
thus the value of KHA was 16.15N/m. The deflection in the vertical direction at the same applied
force value was 452.59μm leading to KVA = 2.21N/m, and in 45o direction the deflection was
106.445 and the value of K45 was 9.40N/m.
[8]
(a)
(b)
[9]
(c)
Figure 2-6 FEA of curved beam - (a) Horizontal Deflection (b) Vertical Deflection (c) 45o Deflection
ANSYS scripts to generate the previous plots are found in appendix B.
2.3.2. Mode Coupling
There are two types of mode coupling in MEMS gyroscopes; the first is the desired one which
arises from Coriolis force, and the designer aims to magnify it, the second is an undesired one
which arises from non-idealities. In reality, fabrication imperfections result in non-ideal
geometries in the gyroscope structure, which in turn causes the drive oscillation to partially
couple into the sense-mode. Considering the relative magnitudes of the drive and sense
oscillations, even extremely small undesired coupling from the drive motion to the sense-mode
could completely mask the Coriolis response.
Equation 2.6 describes an ideal gyroscope, where the mode coupling happens only due to
Coriolis force, the practical equation of motion of a vibratory two modes gyroscope can be
written as:
[
] [ ] *
+ [ ] [
] * + [
] 2-13
Where and in the damping matrix represents the coefficients of the anisodamping forces
in y and x directions as a result of motion in y and x directions respectively. The terms and
in the stiffness matrix represents the anisoelasticity forces coefficients (suspension elements
in real implementations of vibratory gyroscopes have elastic cross-coupling between their
principal axes of elasticity). [2]
[10]
Since the oscillation amplitudes in the sense-mode are orders of magnitude smaller than the
drive-mode, the coupling due to and in the drive dynamics is negligible. The impact of
anisodamping and anisoelasticity is primarily on the sense-mode dynamics due to and ,
which couples the drive-mode displacement into the sense-mode accelerometer.
In Equation 2.13, we notice that there is always a 90o phase difference between the Coriolis
response ( ) and the mechanical quadrature ( ), therefore, the quadrature signal
can be separated from the Coriolis signal during amplitude demodulation at the drive frequency
(using coherent detection In which we multiply the sense signal by a carrier with same
frequency and phase). However, the ansiodamping component is in phase with the Coriolis
response, therefore it can’t be removed during demodulation, and it should be minimized in the
design of the gyroscope itself or by vacuum packaging of the device.
2.4. Electrical Design of MEMS Gyroscopes Micromachined gyroscopes are active devices, which require both actuation and detection
mechanisms. Various vibratory MEMS gyroscopes have been reported in the literature
employing a wide range of actuation and detection methods. For exciting the gyroscope drive
mode oscillator, the most common actuation methods are electrostatic, piezoelectric, magnetic
and thermal actuation. Most common Coriolis response detection techniques include capacitive,
piezoelectric, piezoresistive, optical, and magnetic detection.
In many MEMS applications, capacitive detection and electrostatic actuation are known to offer
several benefits compared to other sensing and actuation means, especially due their ease of
implementation. Capacitive methods do not require integration of a special material, which
makes them compatible with almost any fabrication process. They also provide good DC
response and noise performance, high sensitivity, low drift, and low temperature sensitivity
2.4.1. Capacitive Detection
Parallel-plate capacitors can be mechanized in several ways to detect deflection. For a generic
parallel-plate electrode plate with a gap d and overlap area Aoverlap , the capacitance is
2-14
Figure 2-7: Variable Gap Capacitor
where is the dielectric constant of the material between the plates. Each parameter in this
expression can be modulated by a deflection to result in a capacitance change. In variable gap
[11]
capacitors, the motion is normal to the plane of parallel plates, and the gap d changes with
deflection. In variable area capacitors, the motion is parallel to the plane, which results in a
change in Aoverlap. By placing a moving media between the parallel plates, the dielectric constant
can be modulated by deflection. The most common electrode types in inertial sensors are
variable gap and variable area capacitors, which are summarized below.
2.4.1.1. Variable Gap Detector
Variable-gap capacitors are the most widely used electrode type
for detection of small displacements. When the parallel plates are
oriented normal to the motion direction, deflections cause a
change in the gap .
It should be noticed that capacitance is a nonlinear function of
displacement in variable-gap capacitors. However, for very small
deflections relative to the initial gap, the capacitance change is
linearized. Denoting the displacement in the motion direction as
and assuming << , the capacitance change in a variable-gap
capacitor with an overlap area becomes:
2-15
Thus, small gap changes could result in high capacitance changes, providing very large
sensitivity.
2.4.1.2. Variable Area Detector
Variable area capacitors are ideal when the detected motion magnitudes are larger, especially
either when variable gap capacitors become significantly nonlinear, or deflections are larger
than a minimum gap. Since the overlap area is proportional to both dimensions in the plate
plane, capacitance change is purely linear with respect to motion parallel to the plates. Denoting
x as the displacement in the motion direction parallel to the plates, the capacitance change
becomes
2-16
Figure 2-9: Variable Area Detector
Table 2-1 shows a brief comparison between variable area and variable gap detectors
Figure 2-8 Variable Gap Detector
[12]
Table 2-1: Comparison between Detectors
Variable gap Capacitor Variable area capacitor The change in capacitance is a result of change in the gap d between the two plates.
The change in capacitance is a result of change in the overlap area between the two plates.
Higher sensitivity. Lower sensitivity. Non-linear for large displacement. The change in capacitance is linear.
From the above table, we can conclude that we can use variable gap capacitor if we don’t need a
large displacement and get a high sensitivity. However, we can use variable area capacitor for a
larger travelling distance in the expense of sensitivity.
2.4.2. Electrostatic Actuation
Electrostatic or capacitive actuation is based on the attraction of electric charges [2]. As the
device size is reduced to the micro-scale, this force become significant. The capacitive actuators
are easily fabricated and consume no DC power. There are two main types of capacitive
actuators; the closing gap actuator, and the variable area actuator. The variable area actuators
are much common in gyroscopes, because the electrostatic force varies linearly with the moved
distance. However, in some cases (like the vibrating ring gyroscope), the closing gap actuator is
used.
2.4.2.1. Closing Gap Actuator
Consider the closing gap actuator in Figure 2-10 Closing Gap Actuator, the electrostatic force of a
parallel plate capacitor (which is a good model for many MEMS actuators) is derived from the
energy stored, and is given by:
2-17
Where is the polarization voltage applied on the actuator, is the overlapping area between
the two electrodes, is the initial gap between the electrodes. The restoring force generated in
the spring of stiffness due to displacement is given by:
2-18
At equilibrium, neglecting the weight of the electrodes, the electrostatic force is
equal to the spring force which makes the voltage required to move a distance
equals:
√
2-19
Figure 2-10 Closing Gap Actuator
[13]
From Equation 2.14, we notice that the force is a nonlinear function with the displacement x,
which means that the electrostatic force increases rapidly as the two electrodes gets closer.
When the electrode moves a distance , the electrostatic force grows fast and the
movable electrode accelerates till it sticks with the fixed one, and the structure fails. This
condition is called: the pull-in condition, and the pull-in distance is considered the maximum
distance that the actuator can move, it’s proved in [1] that
, which means that the
closing gap actuator can only move one third of the gap between the electrodes. It
should be considered by the designers that the drive mode amplitude shouldn’t exceed
the pull-in distance. Figure 2-11 shows the electrostatic and spring forces of an actuator of
area = 150μm x 60μm, initial gap of 1.4μm at different polarization voltages.
Figure 2-11 Electrostatic Force and spring force of a closed gap actuator
2.4.2.2. Variable Area Actuators
Variable-area actuators aim to linearize the capacitance change versus displacement, in order to
achieve constant electrostatic force with respect to displacement. The inter digitated comb-drive
structure is based on generating the actuation force through a series of parallel plates sliding
parallel to each other, without changing the gap between the plates. The electrostatic force
generated in the x-direction for two parallel plates as in Figure 2-12 is
2-20
It should be noticed that this force is independent of displacement in the x-direction and the
overlap length of the capacitor plates, x0.
0
20
40
60
80
100
120
140
160
180
200
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Forc
e (μ
New
ton
)
displacement x (μm)
Electrosatic and Spring forces Vs displacement
Fspring
Fe(Vlow)
Fe(Vhigh)
Fe(Vpull-in)
pull-
in
[14]
Figure 2-12: Variable-area electrostatic actuator model.
Inter digitated comb-drives based on variable-area actuation are one of the most common
actuation structures used in MEMS devices. The primary advantages of comb-drives are long-
stroke actuation capability and the ability to apply displacement-independent forces, which
provide highly stable actuation.
In a comb-drive structure made of N fingers, each finger forms two parallel-plate pairs, and the
total electrostatic force generated in the x-direction becomes
2-21
Where z0 is the structure thickness and y0 is the distance between the fingers.
2.4.2.3. Balanced Actuation
In MEMS gyroscope, we always want to induce harmonic motion. Therefore, when a sinusoidal
net actuation force is desired, the drive force can be linearized with respect to the actuation
voltages by appropriate selection of voltages applied to the opposing electrode sets [2]. The net
electrostatic force generated by two opposing capacitors C1 and C2 is:
2-22
A balanced actuation scheme is a common method to linearize the force with respect to a
constant bias voltage and a time-varying voltage . The method is based on applying
to one actuator, and to the opposing actuator. Assuming two
electrodes are identical, and the DC voltage is much greater than the time varying component,
the net electrostatic force reduces to:
[
]
2-23
2.5. Fabrication Technologies
2.5.1. Microfabrication Techniques
Microfabrication describes processes of fabrication of miniature structures, of micrometer sizes
and smaller. Integrated Circuit (IC) fabrication is the earliest microfabrication processes used.
Inertial sensors require moving parts to detect inertial phenomena. Micromachining
technologies have revolutionized inertial sensing by allowing fabricating moving mechanical
systems at the micro scale. Originated from semiconductor fabrication techniques,
micromachining technologies have made it possible to merge micro-scale mechanical and
[15]
electrical components. The essence of all micromachining techniques is successive patterning of
thin structural layers on a substrate [2].
2.5.1.1. Deposition
The process flow of micromachining fabrication starts with a
blank wafer. The intention is to pattern a multiple structural
layer for moving structures, interconnect, electrode areas, or
dielectric layers for electrical isolation using successive
deposition and patterning of these layers.
Depending on the material, layer thickness, or conformal
coverage requirements, different deposition techniques may be
used such as Chemical Vapor Deposition (CVD), Physical Vapor
Deposition (PVD), or electroplating.
2.5.1.2. Photolithography
Photolithography, also known as lithography, is the process of
patterning parts of a thin film or the bulk of a substrate. Prior to
processing, a photolithography mask that carries the wafer-level
layout of a layer is generated. Then the image on the mask is
projected onto a photosensitive material deposited on the wafer, commonly known as
photoresist.
2.5.1.3. Etching
Etching transfers the pattern formed by photolithography into the actual structural materials
and defines the geometry of the device by selective material removal.
There are two primary categories of etching: wet etching and dry etching. As the name implies,
wet etching uses a liquid chemical solution. On the other hand, dry etching uses either a vapor
phase etchant or reactive ions. In MEMS, to determine the required etching method many factors
are involved such as the desired sidewall and bottom surface profiles, isotropy, or stiction
issues. [2]
2.5.2. Bulk-Micromachining Processes
Micromachining processes are usually divided, depending on the structural layer forming
technique, into two main categories: Surface micromachining and Bulk micromachining.
Traditionally, bulk micromachining implies the use of subtractive processes to pattern thick
structural layers. In most bulk micromachining process, two or more wafers are bonded, and the
moving structures are made out of the whole thickness of a silicon wafer.
Bulk micromachining offers many advantages for inertial micromachined devices, since it
provides thick structural layers. Larger device thickness increases the mass and overlap area of
capacitive electrodes, directly improving gyroscope performance. Thicker suspension beams
provide higher out-of-plane stiffness, which reduces shock and vibration susceptibility, and
minimizes the risk of stiction to the substrate. It also allows the use of single crystal silicon as the
device material, which provides excellent mechanical stability. [2]
The implementing of bulk micromachining can be done by many different fabrication
technologies:
Figure 2-14: Microfabriaction Process
[16]
2.5.2.1. SOI-Based Bulk Micromachining
Silicon-on-Insulator (SOI) wafers are excellent starting materials for bulk micromachining. The
silicon device layer comes bonded on an insulator layer. Electrically isolated and mechanically
anchored free-standing structures can be formed simply by patterning the device layer and the
oxide layer underneath.
Figure 2-13: An SOI-based bulk-micromachined gyroscope, diced and released.
2.5.3. Surface-Micromachining Processes
While bulk micromachining uses subtractive processes to pattern thick structural layers, surface
micromachining is in essence an additive technique. It relies on successive deposition and
patterning of thin structural layers on the surface of a substrate, rather than etching thick bulk
layers.
In surface micromachining, complex three-dimensional devices are built by depositing multiple
stacks of alternating structural layers and sacrificial layers. Each sacrificial layer supports the
structural layer above it during fabrication, and separates it from the other layers below. At the
end of the process, the sacrificial layers are selectively etched away, releasing the structural
layers. [2]
2.5.4. SOI-MUMPs
The following is a general process description and user guide for Silicon-On-Insulator Multi-User
MEMS Processes (SOIMUMPs). It is a simple 4-mask level SOI patterning and etching process
derived from work performed at MEMSCAP.
The process begins with 150mm n-type double-side polished Silicon on Insulator wafers. A
phosphosilicate glass layer (PSG) is deposited, and the wafers are annealed at 1050°C for 1 hour
in Argon to drive the Phosphorous dopant into the top surface of the Silicon layer. The PSG layer
is subsequently removed using wet chemical etching [3].
[17]
Figure 2-14
The wafers are coated with negative photoresist and lithographically patterned by exposing the
photoresist with light through the first level mask (PADMETAL), and then developing it.
Figure 2-15
The wafers are coated with UV-sensitive photoresist and lithographically patterned by exposing
the photoresist to UV light through the second level mask (SOI), and then developing it. The
photoresist in exposed areas is removed, leaving behind a patterned photoresist mask for
etching.
[18]
Figure 2-16
A front side protection material is applied to the top surface of the patterned Silicon layer. The
bottom side of the wafers are coated with photoresist and the third level (TRENCH) is
lithographically patterned.
Figure 2-17
The front side protection material is then stripped using a dry etching process. The remaining
“exposed” oxide layer is removed from the top surface using a vapor HF process.
[19]
Figure 2-18
A separate silicon wafer is used to fabricate a shadow mask for the Metal pattern. The shadow
mask wafers are coated with photoresist and the fourth level (BLANKETMETAL) is
lithographically patterned.
Figure 2-19
The shadow mask is aligned and temporarily bonded to the SOI wafer. The Blanket Metal layer is
deposited through the shadow mask.
[20]
Figure 2-20
The shadow mask is removed, leaving a patterned Metal layer on the SOI wafer.
Figure 2-21
[21]
3. Tuning Fork Gyroscope
3.1. Features of Tuning Fork Architecture For many applications, gyroscopes are subject to a wide variety of changing environmental
conditions such as temperature, pressure, and ambient vibrations. The robustness of the sensor
to these external influences during operation is critical for adequate performance. A level of
robustness is commonly achieved through electronic control systems, such as a temperature
compensation circuit which post-processes the output of the mechanical sensor depending upon
temperature or an automatic mode matching controller. Robustness to ambient vibrations,
however, is generally addressed by the mechanical design through the use of tuning fork driving
architectures. Tuning fork designs have the ability to reject common mode inputs due to anti-
phase forcing which results in anti-phase Coriolis responses [4].
3.2. Design Concept The mechanical architecture of the tuning fork gyroscope, Figure 3-1, comprises of two proof-
masses, supported by a network of flexural springs and anchored at a central post.
The drive-mode of the gyroscope is formed by the two masses forced into anti-parallel, anti-
phase motion synchronized by the integrated mechanical lever system. The sense-mode is
formed by the two linearly coupled tines moving in anti-phase Figure 3-2 [5]. The gyroscope is
electro-statically driven into anti-phase motion using driving voltages imposed across the
differential lateral comb electrodes on the drive-mode shuttles. During rotation around the z-
axis, the Coriolis acceleration of the proof masses induces linear anti-phase sense-mode
vibrations which are capacitively detected using differential parallel plate electrodes on the
sense-mode shuttles [6].
Figure 3-1: Schematic diagram of the TFG
[22]
Figure 3-2: In-plane operating flexural modes. (Left) Drive resonant mode along the x-axis.
The anchor design of the TFG satisfies two critical properties: mechanical coupling and resonant
mode isolation. The mechanical coupling allows synchronization of the phases of the proof-
masses. Hence, the central beam is designed as ladder-shape structure as shown in Figure 3-2.
Due to the non idealities other modes are excited such as pseudo drive and pseudo sense modes,
Figure 3-3, so the anchor should also be able to isolate the in-plane operating modes from the
two other in-plan modes.
Figure 3-3: In-plane pseudo-operating flexural modes. (Left) Pseudo-drive resonant mode
The flexural spring must be designed to ensure large mobility along both axes. To this effect, a
fish-hook architecture was adopted which ensures that the mode shapes have two-directional
flexibility.
3.3. Equations of Motion The TFG can be conceptualized as a coupled resonator system, with the rotation induced Coriolis
force being the coupling agent between the two resonant operating modes. The dynamics of the
device are governed by Newton’s second law of motion [7].
The drive-mode oscillator is most commonly a 1 degree-of-freedom (1-DOF) resonator, which
can be modeled as a mass-spring-damper system consisting of the drive proof-mass m, the
drive-mode suspension system providing the drive stiffness k, and the drive damping c
consisting of viscous and thermoelastic damping. With a sinusoidal drive-mode excitation force,
the drive equation of motion along the x-axis becomes
[23]
3-1
With the definition of the drive-mode resonant frequency wd and the drive-mode Quality factor
Qd the amplitude and phase of the drive-mode steady-state response
becomes:
√ (
)
3-2
at w = wd the amplitude becomes
3-3
where
√
3-4
and
3-5
A rotation signal along the normal axis (z-axis) of the results in a Coriolis induced acceleration
on the individual proof-masses along the sensitive axis (y-axis). The magnitude of the Coriolis
acceleration is given by the vector cross product of the input rotation rate vector and the
velocity of the proof mass (2Ω x V).
Considering that the proof-masses are oscillating in a sinusoidal fashion at the drive-mode
resonance, the expression for the Coriolis acceleration along the sense-axis is given by:
3-6
Where Ωz is the input rotation rate, ‘VDrive-x’ is the velocity of the drive resonant mode, ‘XDrive’ is
the amplitude of drive-mode oscillation and ‘ωDrive’ is the drive-mode resonant frequency. And
from Newton’s second law we know that so we can describe the equation of motion of
the 1-DOF sense mode oscillator by the following:
3-7
The amplitude and phase of the steady-state sense-mode Coriolis response in a linear system,
defining the sense-mode resonant frequency ws and the sense-mode Quality factor Qs, become
[2]:
√ (
)
3-8
where
√
3-9
and
[24]
3-10
The rotation-induced proof-mass displacement along the y-axis causes the gap between the
parallel plate sense electrode and the proof-mass to change. This change in capacitive gap is
proportional to the input rotation rate, and is detected by means of transimpedance front-end
electronics.
3.3.1. Drive-Mode Actuation
A key parameter that determines both the resolution and the sensitivity of a micromachined
vibratory gyroscope is the drive amplitude. For this reason, comb-drive electrodes were chosen
ahead of parallel-plate electrodes as the choice of actuation for the drive resonant mode. Comb-
drive actuation offers greater linear range of operation as well as larger drive displacement
before pull-in.
The overall capacitance of the comb-drive electrode is expressed as:
(
) 3-11
where ‘N’ indicates the number of combs, ‘h’ refers to the
comb-thickness, ‘wo’ is the initial overlap, ‘g’ is the adjacent
gap size, ‘x’ is ‘y’ represents the transversal displacement
along the sense axis (y-axis) which may be caused either by
Coriolis or quadrature errors [7].
We also know that
3-12
From equation 3-11 and equation 3-12 we can get the
following:
3-13
We can neglect y with respect to g as y << g, equation 4-13 becomes:
3-14
3.3.2. Sense-Mode Detection:
Based on the comparison in Table 2-1 and as we are not in need for a large displacement,
variable-gap detection will be used as the choice of detection for the sense mode detection.
The capacitance of the sense electrodes is expressed as:
3-15
where ’ls’ is the overlap length between the two electrodes, ‘t’ is the thickness, ‘gs’ is the initial
gap between the electrodes, and ‘y’ is the lateral displacement amplitude along the sense axis (y-
axis).
Figure 3-4: comb-drive electrode
[25]
3.4. Mechanical Design Consider the design shown in Figure 3-1; we need to determine all the dimensions of the proof-
masses, actuators, and detectors. After that, we can calculate the change in the actuation and
detection capacitances. The intention of this design is to get a change in the drive mode
capacitance differentially and change in the sense mode capacitance
differentially with a biasing voltage V < 10V. We first select the width ‘W’, length ‘L’, thickness ‘t’
of the proof-masses (W = 0.4 mm, L = 0.27 mm, and t = 25 um) sticking to the size specifications
and design rules. Then determine the drive and sense frequencies at which the device will
operate ( = 7.5 KHz and = 7.7 KHz).
We can now calculate the stiffness of the flexure beams along the drive axis (x-axis) using
equation 3-4 we get .
Assuming the gap between the fingers in the comb-drive actuators to be g = 3 um and the
thickness of one finger b = 3 um taking into consideration that they must be greater than the
minimum feature length given in the design rules.
From the previous assumed dimensions of the comb-actuator we find that the maximum
allowable number of fingers is N = 38 finger. We use Na = 27 finger for detection and Nd = 11 for
actuation.
Now by applying a volt V = 9.5 V we get the drive force using equation 3-13
and from equation 3-3 we calculate Xo = 4.83 um at QD = 500.
As mentioned above we need a change in the drive mode capacitance > 10 fF, from equation 3-
11 neglecting ‘y’ with respects to ‘g’ we can deduce the change in capacitance as described in the
following equation:
3-16
From equation 3-16 and all the previous calculations we compute differentially.
As mentioned before that the rotation-induced proof-mass displacement along the y-axis causes
the gap between the parallel plate sense electrode and the proof-mass to change. This change in
the gap causes a change in the sense capacitance. To calculate this change we need first to
calculate the displacement in y-direction. After that, we found the change in capacitance by using
the following equation:
3-17
where
and .
After some calculation using equation 3-8 with we get y = 0.0037 um. As a result we
get differentially.
3.5. Finite Element Simulation After the previous first order analysis, a 2-D Finite Element Analysis (FEA) was carried out using
the values calculated in the previous section, the FEA revealed 4 in-plane modes. The first mode
was pseudo drive mode at about 7.48 KHz; the second mode was the anti-phase drive mode at
about 7.52 KHz the fourth and fifth was sense mode and pseudo sense mode at about 7.7 KHz
[26]
and 8.8 KHz, respectively as shown in Figure 3-5. The difference in the resonant frequencies
between the model and FEA might have happened due to the approximations done when
calculating the masses and stiffness. An ANSYS script that animates the mode shapes of the
tuning fork structure can be found in Appendix C.
(a)
(b)
(c)
(d)
Figure 3-5: (a) Drive-mode; (b) Sense-mode; (c) Pseudo drive-mode; (d) Pseudo sense-mode
3.6. Summary of Tuning Fork Gyroscope The tuning fork gyroscope has important features compared to other vibratory gyroscopes.
3.6.1. Advantages of Tuning Fork Gyroscope
Tuning Fork Gyroscope (TFG) is designed with a symmetrical structure.
It employs two masses that vibrate out of phase. This differential operation cancels
common-mode errors.
It also doubles the amplitude of the output signal.
High sense capacitance.
3.6.2. Disadvantage of Tuning Fork Gyroscope
Small displacement in the sense mode.
Large zero bias errors caused by the slight misalignment of the mass centers of the
individual tines.
If the electrostatic drives for the individual tines are not preciously matched, an out of
plane vibration response is introduced.
[27]
4. VIBRATING RING GYROSCOPE The vibrating ring gyroscope is based on the transfer of energy between two identical modes,
thus we can expect high sensitivity. The rotation sensing principles of the vibrating shell
gyroscope can be explained as the ring vibrates in an elliptical (flexural) manner that have two
nodal diameters. When the structure is rotated, the node lines lag behind the rotation (Figure
4-1) [8]. Therefore, the principle of operation of a vibrating ring gyroscope will be: exciting the
ring to vibrate elliptically (Drive mode), then monitoring the lag of the nodes capacitively.
Figure 4-1 Vibrating Ring and lagging nodes
4.1. Vibration Modes of the Ring Structure The vibration of the ring structure can be explained by the normal mode model. In this model,
the elliptic vibration of the ring is considered to be a superposition of two identically shaped
vibration modes. Because of their mode shapes, the locations of maximum motion or antinodes
for the two vibration modes are 45o apart rather than 90o as in the tuning fork gyroscope.
Coriolis effect causes energy transfer between the two modes. [8]
4.1.1. Normal Mode Model
Any general vibration-induced displacement of an elastic body ( can be expressed by the
linear combination of its normal vibration modes :
∑ 4-1
where p is the independent position coordinate which can be expressed by Cartesian
coordinates (x and y) or by cylindrical coordinates (radial and tangential coordinates). The
equation includes generalized (modal) coordinates (mode amplitudes) (i.e. ) and mode
shape functions (i.e. ). [2]
4.1.2. Mode Shapes
There are several modes for the ring structure (out of plane, torsional, translational, and flexure
modes). The most important mode shapes, as mentioned by [9], are four. The first two modes
are translation modes in the x and y directions ( ), and their radial/tangential
components are:
X-axis translation mode:
[28]
4-2
Y-axis translation mode:
4-3
where θ is an independent spatial coordinate (angle) describing position around the ring. The
second two modes are elliptical-shaped flexural modes ( ), and their radial/tangential
components are:
Drive axis flexure mode:
4-4
Sense axis flexure mode:
4-5
Where determines the angle between the principle mode axis and the horizontal axis [8], to
simplify the math, we take , the radial components of the mode shapes are plottet in
Figure 4-2. It’s clear that the each of the two flexure modes has its nodes on the antinodes of the
other. Figure 4-3 shows the vibrations of the ring. A Scilab code for these plots can be found in
Appendix D.
(a) (b)
Figure 4-2 Mode amplitude plots of the ring vibrations
(a) Horizontal and Vertical Translational Modes, (b) Primary and Secondary Flexural Modes
[29]
(a) (b)
(c) (d)
Figure 4-3 Evolution of Translational (a, b) and Elliptic (c, d) vibrations of the ring structure
4.1.3. Equations of Motion
We Consider the ring structure in Figure 4-4 Conceptual view of a MEMS ring gyroscope, the ring
structure is attached to an anchor by 8 symmetric curved beams, the ting is driven into flexure
mode horizontally by two electrodes at 0o and 180o, and the two electrodes at 45o and 225o are
used for sensing (Open Loop Operation).
Unlike the non-degenerate gyroscopes, like tuning fork gyros, ring gyroscopes cannot be
analyzed using simple lumped models because the mass and the stiffness of the ring gyro are
distributed along the ring. The equations of motion of the ring gyroscope structure can obtained
by deriving the kinetic energy, potential energy, and dissipated energy by viscous damping for
each mode, and substituting in Lagrange’s equation.
[30]
Figure 4-4 Conceptual view of a MEMS ring gyroscope
Considering the flexure and translational modes only, the equations of motion can be expressed
as shown below, a detailed derivation of these equations is done in [9], and the final results
were:
[
] [
] [
] [
] [
] [
]
[
] [
] [
] [
]
[
] [
] [
] [
]
[
] [
] [
] [
]
[
]
4-6
where line (1) represents Mass, Damping, and Stiffness; M1, M2, M3, M4 are the modal masses of
the modes 1, 2, 3, 4 respectively, C1, C2, C3, C4 are the viscous damping coefficients for each mode,
K1, K2, K3, K4 are the stiffness seen by each mode due to support springs, for the translational
[31]
modes, and due to a combination of the support springs and the ring structure stiffness for the
flexure modes. The terms in line (2) (γT and γF) represents the modal coupling terms induced by
the Coriolis forces and by angular acceleration, the angular acceleration is negligible because the
ratio between angular acceleration to Coriolis response is inversely proportional to the flexural
resonant frequency , Line (3) contains additional stiffness terms that arise from centripetal
acceleration and electrostatic effects (α, β, χ), line (4) contains the terms representing the
environmental excitation ( and vo), and it’s clear that the ambient vibrations affect only the
translational modes, line (5) contains a term from the electrostatic actuation. Details of
Calculation of each term in the previous matrices are explained in [8], [9]..
From the equations of motion, it’s clear that the four modes form two decoupled sets of
equations in the absence of angular rotation; which independently govern the translation and
flexural modes. Therefore, the flexural modes, which are excited by the operation of the ring
gyroscope, are not influenced by the translation modes which are excited by the environmental
vibration. Thus, the flexural modes are not influenced by environmental vibrations (Ideally)
[9,10].
4.2. Vibration Induced Errors in Ring Gyroscopes When looking at the previous equations (4.6), it seems that the output of a ring gyroscope is
insensitive to vibration due to the decoupled dynamics governing ring translation versus ring
flexure; however, this decoupling is violated in the presence of non-proportional damping and
capacitive nonlinearity at the sense electrodes [9,11,10].
4.2.1. Vibration Induced Errors due to Non Proportional Damping
Proportional Damping is the type of damping in which the modal damping matrix [C] is in the
form of:
[ ] [ ] [ ] 4-7
where [M], [K] are the modal masses and stiffness respectively, α, β are constants, usually
empirical. This type of damping is known as PROPORTIONAL, i.e proportional to either the mass
M of the system, or the stiffness K of the system, or both. Proportional damping is rather unique,
since only one or two parameters, α, β, appear to fully describe the complexity of damping,
irrespective of the system number of DOFs, n. This is clearly not realistic. Hence, proportional
damping is not a rule but rather the exception. [9]
Considering Proportional Damping, the damping matrix is diagonal, since the matrices of mass
and stiffness are supposed to be diagonal, which results in decoupled modes. However, Non-
Proportional damping has been observed in MEMS gyroscopes. In case of non-proportional
damping, the damping matrix contains non-zero off-diagonal elements as follows:
[
]
where N is the number of modes of the structure, and this is considered as one of the causes of
undesired mode coupling.
[32]
4.2.2. Vibration Induced Errors due to Non Linearity of Sense Electrodes
The parallel-plate sensing mechanism contributes a nonlinear behavior between sense
capacitance and the sense-axis displacement. This nonlinearity is negligible in normal operation
because the displacement produced by the Coriolis force is small. However, larger displacements
can be readily generated by vibration, and these displacements are subject to capacitive
nonlinearity. [11]
Vibration-induced errors are explained in [9] by subtracting the capacitive change by only
Coriolis force and no external vibration, from the capacitive change by both Coriolis force and
external vibration, and removing the signals produced having frequencies far from the resonant
frequency of the gyroscope (∼20 30 kHz), because they will be filtered out by the interface
circuit demodulation system. The resulting change in capacitance due to vibrations is given by:
[
]
4-8
where / and / are the initial capacitance and the initial gap of the sense
electrode at 45/225. In an ideally fabricated symmetric ring structure, = and =
and becomes:
4-8
Therefore, another source of vibration-induced errors in ring gyroscopes arises from the high
order (cubic) terms in the capacitive nonlinearity at the sense electrodes.
There are other vibration induced error sources like those resulted from high frequency external
vibration or from imperfections that couple ring translation and flexure. High frequency
vibration (with spectral content frequency containing the flexural-mode resonant frequencies)
may directly excite the flexural modes leading to undesired responses that cannot be
distinguished from the desired responses excited by ring gyro operation. This error mechanism
obviously exists even for ideally fabricated ring gyroscopes.
On the other hand, vibration-induced errors by fabrication imperfection may occur when the
flexural modes are excited by translation modes. The decoupling of flexural and translation
modes can arise from the assumed perfect symmetry of the ring gyro. The symmetry may be
destroyed by a non-uniform or asymmetric distribution of ring mass and/or stiffness (inertial
and/or compliance coupling) as previously noted in analyses of degenerate gyroscopes.
4.3. A HARPSS Polysilicon Vibrating Ring Gyroscope A famous design example about ring gyroscopes was the one made in [12]. The paper presents a
80-μm-thick, 1.1 mm in diameter high aspect-ratio (20:1) polysilicon ring gyroscope (PRG). A
detailed analysis has been performed to determine the overall sensitivity of the vibrating ring
gyroscope and identify its scaling limits. An open-loop sensitivity of 200 μV/deg/s in a dynamic
range of ±250 deg/s was measured under low vacuum level for a prototype device. The
resolution for a PRG with a quality factor (Q) of 1200, drive amplitude ( ) of 0.15 μm was
measured to be less than 1 deg/s in 1 Hz bandwidth, limited by the noise from the circuitry.
The vibrating ring gyroscope, shown in Figure 4-5 [12], consists of a ring, eight semicircular
support springs, and drive, sense and control electrodes. Symmetry considerations require at
[33]
least eight springs to result in a balanced device with two identical elliptically-shaped flexural
modes that have equal natural frequencies and are 45o apart from each other. The ring is
electrostatically vibrated into the primary flexural mode with fixed amplitude.
Figure 4-5 The HARPSS Vibrating Ring Gyroscope – (a) SEM Image, (b) Electrode Voltages
In this section, we will apply the model suggested by the authors of [4] to redesign the HARPSS
Gyroscope.
4.3.1. Mechanical Design
General gyro specifications often include gyro size, environmental conditions (or applications),
or sensitivity. We first select the ring structure radius ( = 550 μm) from the size
specification and flexural and translation resonant frequencies ( = 29 KHz and =20 KHz)
from the environment conditions (or applications) or g-sensitivity (sensitivity to linear
acceleration). The g-sensitivity (in deg/s/(m/s2)2 is given by [9]:
4-10
Where is the angular rate, is the gap between the capacitor’s electrode and the ring.
The flexural resonant frequency (used for drive and sense modes) should lie well above the
frequency spectrum of the environmental vibration. The support beam radius ( = 235
μm) is successively set to be from a half to a quarter of the as observed in Figure 4-4.
Next, we adjust the effective mass [ ] and stiffness [ ] matrices in equation 4.2 to match the
decided flexural and translation resonant frequencies. The flexure mode is concerned with only
4 springs, thus the flexure mode effective mass in the mass matrix is calculated as shown below:
4-11
Where and are the effective mass of the ring frame and the support
springs that is stretched horizontally for the flexure mode and can be considered as one third of
the actual mass if the spring is stiff, and half of the mass if the spring is compliant [13]:
4-12
4-13
[34]
Where , are the width and the thickness of the structure, is the density = 2328
Kg/m3. For the translational modes, the effective mass is approximately the sum of two
horizontal, two vertical and four 45o effective spring masses. In addition to the actual ring mass:
4-14
Where and , can be considered as half of the spring’s mass (since
they are very compliant).
The stiffness matrix is calculated from the curved beam stiffness equations 2.10, 2.11, and 2.12):
4-15
4-16
Where = 150 GPa, for , , and , = = 235 μm, and = at r = ,
because the ring frame is considered as 2 parallel curved beams [12]. By dividing by , and
equating the resulting expression to the square of the resonance angular flexure frequency, we
can obtain the width of the ring ( μm), substituting in mass and stiffness matrices to
get and . The height of the ring is still not calculated because
the resonant frequencies of the ring don’t depend on it [12]. is better to be set to a large
value to reject out of plane modes, but this will require higher driving voltage to maintain the
same drive amplitude as shown in the Electric design part in 4.3.3, we will set the height to 80
μm as the paper.
4.3.2. Finite Element Simulation
After the previous first order analysis, a 2-D Finite Element Analysis (FEA) was carried out using
the values calculated for ring and spring dimensions (Figure 4-6), by tuning the obtained values
for the ring dimensions above, the FEA revealed 5 in-plane modes at μm and =
235 μm. The first mode was torsional at about 10KHz (the outer ring is rotating about with its
center in the middle of the inner circular post), the second two modes were translational ones at
about 20 KHz the fourth and fifth were flexure at approximately 28 KHz. The difference in the
resonant frequencies between the model and FEA might have happened due to the
approximations done when calculating the effective masses and stiffness. The mode shapes
weren’t very accurate due to asymmetries in the mesh which caused rotation of the principle
mode axis. However, this won’t affect the resonant frequencies too much, and can be managed
by balancing electrodes. 2-D FEA didn’t show out of plane modes, however we shouldn’t worry
about them since they are minimized due to the high aspect ratio of the device. An ANSYS script
that animates the mode shapes of the ring structure can be found in Appendix E.
[35]
(a) (b)
(c) (d)
Figure 4-6 Finite Element Analysis of the HARPSS Ring Gyroscope – (a) X-Axis Translational Mode, (b) Y--Axis Translational Mode, (c) Primary Flexural Mode, (d) Secondary Flexural Mode
4.3.3. Electrical Design
The driving specification of the electric design is the sensitivity (or may be the resolution)
requirement. It is calculated from the capacitive change per angular rate which is given by [11]:
4-17
where is the number of used sense electrodes, is the rest capacitance of the electrode,
is the angular gain 0.37, is the quality factor, is the drive mode amplitude.
Given that the required sensitivity is 0.12 fF/(deg/s), the number of electrodes to be used for
sensing or driving is 2 (for each, see Figure 4-4), quality factor of 1200, electrode gap
(from equation 4.10), Polarization voltage of the ring , we can assume
values for drive mode amplitude: , therefore the needed electrode capacitance
. The electrode capacitance is given by:
4-18
Therefore, we can let the height of the electrode , to have the angle
. From the drive mode amplitude, the damping coefficient ( ) can be found:
[36]
4-19
Therefore, the AC drive signal is equal to 15.5 mV. The value is too far from what was
mentioned in the paper (5-8mV) because the equations of motion were derived based on the
usage of 2 driving electrodes at 0o and 180o as illustrated in Figure 4-4, while the operation
mode of the gyroscope in [12] was different (Force to rebalance mode, see Figure 4-5 The
HARPSS Vibrating Ring Gyroscope – (a) SEM Image, (b) Electrode Voltages - b). Table 4-1
Summary of Design Parameters estimated by Model, FEA, and Achieved in the paper.
Table 4-1 Summary of Design Parameters estimated by Model, FEA, and Achieved
Design Parameter Model FEA Achieved
Flexure Mode Effective Mass 2.05x10-9 Kg 2.04x10-9 Kg Translational Mode Effective Mass 4.54x10-9 Kg
Flexure Mode Stiffness 65.38 N/m 63.46 N/m Translational Mode Stiffness 74.84 N/m
Flexure mode resonant frequency 28.38 KHz 28.08-28.17 KHz 28.3 KHz Translational mode resonant frequency 20.44 KHz 19.26-19.36 KHz
Ring and Spring Width 3.9 μm 4.0 μm 4 μm Electrode Gap Spacing 1.4 μm 1.4 μm
Electrode Height 60.0 μm 60.0 μm Length of Electrode 148 μm 150.0 μm AC Signal Amplitude 15.5 mV 5-8 mV
The results in Table 4-1 shows that the approximations done to calculate the effective masses of
the flexure and translational modes were acceptable for a first order hand analysis.
4.4. Evaluation of Vibrating Ring Gyroscope
4.4.1. Advantages of Ring Architecture
The vibrating ring structure has important features compared to other architectures. In a brief:
It has a balanced symmetrical structure that is less sensitive to environmental
vibrations.
Since two identical flexural modes of the structure are used to sense rotation, the
sensitivity of the sensor is amplified by the quality factor of the structure (Eq. 4.17).
The vibrating ring is less temperature sensitive since the two flexural vibration modes
are affected equally by temperature [8].
Any frequency mismatch between the drive and sense resonance modes that occurs
during fabrication process (due to mass or stiffness asymmetries) can be electronically
compensated by use of the tuning electrodes that are located around the structure [8].
More resistive to ambient vibrations [9,10].
4.4.2. Disadvantages of Ring Architecture
Lower pick off capacitance compared to tuning fork gyroscopes [8].
Requires a high aspect ratio fabrication process; thin tall structure is needed to obtain
reasonable actuation voltages and low resonant frequencies [8].
[37]
5. Interface Electronics
5.1. System Components Simple generalized model of a gyroscope with the electronic interface necessary to produce the
final output. An oscillator establishes the drive oscillation at the drive resonance frequency, and
the Coriolis readout interface detects and amplifies the Coriolis acceleration. A demodulator
demodulates the angular rate signal from the Coriolis acceleration, and a low-pass filter removes
other unwanted signals out-side the desired frequency band, from the final output. [14]
Figure 5-1 generalized model of a gyroscope with the electronic interface
5.1.1. Drive loop
The drive loop electronics are responsible for starting and sustaining oscillations along the
reference axis at constant amplitude. It is essential that a constant drive amplitude be
maintained, as any variation in the drive amplitude manifests itself as a change in velocity of the
mechanical structure (along the driven axis). Velocity fluctuations modulate the sensor output
and can result in false or inaccurate rate output.
There are two approaches to implement the drive loop, both of which have been implemented in
this work:
• An electromechanical oscillator: Here the drive mode oscillations are started and sustained
by using a positive feed-back loop that satisfies the Barkhausen’s criteria (Loop gain = 1, Loop
Phase shift = 0o) based on the natural frequency of the mechanical gyrpscope.
• A Phase-Locked Loop(PLL) based approach: Here the reference drive vibrations are set-up
using a phase locked loop (PLL). The PLL center frequency and capture range are set close to the
drive resonant frequency of the gyroscope. On power up, the PLL locks on to the output of the
front-end. The PLL output is amplified or attenuated to achieve the desired voltage amplitude
and used to drive the microgyroscope. [15]
[38]
5.1.2. Sense loop
The primary function of the sense channel is to extract the input rotation information from the
gyroscope output. The AM Coriolis output is demodulated using the drive oscillator signal. This
phase sensitive demodulation allows for the rejection of the interfering mechanically generated
quadrature error, due to the inherent 90 phase difference between the quadrature and Coriolis
signals. The low-pass filtered base-band signal is proportional to input rotation rate, and may be
amplified if necessary at a later stage. Since synchronous demodulation allows for phase
sensitive detection and rejection of quadrature error, it is preferred over other techniques such
as envelope detection. [15]
Sense loop can be open or closed loop, open-loop is widely used since it’s requires simple
electronics design, while closed-loop rate sensing electronics (mostly digital) the feedback
mechanism generates an electrostatic rebalancing force to damp the displacement of the proof
mass in response to an angular rate, also the dynamic range of the readout setup can be
significantly improved. Indeed, by increasing the maximum attainable feedback force, larger
input forces can be measured without saturating the readout and interface circuits (because
these circuits only process the error signal). [16]
5.2. Overview of sense and drive electronics Reviewing many systems we will discuss the following to understand the main blocks of the
readout/control circuits of the gyroscope interface:
A low-noise interface circuit for MEMS vibratory gyroscope [17]
The interface circuit shown in Figure 5-2 consists of two axis, closed-loop drive axis and sense
axis. The main task of closed-loop drive axis control system is to initiate and maintain an
oscillation along the drive axis with constant amplitude at the resonant frequency. There are two
kinds of closed-loop drive control systems: single closed-loop (AGC control loop) drive system
and double closed-loop (both amplitude and phase control loop) drive system. The single closed-
loop is lower cost and easier to implemented in hardware
This readout circuit for micromachined differential capacitive sensors is based on charge
sensitive amplifiers (CSA). In the drive axis, CSA is used to convert the capacitive signals to
voltage and modulate the signals to the chopping frequency of 2MHz by a sine wave VAC applied
on the proof-mass. Thereafter, the signals are filtered out low frequency noise and amplified,
and their levels are adjusted by a variable-gain amplifier (VGA). The gain of VGA is controlled by
the amplitude of the drive axis sensing signal. A phase shifter is used to ensure a loop phase of
0˚. Therefore, the AGC control loop ensures an oscillation with constant amplitude along the
drive axis. As the common-mode voltage of 2.5V in-chip is too low to cause a gyroscope to
vibrate, an off-chip level shifter is applied in the loop to lift the DC level of the signal to 5V.
Then, in the sense axis, most circuit blocks are the same as in the drive axis. Proof-mass due to
both Cosriolis acceleration and quadrature error take place at the resonant frequency. The rate
and quadrature can be distinguished by modulating the sense output with the 0˚ and 90˚ signals
from drive axis output.
[39]
Figure 5-2 A low-noise interface circuit for MEMS vibratory gyroscope
A CMOS-MEMS Gyroscope Interface Circuit Design With High Gain and Low Temperature
Dependence [18]
In Figure 5-3 the proof mass is driven to resonance using a self-oscillation loop. A fully-
differential TIA, whose gain is tunable by the gate voltage, picks up the displacement of the proof
mass in the driving mode and generates 90 phase difference. The signal is further amplified to be
large enough to excite a self-oscillation by feeding it back to the driving electrodes. The am-
plitude of the driving signal is controlled by an automatic gain control (AGC) loop (not shown),
which compares the amplitude of the driving signal with a reference and generates a gain-tuning
signal through a low-pass loop filter.
When the system is subject to a rotation, the Coriolis-acceleration induced displacement signal is
amplified by the a differential difference amplifier (DDA can achieve low dependence on
temperature and process) and the following gain stages. The amplified Coriolis signal is de-
modulated using a chopper mixer, and filtered by an off-chip low-pass filter to obtain the
rotation rate. Since the Coriolis signal is in phase with the driving signal of the resonator in this
design, the quadrature error, which is an error due to the crosstalk from the driving-mode
movement and has a 90˚ phase difference with the Coriolis signal, is removed after the
synchronized demodulation and filtering
Figure 5-3 CMOS-MEMS Gyroscope Interface Circuit Design With High Gain and Low Temperature Dependence
[40]
A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork
Microgyroscopes [19]
In Figure 5-4 this circuit, the drive-mode oscillation is sensed by a transresistance amplifier,
where the feedback resistance is controlled by an automatic level controller (ALC) for constant-
amplitude vibrations. Similarly, in the sense-mode, differential transimpedance amplifiers
convert the resultant capacitive changes in response to an applied angular rate to voltage for
further signal processing operations. Since the sense-mode transimpedance amplifier output is
an amplitude-modulated signal at the frequency of drive-mode oscillations, a demodulator
circuit composed of a multiplier followed by a low-pass filter transfers the signal to the
baseband, where the carrier signal of the demodulator is generated by a PLL circuit connected to
the drive –mode oscillator.
Figure 5-4 A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes
A digitally controlled MEMS gyroscope with unconstrained sigma-delta force-feedback
architecture [16]
A system-level representation of the gyroscope is shown in Figure 5-5, the drive loop consists of
digital quadrature oscillator (DCO) which provide a sinusoidal signal is derived which defines
the wanted driving force, amplitude controller to control the amplitude of the driving force, and
a Σ∆-modulator used to convert the driving force into a oversampled one-bit signal. This one-bit
signal is further used for actuation. Depending on the binary value, an electrostatic force Fel is
applied in either the positive or the negative x-direction (driven mode). This is accomplished by
applying a fixed voltage to a comb- like actuator, which results in force pulses with constant
magnitude, independent of the position of the proof mass in the x-direction. As a result, the
actuation approach realizes an inherent digital-to-force conversion with good linearity. The
sense loop is a closed loop; the force-feedback mechanism generates an electrostatic rebalancing
force to damp the displacement of the proof mass in response to an angular rate. Although this
mechanism requires complicated electronics and gives a quantization noise that is needed to be
considered, but it gives more linear response in a higher bandwidth since the sense-mode of the
gyroscope is forced to be stationary, the output is AM-modulated signal where a coherent
demodulator is used to demodulated the signal gives the angular rate data.
[41]
Figure 5-5 A digitally controlled MEMS gyroscope with unconstrained sigma-delta force-feedback architecture
A digitally controlled MEMS gyroscope with 3.2 deg/hr stability [20]
The interface ASIC in Figure 5-6 contains several blocks controlled by clock signals. Therefore,
the clock distribution has been designed to emit as little substrate noise as possible. A great
effort has also been spent on the ∑∆-modulator, since the data streams are semi-stochastic and
might generate noise when folded by the measurement circuitry.
The control loops, the demodulation circuitry, filtering and timing are implemented as a digital
configuration of the FPGA. The interface ASIC and the FPGA communicate through digital ∑∆-
modulated bit streams. The interface ASIC is built up from two identical signal paths. One for the
excitation loop and one for the detection loop. Each loop consists of a charge amplifier, a ∑∆-
modulator, a digital feedback implementation with a ∑∆-modulated feedback signal and a
recovery circuit for the feedback signal.
The charge amplifiers are fully differential charge Integrators. The recovery circuits also low-
pass filter the data stream to avoid the high frequency ∑∆-noise.
The digital signal processing consists of three main blocks, the excitation feedback, the detection
feedback and the output generation. A11 blocks have in common that they work only on the
necessary bit width and part of the algorithms even operates directly on the ∑∆ bit-stream.
The purpose of the excitation feedback loop is to make sure that the excitation mode oscillation
has constant amplitude. The detection feedback algorithm makes sure that the bandwidth of'
the detection mode, and thus the rate signal bandwidth, is increased. Both control loop
algorithms contain digital ∑∆-modulators, which output ∑∆ bit-streams back to the ASIC's
recovery circuits.
The output generation block performs the mixing and low-pass filtering of the excitation and
detection signals to generate a rate signal.
[42]
Figure 5-6 A digitally controlled MEMS gyroscope with 3.2 deg/hr stability
[43]
6. Building Blocks In this chapter, the major control blocks of the gyroscope interface system are identified and
discussed. The entire system of the gyroscope may be broadly classified under two parts (1) the
drive loop – which oscillates the proof-masses at the drive-mode resonant frequency with a
constant displacement amplitude which consists of frequency synthesizer and Automatic Gain
Control (AGC) (2) the sense channel – which extracts the input rotation signal information from
the AM modulated Coriolis response which consists of the Analog to Digital converter followed
by the demodulation block to extract the final output, both of the loops needs an interfacing
block with the mechanical gyroscope which is the capacitive sensing block.
6.1. Capacitive interface
6.1.1. Theory of Operation
The first step in developing a MEMS based microsystem is to choose an appropriate front-end
interface to convert the mechanical signals such as displacement and velocity into electrical
quantities, i.e., voltages and currents. The choice of the interface topology depends significantly
on the nature of the mechanical system at hand. [15]
6.1.2. Capacitive sensing VS Resistive sensing
Position sensing through capacitance change is the key point in many applications of MEMS
structures including micromachined vibratory gyroscopes. For high-performance gyroscopes, it
is required to sense capacitance changes in the order of zepto-farads (1zF = 10-21F) in response
to physical displacements much smaller than the diameter of a silicon atom. Such small changes
can only be detected by dedicated interface electronics converting the charge at the output of the
capacitive gyroscope to a voltage signal. Being the interconnection between mechanical and
electrical domains, these interfaces have considerable effect on the overall performance of the
gyroscope; therefore, they should meet some challenging requirements. An ideal interface must
have very low noise and introduce no phase error.
The Figure 6-1 illustrates the generalized view of a basic interface circuit. In this circuit, current
injected from the gyroscope is converted to voltage according to basic Ohm’s voltage expression
given as
[
] (6-1)
where Av is the voltage gain of the amplifier, Is is the current pumped by the gyroscope, Cs is
the stationary capacitance between the sense electrode and the proof mass, Cp is the total of
parasitic capacitances, and Zint is the effective impedance of the interface.
Figure 6-1- generalized view of a basic interface circuit
[44]
The interface electronics can be classified into two basic categories as resistive-type and
capacitive-type according to the type of dominant interface impedance, Zint, on which the
generated charge is converted to voltage.
In resistive-type interfaces, the resistance dominates the effective impedance and biases the
high-impedance node to a DC potential, which is usually ground. This biasing is quite important
in the sense that floating nodes are very susceptible to leakage currents and external noise
signals, leading unpredictable behavior at the gyroscope output. For a proper biasing resistor
and assuming that the amplifier has infinite input impedance, the equivalent input current noise
of the resistive-type interface can be estimated as
(6-2)
where vi is the input -referred voltage noise of the amplifier, from the above equation it’s
obvious for the maximum resolution that the interface resistor should be as large as possible to
minimize the current noise.
But parasitic capacitances limit the maximum value of the resistor as the total effective
impedance of the capacitors should be much larger than that of interface resistor
[
] (6-3)
for almost purely resistive interface impedance. Otherwise, together with the possible large
parasitic capacitances, such resistors would introduce phase errors, slow down the circuit and
load the resonator.
On the other hand, in the case of capacitive-type interface, biasing resistors are designed to have
much larger impedance than that of equivalent interface capacitance, i.e.
, so that
the current-to-voltage conversion is achieved on the dominating capacitance, and circuit
becomes a current integrator whose current-voltage expression is approximated as
(
) (6-4)
Obviously, the noise analysis of the capacitive-type interfaces should be carried out in the
frequency domain. In this case, white noise spectrum of the resistor thermal noise is shaped by
the RC low-pass filter formed by the biasing resistor itself and the charge integration capacitor.
Then, the amplifier noise adds up to this noise giving total output referred voltage noise of
(6-5)
So,
(6-6)
Then the equivalent input referred current noise given as
(6-7)
[45]
So in order to decrease the current noise and increase the resolution, equivalent capacitance
across the high-impedance node and AC ground should be decreased. However, this capacitance
is limited by the parasitic capacitances coming from amplifier itself, interconnect metallization
and wirebonds. Moreover, as the impedance of the effective capacitance increases, the biasing
resistor should also be increased so that the capacitance is the dominant element and phase
error is in tolerable ranges.
Another problematic issue in capacitive-type interfaces is the 90˚ phase shift introduced
inherently by the charge integration. This implies that an additional 90˚ phase shifting circuit,
such as integrator or differentiator, is required in the drive-mode self-oscillation loop, making
the overall circuit more complicated.
Therefore, resistive-type interfaces, which ideally have either 0˚ or 180˚ phase shift, are usually
preferred in the drive-mode electronics although capacitive-type interfaces have better
sensitivity performance. In fact, sensitivity performance of the interface is not critical in the
drive-mode as long as the oscillation criteria are satisfied. [21]
So we are concerned more about capacitive type in this project to satisfy the best resolution for
sensing and for simplicity symmetry of designing for both sense and drive loops besides the
main advantages of low-power, high-sensitivity, relatively simple structure, and inherently low
temperature sensitivity.
6.1.3. Main ruling Specs
Noise Floor (º/sec/sqrt(Hz))
Affected by electronic noise of the interface
Bandwidth
Parasitic and rest Capacitances
Amplifier noise
Power dissipation
6.1.4. Electronic Noise Sources
Various electronic noise sources exist in the interface circuits, by studying the noise sources in
the generic capacitive to voltage interface (C/V) shown below (Figure 6-2)
Figure 6-2- electronic noise sources in the interface circuits
[46]
Electronic noise comes from the following four sources: the thermal noise of the sensing node
biasing resistance in,b , the thermal noise from the input transistor in,th, the flicker noise from the
input transistor in,flicker , and noise from the load in,load.
Neglecting in,load by considering minimized noise in following stages we consider the rest of noise
sources mentioned above.
√
(6-8)
(6-9)
(6-10)
where W and L are the channel width and length of the MOSFET, gm is the transconductance of
the MOSFET, ID is the bias current of the MOSFET, k is the Boltzman’s constant, T is the
temperature in Kelvin, μn is the carrier mobility, Cox is the gate capacitance per unit area, Kf is
the flicker noise coefficient, Rb is the resistance value of the biasing resistance, f is the frequency
at which the circuit is operated and ϒ the MOSFET thermal noise coefficient (2/3 for long
channel transistors). [17]
6.1.5. Capacitive Sensing configurations
Capacitive sensing is based on motion-induced charge transfer, which consequently generates
an ac voltage or current. With different mechanical designs and wiring methods, the sensing
capacitors from the transducer can be configured into a voltage source, a current source, or a
charge source. Accordingly, there are three different topologies for the readout circuit: reading
the voltage, reading the current, and reading the charge, as shown in Figure 6-3Figure 6-3 below
(a), (b) and (c) respectively. Voltage sensing and current sensing can be easily implemented with
continuous-time circuits, while it is more convenient to implement charge sensing in discrete-
time switched-capacitor circuits. [22]
Figure 6-3- topologies for the readout circuit
Reading Charge configuration can be implemented by Switched-capacitor (SC) charge
integration amplifier, while reading current by continuous-time (C/C) current readout with
transimpedance amplifier (TIA), and reading voltage by continuous-time voltage readout (C/V).
[47]
The C/V readout can be realized by three approaches: unit-gain buffer, capacitive feedback
architecture, and open-loop architecture. [23] [17]
6.1.5.1. Continuous-Time Voltage Sensing
6.1.5.1.1. Unity-gain voltage buffer
Figure 6-4 - Unity-gain voltage buffer
In this architecture, the output signal is given by
(6-11)
In order to minimize the noise it is desired to increases the ac signal beyond the corner
frequency of the amplifier so only thermal noise became dominant. Also increasing the drive
voltage amplitude (Vm) and reducing the parasitic (Cp) improve the minimum detectable
capacitance.
The effective input parasitics can be reduced by boot-strapping where the interconnects from
the sensor to the readout front-end are shielded and the shield is driven by the output of a unity-
gain buffer. [23]
√ (6-12)
Capacitive sensing interface
Charge
Switched-capacitor charge amplifier (SC)
Voltage
unity-gain buffer
chopping amplifier with capacitive
feedback
open-loop differential chopper
amplifier
Current
transimpedance amplifiers (TIA)
Trans-capacitance amplifier (TCA)
[48]
where Vn-rms is the input-referred thermal noise floor of the amplifier and BW is the capacitance
detection bandwidth
6.1.5.1.2. Chopper amplifier with capacitive feedback
Chopper amplifier converts low level signal or frequency into high level frequency
Figure 6-5 - Chopper amplifier with capacitive feedback
the output voltage is given by:
(6-13)
Since an AC virtual ground is provided at the sensing node in this configuration, the sensed
signal is parasitic capacitance-insensitive. It also offers accurate gain and good linearity.
However, the SNR is still deteriorated by Cp, because the noise transfer function from the input
to output is affected by Cp. In pure CMOS MEMS inertial sensors that have small sensing
capacitance C0, a chopping clock with a relatively high frequency is needed to effectively reduce
the flicker noise. The high gain-bandwidth requirement of the amplifier in this feedback
configuration results in a limit on the minimum achievable power consumption.
6.1.5.1.3. Open-loop differential chopper amplifier
Figure 6-6 - Open-loop differential chopper amplifier
the sensed signal is sensitive to the parasitic capacitance Cp at the sensing nodes that’s why the
open-loop architecture is undesirable if a large varying Cp exists at the sensing node.
In the case that Cp is stable and with a value comparable to or smaller than the sensing
capacitance C0 (since wiring from sensing elements to the inputs of readout circuits is provided
by metal layers in CMOS-MEMS process). So, the SNR attenuation introduced by Cp is relatively
[49]
small in these technologies. The topology has the potential to achieve both low power
consumption and low noise, since high gain-bandwidth product requirement is not needed in
open-loop amplifier, and high chopper frequency is achievable to effectively remove 1/f noise
without consuming too much power. Some disadvantages exist in this configuration, such as gain
inaccuracy, distortion with large input signals, and sensitivity to process variations and
temperature drift. [24]
6.1.5.2. Continuous-Time Current Sensing
6.1.5.2.1. Trans-impedance amplifier
Figure 6-7 - Trans-impedance amplifier
The circuit output is given by:
(6-14)
For capacitive sensing, the transimpedance amplifier is a differentiator that has a high-pass
frequency response. This architecture provides virtual ground and robust dc biasing at the
sensing node in continuous-time. However, the noise performance of this topology is inferior to
other topologies, since the white noise of the amplifier at high frequencies will be amplified by
the amplifier, due to its high-pass transfer function, also the pole associated with Rf limits the
bandwidth, also The noise performance is typically dominated by the thermal noise of the
feedback resistor as the amplifier noise is minimized. [23]
√
√
(6-15)
where GBWamp is the amplifier gain bandwidth.
[50]
6.1.5.2.2. Trans-capacitance amplifier
Figure 6-8 - Trans-capacitance amplifier
(6-16)
Low power consumption is achievable since the circuit amplifies signal at the baseband and the
gain-bandwidth product of the amplifier is not high. However, flicker noise will be a serious
problem in pure CMOS processes, since the readout circuit works only in the baseband. [17]
6.1.5.3. Discrete-Time Charge Sensing
The capacitive sensing is based on charge-voltage relationship, the same foundation on which
the SC circuit operates.
Thus, the capacitive sensor can be integrated very well with the SC interface circuits. The SC
circuit provides a virtual ground and robust dc biasing at the sensing node so that the sensed
signal is insensitive to parasitic capacitance and undesirable charging. The SC circuit also offers a
wide range of techniques to suppress offset and low-frequency noise, such as correlated double
sampling (CDS) [25]
In charge sensing, the capacitance change is converted to charge redistribution, which can be
readout with discrete-time switched-capacitor (SC) circuits. Correlated double sampling (CDS)
technique is widely used in SC circuits to cancel 1/f noise of the amplifier.
Based on where to store the sampled offset and 1/f noise voltage in CDS, there are two different
SC charge integration amplifier configurations:
(a) SC amplifiers with input offset storage (IOS)
[51]
during Φ1, the charges on sensing capacitors are reset to zero and the circuit offset (and low
frequency 1/f noise) is stored on Cos. During Φ2, the circuit offset is subtracted and the sensed
signal is amplified. In this configuration, the thermal noise from switching is determined by
kT/C0 , and a relatively large C0 is needed to reduce this noise component. Therefore, SC
amplifiers with IOS are only used in MEMS gyroscopes where large C0 is achievable.
(b) SC amplifiers with output offset storage (OOS)
the dc level of the charge integration amplifier is set during t1, and the circuit offset (and 1/f
noise) is stored into CHduring t2. During t3, the offset is cancelled and the signal is amplified. In
this configuration, the thermal noise from switching is determined by kT/CH. Since CHcan be
made relatively large, so the kT/C noise is effectively reduced, and also a small C0is allowed. A
drawback of this topology is that a preamp is needed after the charge-integration amplifier, so it
dissipates more power than the topology previously mentioned
In both SC charge integration circuits, the output signal is given by:
(6-17)
The SC readout circuits have good robustness, accurate gain and good linearity. but, the 1/f
noise is reduced at the cost of folding back all the thermal noise of the amplifier back into the
baseband. Therefore,its noise performance is worse than the continuous-time voltage sensing
circuits.
[52]
6.1.6. Comparison of Different Capacitive Sensing Architectures
By challenging the mentioned above topologies we can figure out the following [25]
SC CTC CTV
Pro
s
Provides virtual ground so, Insensitive to parasitic caps
Key advantage of the TIA architecture is that it provides a virtual ground in continuous-time so that the sensed signal (but not the noise) is insensitive to parasitic capacitance.
The open-loop CT voltage sensing architecture not only has good noise performance but also requires much smaller bandwidth than the other architectures, which implies savings in power and area.
Simplify the overall system designs (no need for sample and hold circuits)
con
s
Worse noise performance due to added thermal noise of switches
With the feedback resistor also adding noise, the CT current sensing also has worse noise performance than the CT voltage sensing
Requires DC bias through MOSFET Resistors
it is a sampled-data system and a SC front-end prohibits any anti-aliasing filter to be used prior to sampling severe noise folding causes the output noise power to multiply
The transimpedance amplifier is inherently a differentiator and has high-pass frequency response. The high-frequency noises are amplified by the TIA and folded into the signal band.
the open-loop architecture is undesirable when there exists a large varying parasitic capacitance open-loop continuous-time voltage readout has been considered the least robust
[53]
6.2. Analog / Digital converter
6.2.1. Introduction
Analog-to-digital conversion is everywhere around us. In all forms of electronic equipment the
analog-to-digital converter links our physical world to digital computing machines. This
development has enabled all the marvelous functionality that has been introduced over the last
thirty years, from mobile phone to internet, from medical imaging machines to hand-held
television.
Pure analog electronics circuits can do a lot of signal processing in a cheap and well-established
way. Many signal processing functions are so simple that analog processing serves the needs
(audio amplification, filtering). In more complex situations, analog processing however lacks
required functionality. There digital signal processing offers crucial extensions of this
functionality. The most important advantages of digital processing over analog processing are a
perfect storage of digitized signals, unlimited signal-to-noise ratio, the option to carry out
complex calculations, and the possibility to adapt the algorithm of the calculation to changing
circumstances. If an application wants to use these advantages, analog signals have to be
converted with high quality into a digital format in an early stage of the processing chain. And at
the end of the digital processing the conversion has to be carried out in the reverse direction.
The digital-to-analog translates the outcome of the signal processing into signals that can be
rendered as a picture or sound. This makes analog-to-digital conversion a crucial element in the
chain between our world of physical quantities and the rapidly increasing power of digital signal
processing. Figure 6-9 shows the analog-to-digital converter (abbreviated A/D-converter or
ADC) as the crucial element in a system with combined analog and digital functionality [26].
Figure 6-9 the analog to digital & digital to analog converters are the ears and eyes of a digital system
6.2.2. General Specifications
In this section, some commonly used terms describing the performance of data converters are
defined. Before proceeding, definitions are required for determining the transfer responses of
both D/A and A/D converters.
[54]
Figure 6-10 ideal characteristics of D/A
Figure 6-11 ideal characteristics of A/D
6.2.2.1. Resolution
The resolution of a converter is defined to be the number of distinct analog levels corresponding
to the different digital words. Thus, an -bit resolution implies that the converter can resolve
distinct analog levels. Resolution is not necessarily an indication of the accuracy of the converter,
but instead it usually refers to the number of digital input or output bits [27].
6.2.2.2. Offset and Gain Error
In a D/A converter, the offset error is defined to be the output that occurs for the input code that
should produce zero output
Where the offset error is in units of LSBs, Similarly, for an A/D converter, the offset error is
defined as the deviation of V000 from 1 ⁄ 2 LSB
Figure 6-12 Definition of offset error
The gain error is defined to be the difference at the full-scale value between the ideal and actual
curves when the offset error has been reduced to zero [27].
[55]
Figure 6-13 definition of gain error
6.2.2.3. Integral Nonlinearity (INL) Error
After both the offset and gain errors have been removed, the integral nonlinearity (INL) error is
defined to be the deviation from a straight line. However, what straight line should be used? A
conservative measure of nonlinearity is to use the endpoints of the converter’s transfer response
to define the straight line. An alternative definition is to find the best-fit straight line such that
the maximum difference (or perhaps the mean squared error) is minimized. These two
definitions are illustrated in Fig. 6. One should be aware that the INL values can be for each
digital word (and thus these values can be plotted for a single converter), whereas others
sometimes define the term “INL” as the maximum magnitude of the INL values (or equivalently,
as the relative accuracy). Typically INL is measured by slowly sweeping the converter input over
its full-scale range; hence it is a measure of the converter’s accuracy only at low input signal
frequencies [27].
Figure 6-14 integral nonlinearity error
6.2.2.4. Differential Nonlinearity (DNL) Error
In an ideal converter, each analog step size is equal to 1 LSB. In other words, in a D/A converter,
each output level is 1 LSB from adjacent levels, whereas in an A/D, the transition values are
precisely 1 LSB apart. Differential nonlinearity (DNL) is defined as the variation in analog step
sizes away from 1 LSB (typically, once gain and offset errors have been removed). Thus, an ideal
converter has its maximum differential nonlinearity of 0 for all digital values, whereas a
[56]
converter with a maximum differential nonlinearity of 0.5 LSB has its step sizes varying from 0.5
LSB to 1.5 LSB. Once again, as in the INL case, we define DNL values for each digital word,
whereas others sometimes refer to DNL as the maximum magnitude of the DNL values. Like INL,
DNL is a measure of dc or low-frequency accuracy. Hence, both are referred to as measures of
static nonlinearities [27].
Figure 6-15 Definition of differential linearity error
6.2.2.5. Monotonicity
A monotonic D/A converter is one in which the output always increases as the input increases.
In other words, the slope of the D/A converter’s transfer response is of only one sign. If the
maximum DNL error is less than 1 LSB, then a D/A converter is guaranteed to be monotonic.
However, many monotonic converters may have a maximum DNL greater than 1 LSB. Similarly,
a converter is guaranteed to be monotonic if the maximum INL is less than 0.5 LSB [27].
6.2.2.6. Missing Codes
Although monotonicity is appropriate for D/A converters, the equivalent term for A/D
converters is missing codes. An A/D converter is guaranteed not to have any missing codes if the
maximum DNL error is less than 1 LSB or if the maximum INL error is less than 0.5 LSB [27].
6.2.2.7. A/D Conversion Time and Sampling Rate
In an A/D converter, the conversion time is the time taken for the converter to complete a single
measurement including acquisition time of the input signal. On the other hand, the maximum
sampling rate is the speed at which samples can be continuously converted and is typically the
inverse of the conversion time. However, one should be aware that some converters have a large
latency between the input and the output due to pipelining or multiplexing, yet they still
maintain a high sampling rate. For example, a pipelined 12-bit A/D converter may have a
conversion time of 2 ns (i.e., a sampling rate of 500 MHz) yet latency from input to output of 24
ns [27].
6.2.2.8. D/A Settling Time and Sampling Rate
In a D/A converter, the settling time is defined as the time it takes for the converter to settle to
within some specified amount of the final value (usually 0.5 LSB). The sampling rate is the rate at
which samples can be continuously converted and is typically the inverse of the settling time
[27].
6.2.2.9. A/D signal to quantization noise ratio (SNQR)
In ideal ADC There is a range of valid input values that produce the same digital output word.
This signal ambiguity produces what is known as quantization error.
[57]
Figure 6-16 Ideal A/D response to ramp signal & Quantization error of that A/D
If we assume that the input signal is varying rapidly such that the quantization error signal, VQ, is
a random variable uniformly distributed between ±VLSB ⁄ 2. The probability density function
for such an error signal, fQ(x), will be a constant value, as shown in Fig. 9
Figure 6-17 uniform distribution of quantization error
Assume Vin is a sinusoidal waveform between 0 and Vref. Thus, the ac power of the sinusoidal
wave is Vref ⁄ (2√ ), which results in
(
) (6-18)
(
( √ )⁄
(√ )
⁄) (6-19)
(√
) (6-20)
(6-21)
6.2.2.10. Dynamic Range
The dynamic range of a converter is the ratio of the maximum to minimum signal amplitudes. A
popular metric quantifying dynamic range is the maximum achievable signal-to-noise and
distortion ratio (SNDR) specified as the ratio of the rms value of an input sinusoidal signal to the
rms output noise plus the distortion measured when that same sinusoid is present at the output
[27].
Dynamic range can also be expressed as an effective number of bits (Neff) by computing the
resolution of an ideal.
(6-22)
[58]
6.2.3. Analog to Digital converters
The analog-to digital (A/D) interface converts a continuous –amplitude, continuous-time input
to discrete-amplitude, discrete-time signal. Shown in Fig. 10 is the A/D in more detail. Frist the
analog low-pass filter limit the signal bandwidth so that subsequent sampling dose not alias any
unwanted noise or signal component into actual signal band. Next o/p of filter is sampled so as
to produce a discrete-time signal. The amplitude of this waveform is then “quantized” i.e.,
approximated with a level from a set of fixed references, thus generating a discrete-amplitude
signal. Finally, a digital representation of that level is established at the output [28].
Figure 6-18 Detailed analog to digital converter interface
6.2.3.1. Architectures
Figure 6-19 different architectures of ADC
Here is a figure of different architectures of ADC & some points of comparison that can help us
select appropriate topology for our gyroscope. According to what we said in the challenges of the
capacitive sensing we need a highly accurate, low speed (as gyroscope is a mechanical structure)
from table 2.1 u can see that sigma delta ADC is the perfect choice. But cant SAR & pipeline be
used? Actually the sigma delta ADC has much better noise performance than other two this is
because of oversampling + noise shaping that can be done. Additionally, oversampling relaxes
the implementation of lowpass filter (antialiasing filter). For these reasons, we think that the
sigma-delta ADC is the best choice for this circuit.
[59]
6.2.3.1.1. Sigma delta converters
The system architecture of a ΔΣ oversampling A/D converter is shown in Fig. 12. The first stage
is a continuous-time anti-aliasing filter and is required to band-limit the input signal to
frequencies less than one-half the oversampling frequency Fs. When the oversampling ratio is
large, the anti-aliasing filter can often be quite simple, such as a simple RC low-pass filter, in
some cases it might be implemented using parasitics of circuit. Following the anti-aliasing filter,
the continuous-time signal, Xc(t), is sampled by a sample and hold. This signal is then processed
by the ΔΣ modulator, which converts the analog signal into a noise-shaped low-resolution digital
signal. The third block in the system is a decimator. It converts the oversampled low-resolution
digital signal into a high-resolution digital signal at a lower sampling rate usually equal to twice
the frequency of the desired bandwidth of the input signal. The decimation filter can be
conceptually thought of as a low-pass filter followed by a down sampler, although in many
systems the decimation is performed in a number of stages. It should be mentioned that in many
realizations where the ΔΣ modulator is realized using switched-capacitor circuitry, a separate
sample-and-hold is not required, as the continuous-time signal is inherently sampled by the
switches and input capacitors of the SC ΔΣ [27].
Figure 6-20 Block diagram of an oversampling A/D converter
Oversampling Quantization with a step size LSB can be modeled as an additive quantization noise distributed
between –LSB/2 and +LSB/2 with a white power spectrum and total power of LSB2/12
The spectral density height is calculated by noting that the total noise power is
and, with a
two-sided definition of power, equals the area under Se(f) within ±fs ⁄ 2, or mathematically
∫ ∫
=
(6-23)
(
√ )√
(6-24)
[60]
Oversampling occurs when the signals of interest are band limited to F0 yet the sample rate is at
Fs, Where Fs > 2F0. We define the oversampling ratio, OSR, as
(6-25)
Then if the signal is oversampled then pass through brick-wall filter to remove much of the
quantization noise as shown in the figure below
Figure 6-21 (a) A possible oversampling system without noise shaping. (b) The brick-wall response of the filter to remove much of the quantization noise.
The power of the input signal within y2(n) remains the same as before since we assumed the
signal’s frequency content is below . However, the quantization noise power is reduced to
∫
| | ∫
(
) (6-26)
Therefore, doubling OSR (i.e., sampling at twice the rate) decreases the quantization noise
power by one-half or, equivalently, 3 dB
We can also calculate the maximum SQNR to be the ratio of the maximum sinusoidal power to
the quantization noise power in the signal to be
(
) (
) (6-27)
This is also equal
= 6.02N + 1.76 + (6-28)
Here we see that straight oversampling gives a SQNR improvement of 3 dB/octave or,
equivalently, 0.5 bits/octave. This done Without Noise shaping
Noise shaping Using the noise shaping technique the SQNR is increased. This is done through feedback
structure shown in Figure below; this feedback reduces the effect of the noise of the output stage
of the opamp in the closed loop amplifier’s output signal at low frequencies when the opamp
gain is high. At high frequencies, when the opamp’s gain is low, the noise is not reduced.
[61]
Figure 6-22 A modulator and its linear model: (a) a general delta-sigma (interpolator structure) ; (b) linear model of the modulator showing injected quantization noise
From figure 18.6 we can derive a signal transfer function, STF(z) , and a noise transfer function
NTF(z) is
(6-29)
(6-30)
Using
(first order noise shaping ) the noise is reduced in the band of interest as can
be seen in the figure this can be explained by the signal transfer function STF(z) and the noise
transfer function NTF(z)
⁄
⁄ = (6-31)
⁄ (6-32)
You can notice that at DC (z=1) noise component is zero while the signal value don’t change the
when following equation it will lead u to the figure which show the shape of noise without noise
shaping , first order noise shaping , second order noise shaping
Figure 6-23 some different noise-shaping transfer functions
This a summary of the main differences in architecture and noise performance of nyquist,
oversampling without noise shaping &oversampling with noise shaping
[62]
Figure 6-24 oversampling, digital filtering, noise shaping and decimation
Sigma-Delta different architectures
a)1-bit sigma delta architecture
Figure 6-25 Frist-order A/D modulator: (a) block diagram; (b) switched-capacitor implementation.
The main advantage of this architecture is that it uses 1-bit DAC which is inherently linear. This
linearity is a result of a 1-bit D/A converter having only two output values and, since two points
define a straight line. The output from a 1-bit converter can be filtered to obtain the equivalent
of a 16-bit converter. If better noise performance (better resolution) is required higher order of
noise shaping can be used. For higher order modes Interpolative structure or multistage noise
shaping architectures can be used.
[63]
b)Bandpass Oversampling converters
Figure 6-26 A second order bandpass oversampling modulator that shapes the quantization noise away from fs/4
Signal is not always in the low pass band, it can be modulated by some higher-frequency carrier
signal. For such applications, one can make use of bandpass oversampling.
Simply if H(z) is changed to has high gain at carrier frequency instead of high gain at DC in the
lowpass oversampling converters. With such approach, the quantization noise is small around
carrier frequency For example if Fc=Fs/4 the H(z) will be equal
(6-33)
The difference between the lowpass & bandpass example Fc=Fs/4 is shown in the figure, where
is the double frequency of bandpass filter, FC is carrier frequency, FS is the sampling
frequency
Figure 6-27 Noise-transfer-function zeros for oversampling converters: (a) first-order lowpass; (b) second-order bandpass
c)Multi-bit structure
Figure 6-28 Multi-bit sigma delta structure
[64]
Although 1-bit oversampling converters have the advantage that they can realize highly linear
data conversion, they also have some disadvantages. 1-bit oversampling modulators are prone
to instability due to the high degree of nonlinearity in the feedback. Another disadvantage is the
existence of idle tones. The use of Multi-bit internal quantization improves stability and
therefore is often used in high order modulators with low OSR. But it need to combined some
linearity enhancement techniques for the feedback DAC
6.2.4. Decimation Filters
6.2.4.1. Decimation theory
Decimation is the processes of lowering the word rate of a digitally encoded signal, which is
sampled at high frequencies much above the Nyquist rate. It is usually carried out to increase the
resolution of an oversampled signal and to remove the out-of-band noise. In a sigma-delta ADC,
oversampling the analog input signal by the modulator alone does not lower the quantization
noise; the ADC should employ an averaging filter, which works as a decimator to remove the
noise and to achieve higher resolutions. A basic block diagrammatic representation of the
decimator is shown in figure below.
The decimator is a combination of a low pass filter and a down sampler. In Fig. 3 the transfer
function, H(z) is representative of performing both the operations. The output word rate of the
decimator is down sampled by the factor M, where M is the oversampling ratio. The function of
low pass filtering and down sampling can be carried out using an averaging circuit. The transfer
function of the averaging circuit is given by equation below:
(6-34)
The averaging circuit defined averages every M samples. By converting the z-domain transfer
function into the frequency domain the characteristics of the circuit can be plotted. The
frequency response of the decimator is given by equation below.
(6-35)
The plot of the frequency response of the filter is shown in Fig.
Figure 6-29 Basic diagram of the decimation filter
[65]
Figure 6-30 Frequency response of the Decimation filter
In order for the decimator to satisfy the digital low pass filter characteristics the attenuation in
the stop band should be high. The ratio of the main lobe to the side lobe forms a critical factor in
designing a decimator. The filter characteristics can be improved to have sharp transition
between the pass band and stop band and also good attenuation in the stop band by cascading
the decimation stages. The gain of the filter is given by the value M. Increasing the value M
simply means increasing the final output resolution. The decimator averages every M samples
and has an output at every Mth sample. The output rate of the decimator is
. The input to a
decimator is the sequence of bits of 1’s and 0’s and since the averaging operation involves the
addition of these bits, the output resolution increases due to the addition of every M number of
bits. As the M value increases the output resolution also increases.
The decimator is designed to be cascaded with sigma-delta ADC. The filters order depends on
the ADC order according to the following equation if the order of the ADC is one then the order
of the filter is two
(6-36)
Where K is the filter’s order, and M is the ADC order. The complete transfer function of the
decimator is:
(6-37)
6.2.4.1.1. Cascaded Integrated Comb filters
The CIC filter is a combination of digital integrator and digital differentiator stages, which
perform the operation of digital low pass filtering and decimation. The CIC filters do not require
any multiplier circuits and hence are very economical for implementation in hardware. Equation
below gives the transfer function of the CIC filter in z-domain, which is similar to equation of
decimators except the numerator term, and the denominator terms are separated. The
numerator represents the transfer function of a differentiator and the denominator indicates
that of an integrator.
(6-38)
[66]
The CIC filter first performs the averaging operation then follows it with the decimation
operation. A simple block diagram of a first order CIC filter is shown in Figure below.
Figure 6-31 Simple First order CIC filter
The hardware needed to implement the CIC filter shown is very significant because of the delay
elements that are used in the differentiator stage. It can be seen that the differentiator circuit
needs M delay elements. Usually the delays are implemented using registers. As the
oversampling ratio increases, the number of delay elements also increases and as well the
number of register bits that are used to store the data.
It is better to implement the decimation filter in a multistage as long as the oversampling factor,
M, is not prime. The more prime factors M have, the more choices you have to implement the
Filter. [29]
The integrator The integrator circuit is similar to an accumulator, which is used to accumulate, or storethe
sum of the input data. . It is Infinite Impulse Response (IIR) filter with a filter coefficient factor of
one. The transfer function of the integrator is shown in equation below
(6-39)
The transfer function for an integrator on the z- plane is
(6-40)
The output of the integrator is the sum of the present input and the past output as can be
observed from the time domain. A diagram representation of the digital integrator can be
modeled and is shown in the following figure. [30]
Figure 6-32 Basic integrator
[67]
The differentiator A differentiator circuit also called as a comb filter is a Finite Impulse Response (FIR) filter. A
comb filter is a digital low pass filter. The time domain and the transfer function of the
differentiator are given in equation below, From the time domain representation it can be
explained that the output of the differentiator is the difference between the present input and
the past input.
(6-41)
(6-42)
Figure 6-33 Basic differentiator
The transfer function is converted into the frequency response and the expression for the
magnitude response is given by equation below. The plot of magnitude response of the
differentiator is shown in Figure below. The two’s complement output of the integrator is
applied as the input to the differentiator, and so the differentiator also uses the two’s
complement scheme of coding. [30]
| | √ (
) (6-43)
Figure 6-34 Magnitude response of differentiator
Applications of CIC Filters The application for CIC filters seems to be in areas where higher sampling rates make
multipliers an uneconomical choice and areas where large rate change factors would require
large amounts of coefficient storage or fast impulse response generation.
6.2.4.1.2. Decimation filters overview
In this section we will compare different architectures of cascaded integrator combs (CIC) using
parameters like area and power consumption. In this comparison a second order sigma delta
modulator is used integrated with a third order decimation filter to form a sigma-delta ADC. [31]
[68]
IIR-FIR structure A simplified implementation of CIC filter is shown in Figure below. In this circuit, the IIR filters
work at fs and the FIR filter works at Nquist rate (fN ). To maintain accuracy the data word
length inside the IIR part must be m + k*log2N bits. Since N is usually very large (32, 64, etc.),
hence the IIR part has a long word length and has to operate at the very high oversampling
frequency fs. Therefore the IIR part limits the applicability of the recursive structure to very high frequency A/D converters. Meanwhile large power consumption is caused by the IIR part
since a lot of long word addition operations are performed at oversampling frequency. The
power consumption of FIR filters is low because it works at a frequency (
). [31]
Figure 6-35 IIR - FIR CIC
Non-recursive structure The transfer function of the comb decimation filter can be simplified as:
∑ ∑
∏ (6-44)
This decimation filter can be realized using a cascade of log2 N FIR filters. This structure is called
’non-recursive structure’ because there are only FIR filters needed for implementation while in
IIR-FIR structure is a recursive one due to IIR filters. So there are no stability related issues in
non-recursive structure. The wordlength increases by k bit through every stage while the
sampling rate decreases by a factor of 2 starting from fs. Reducing sampling rate in the earlier
stages helps to reduce the power consumption. In spite of decreasing the frequency in each stage
by two, half the output is used and the filters works twice as we need. [31]
Figure 6-36 Block diagram for non-recursive decimator
Polyphase structure In the non-recursive structure the output is decimated by factor 2, implies that half of the output
is not used. This leads to waste of computational resources and increased power consumption.
By applying polyphase decomposition we can get a more efficient implementation. Each FIR
filter in non-recursive structure can be implemented by 2- component polyphase decomposition
of its transfer function.
( )
(6-45)
[69]
Figure 6-37 Polyphase decimation filter
This structure allows the placement of the downsamplers at the input of the filter, making the
whole structure work at half the frequency it used to work in non-recursive structure at the cost
of increased circuitry. [31]
Results and comparisons:
A-Area
We can see below that the area is least in case of IIR-FIR structure, increases with non- recursive
structure and the highest in polyphase structure for the same oversampling ratio. IIR-FIR
structure has minimum area for a given oversampling ratio and the increase in the area with
oversampling ratio is minimum compared to other structures. Moreover the increase in area
with oversampling ratio remains the same.
Figure 6-38 Areas of different decimation filters types
Table 2 Comparison between different architectures of decimation filters in area
Oversampling ratio IIR-FIR Non-recursive Polyphase
64 6648 12951 19080
128 7635 16555 24807 256 8591 20638 31077
B-Power consumption
From the comparison shown in Fig. 6, Polyphase structure has the minimum power
consumption followed by non-recursive structure and worst in case of IIR-FIR structure. The
increase in power consumption between two consecutive oversampling ratios for IIR-FIR
structure is linear. Polyphase structure has the least power consumption of all other structures.
The advantage of this structure increase in power consumption between two adjacent
oversampling ratios is less than that of non-recursive structure for the same oversampling
[70]
ratios. This is due to downsampling occurs first followed by filtering. So the downsampling
registers work with frequency of the block while the filter registers work with half the
frequency. [31]
Figure 6-39 Power of different decimation structures
Table 3 Comparison between different architectures of decimation filter in power dissipation
Oversampling ratio IIR-FIR Non-recursive Polyphase
64 120.3 103.2 83.4
128 136.7 110.4 84.6 256 152.51 113.7 85.6
From these comparisons we can estimate which structure to use and this depends on the
application area and power consumption.
[71]
6.2.5. Digital to Analog Converters
The Digital to analog converters (D/A) usually interface at the back end of the system. It
converts a discrete-amplitude, discrete-time signal to a continuous-amplitude, continuous-time
output. D/A selects and produce an analog level from a set of fixed references according to the
digital input. If DAC generates large glitches during switching from one code to another then
deglitching circuit (usually sample and hold amplifier) follows to mask the glitches finally, since
the reconstruction function preformed y the DAC introduces sharp edge in the waveform as well
as sinc envelope in the frequency domain, an inverse sinc filter and lowpass filter are required to
suppress these effects [28].
Figure 6-40 Detailed digital analog converter
6.2.5.1. Architectures
Its seems clear to us that if the sigma-delta ADC converter is used then a sigma-delta DAC is used
at o/p as it will work on same clock, give us same noise performance and will let u use linear 1
bit DAC but here we will show all the options we have including Nyquist architectures
6.2.5.1.1. Nyquist architectures
Nyquist-rate D/A converters can be roughly categorized into four main types: decoder-based,
binary-weighted, thermometer-code, and hybrid. These different topologies can be built using
voltage or charge or current based elements.
6.2.5.1.2. Binary-scaled D/A converters
It combines binary-weighted circuit quantities (currents, resistors, capacitors, etc.) under digital
control to realize an analog quantity. Such techniques are generally hardware-efficient, but can
be subject to significant nonlinearities
Figure 6-41 Voltage-mode binary-weighted resistor D/A
The voltage-mode binary-weighted resistor DAC shown in Figure 3.12 is usually the simplest
textbook example of a DAC. However, this DAC is not inherently monotonic and is actually quite
hard to manufacture successfully at high resolutions. In addition, the output impedance of the
voltage-mode binary DAC changes with the input code [32].
[72]
Figure 6-42 Current-mode binary-weighted DACs
Current-mode binary DACs are shown in Figure 23A (resistor-based), and Figure 23B (current-
source based). An N-bit DAC of this type consists of N weighted current sources (which may
simply be resistors and a voltage reference) in the ratio 1:2:4:8:....:2N–1. The LSB switches the 2N–
1 current, the MSB the 1 current, etc. The theory is simple but the practical problems of
manufacturing an IC of an economical size with current or resistor ratios of even 128:1 for an 8-
bit DAC are enormous, especially as they must have matched temperature coefficients. Also this
architecture is better than voltage mode as the o/p impedance don’t change with i/p code it is
exposed to some glitches that limit its operation at high speed [32].
Figure 6-43 Capacitive binary weighted DACs
Capacitive binary-weighted DAC is shown in Fig. 24 the basic idea here is to simply replace the
input capacitor of an SC gain amplifier by a programmable capacitor array (PCA) of binary-
weighted capacitors, as shown in Fig.24. As in the SC gain amplifier, the shown circuit is
insensitive to opamp input offset voltage, 1/f noise, and finite-amplifier gain. Also, an additional
sign bit can be realized by interchanging the clock phases (shown in parentheses) for the input
switches. It should be mentioned here that, as in the SC gain amplifier, carefully generated clock
waveforms are required to minimize the voltage dependency of clock feed-through, and a
deglitching capacitor should be used. Also, the digital codes should be changed only when the
input side of the capacitors is connected to ground, and thus the switching time is dependent on
the sign bit, which requires some extra digital complexity [27].
[73]
6.2.5.1.3. R-2R ladder D/A converters
It produces binary-weighted currents without the need for a complete array of binary-weighted
resistors. Instead, only 2:1 component ratios are needed, a significant savings for high-resolution
converters.
Figure 6-44 4-bit R-2R based D/A converter.
6.2.5.1.4. Thermometer-code converters
It employs an array of 2N – 1 unitary equally-sized signal quantities. A digital thermometer code
selects the appropriate number of these unitary signal quantities, summing them to produce the
analog output with guaranteed monotonicity and better static linearity than binary-weighted
converters [27]. This architecture also overcome glitches problem that limits operation at high
speed. Here is an example of architectures of this topology
Figure 6-45 Current sources Thermometer-cod inverters
6.2.5.1.5. Hybrid Converters
So far we have considered basic DAC architectures. When we are required to design a DAC with
a specific performance, it may well be that no single architecture is ideal. In such cases, two or
more DACs may be combined in a single higher resolution DAC to give the required
performance. These DACs may be of the same type or of different types and need not each have
the same resolution. For Example
Resistor–Capacitor Hybrid Converters It is possible to combine tapped resistor strings with switched-capacitor techniques in a number
of different ways. In one approach, an SC binary-weighted D/A converter have its capacitors
connected to adjacent nodes of a resistor-string D/A converter, as shown in Fig. 27. Here, the
top 7 bits determine which pair of voltages across a single resistor is passed on to the 8-bit
capacitor array. For example, if the top 7 bits are 0000001, then switches S1andS2 would be
[74]
closed, while the other Si switches would remain open. The capacitor array then performs an 8-
bit interpolation between the pair of voltages by connecting the capacitors associated with a 1 to
the higher voltage and the capacitors associated with a 0 to the lower voltage. This approach
gives guaranteed monotonicity, assuming the capacitor array is accurate to only 8 bits [27]. The
converter in has 15-bit monotonicity
Figure 6-46 Example of 15-bit Resistor-capacitor hybrid D/A converter
6.2.5.1.6. Oversampling architectures
The main example of the oversampling architecture is the sigma-delta DAC. Sigma-delta DACs
operate very similarly to sigma-delta ADCs, however in a sigma-delta DAC, the noise shaping
function is accomplished with a digital modulator rather than an analog one. A Σ-Δ DAC, unlike
the Σ-Δ ADC, is mostly digital (see Figure 3.147A). It consists of an "interpolation filter" (a digital
circuit which accepts data at a low rate, inserts zeros at a high rate, and then applies a digital
filter algorithm and outputs data at a high rate), a Σ-Δ modulator (which effectively acts as a low
pass filter to the signal but as a high pass filter to the quantization noise, and converts the
resulting data to a high speed bit stream), and a 1-bit DAC whose output switches between equal
positive and negative reference voltages. The output is filtered in an external analog LPF.
Because of the high oversampling frequency, the complexity of the LPF is much less than the
case of traditional Nyquist operation. The 1-bit & M-bit sigma-delta DAC architecture is shown
Fig. 28 [32].
[75]
Figure 6-47 Sigma-delta DACs
There is some constrains on analog filter for the sigma-delta modulator to work properly and for
the filter to eliminate noise. Filter must work on higher order than modulator order at least one
order greater, filter must also have sufficient dynamic range to accommodate both signal and
large quantization noise power at its input. If multibit is used linearity of M-bit DAC must be
ensured.
[76]
6.3. Demodulation block In the case of gyroscope the sensed signal is “double sided band – suppressed carrier” (DSB-SC)
which is one of the types of AM modulation. This type of demodulation is realized by a coherent
detection.
6.3.1. Coherent detection
If the frequency and phase of the carrier signal are known, then multiplying the output signals
by the carrier signal and then low-pass filtering gives the amplitude of the output signal. This
technique is similar to the Full Wave Rectification except that it only rectifies signals in phase
with the carrier, so it does not rectify out of band noise. The problem with this method, however,
is that it requires an accurate knowledge of the phase and frequency of the carrier signal; the
next figure shows the process of modulation and demodulation. [33]
Figure 6-48 Diagram shows the modulation and demodulation
In some cases it is better to measure the quadrature error and use it in recalibrating the
gyroscope device.
Digital demodulator consists of two main blocks, Digital multiplier and a Low pass filter. First we
will talk about different architectures of multipliers and then we will talk about different types
filters.
6.3.1.1. Digital multipliers
Binary multiplier is an electronic hardware used in digital electronics to perform rapid
multiplication of two numbers in binary representation. It’s building blocks are half adders and
full adders.
The rule for multiplication can be stated as follows
1. If the multiplier digit is a 1, the multiplicand is simply copied down and represents the
product.
2. If the multiplier digit is a 0, the product is also 0.
[77]
For designing a multiplier circuit we should have a circuitry to provide or do the following
things:
1. It should be capable identifying whether a bit is 0 or 1.
2. It should be capable of shifting left/right partial products.
3. It should be able to add all partial products to give the products as sum of partial
products. [34]
6.3.1.1.1. “Shift and Add” Multiplier
This type of multiplier needs an adder a shift register and a multiplexer. For example if we need
to multiply A (n-bit) and B (n-bit). A is the multiplicand, B is multiplier and P is the accumulator
with an initial value of zero. If the least significant bit of B equals to 1 then add A to P, if else add
zero to P. then the [P][B] is shift right by one. This procedures is repeated (n-1) times and then
the result product will be [P][B]. [35]
Figure 6-49 Shift and Add Multiplier
6.3.1.1.2. Carry Save Array Multiplier
The Carry-Save array multiplier is a straightforward implementation of vector multiplication. It
consists of a partial product reduction tree, which is used to calculate partial products in Carry-
Save redundant form, and a final chain adder to transform the redundant form in normal binary
form. A 4x4 Carry-Save multiplier is shown in figure below.
Figure 6-50 4x4 carry-save multiplier (left). Full adder (right)
[78]
We assume that X= (xn-1,…, x1, x0) and Y= (yn-1, …, y1, y0). The bits are fed into an array of Full
Adder cells. Each FA cell performs the multiplication using an AND gate and then adds the result
with the incoming carry bits, to produce an output sum and an output carry. All FA cells are
appropriately connected as shown in figure above, to perform the multiplication. The final adder
shown in figure 1 is used to merge the sums and carries from the last row of the array. We can
see that when Y1 is 0 then the corresponding diagonal cells are functioning unnecessarily. In all
these cells the partial products and the carry inputs are zero and this chain does not contribute
to the formation of the product. Consequently, the sum output of the above cell can bypass this
unimportant diagonal with the use of transmission gates. [36]
6.3.1.1.3. CSA with Bypassing Technique
The transmission gates in the FAB cell, shown in figure below, lock the inputs of the full adder to
prevent any transitions. When Y=0, and a multiplexer propagates the sum input to the sum
output. When Y=1, the sum output of the full adder is passed. The carry input does not generate
any new value since the initial diagonal carry input is always 0. So, no transmission gate is used
to block it. to fix any erroneous carry generated from previous computations, an AND gate is
used before the final adder to make the final diagonal carry output 0. The whole structure of the
modified multiplier is presented in figure below. [36]
Figure 6-51 4x4 Carry-save multiplier (left), FAB cell (right)
6.3.1.1.4. Wallace tree multiplier
Wallace tree is an efficient hardware implementation of a digital circuit that multiplies two
integers.
The Wallace tree has three steps:
Multiply (that is - AND) each bit of one of the arguments, by each bit of the other,
yielding results.
Reduce the number of partial products to two by layers of full and half adders.
Group the wires in two numbers, and add them with a conventional adder. [36]
[79]
Figure 6-52 Wallace tree
6.3.1.1.5. Mixed Architectures
The mixed architecture is nothing but the combination of Wallace tree and Array structure. The
great timing advantage of the Wallace tree along with the great power advantage of the bypass
scheme can be combined in a mixed architecture. The figure for mixed architecture is shown in
figure below.
Figure 6-53 16-bit multiplication split in parts
If the first 8 bit value is (A,B) and the second is (C,D), four 8 bit products are generated, X=AxD,
Y=BxD, Z=AxC and W=BxC. These four partial products shifted and added together generate the
final 16-bit multiplication. Z and X are performed by Wallace tree and the other is performed by
bypass array. By this technique we can benefit speed performance from Wallace tree and low
power dissipation from the bypass architecture. [36]
[80]
6.3.1.1.6. Results and Comparisons
When compared to other architectures, such as Wallace and normal multipliers, it is power
efficient.
Table 4 comparison between different multiplier topology
Multiplier Topology Bits Switching Power Dissipation
Critical Path Delay
Area Power Delay
Carry save Array Multiplier
8x8 4.11 22.34 124 91.81
Bypass 8x8 3.02 22 117 66.44 Wallace 8x8 3.13 24.68 132 77.24 Mixed Style Multiplier 8x8 3.31 19.8 135 65.53
Form this comparison we can determine which architecture we will use according to
specifications needed and the application of the gyroscope. [36]
6.3.1.2. Digital Filters
In this section we will discuss the different architectures of digital architectures and their pros
and cons, but before that we must know first the design methodology of any filter.
1. Filter specification.
Figure 6-54 Describes the most important filter specifications
To design a digital filter, first we must specify the stopband and cut-off frequency and the most
allowed ripples in the passband that the application can handle.
2. Coefficient calculation. There are several different methods available, the most popular are:
• Windowing (FIR)
• Parks and McClellan algorithm (FIR)
• Bilinear transform (IIR)
• Impulse invariant method (IIR)
(a)
1
f(norm)fc : cut-off frequency
pass-band stop-band
pass-band stop-bandtransition band
1
s
pass-bandripple
stop-bandripple
fpb : pass-band frequency
fsb : stop-band frequency
f(norm)
(b)
p1
s
p
0
-3
p1
fs/2
fc : cut-off frequency
fs/2
|H(f)|(dB)
|H(f)|(linear)
|H(f)|
[81]
3. Structure selection In any type of the two filters, there are different structures to realize the filter, and this depends
on the specification of memory and power consumption. [29]
There are two main types of digital filters:
A. Infinite impulse response filters (IIR).
B. Finite impulse response filters (FIR)
6.3.1.2.1. IIR filters
IIR digital filters are recursive systems that involve fewer design parameters, less memory
requirements, and lower computational complexity than finite impulse response (FIR) digital
filters. These are primary advantages of implementing IIR digital filters. If there is no
requirement for a linear-phase characteristic within the passband of a digital filter, the
advantages make IIR filters more attractive to a system designer. This type of recursive system
belongs to an important class of linear time- invariant discrete-time systems characterized by
the general linear constant-coefficient difference equation as follows:
∑ ∑
(6-46)
Transforming this difference equation into the z-domain by means of the z-transform, such a
class of linear time-invariant discrete-time systems is also characterized by the transfer function
as follows:
∑
∑
(6-47)
Different structures of IIR filters are described by the difference equation in Equation above.
These structures are referred to as direct-form realizations. It should be noted that although
these structures are different from one another by design, they are all functionally equivalent.
Two prominent direct-form realizations are the Direct-Form, the Direct-Form II and Cascade-
Form Structure. In terms of hardware implementation, the Direct-Form I structure requires
M+N+1 multiplications, M+N additions, and M+N+1 memory locations.
Figure 6-55 Direct form realization
[82]
The Direct-Form II structure requires less memory locations than the Direct- Form I structure.
Figure 6-56 Direct-form II realization
• Advantages:
Non-linear phase characteristics.
Low filter order (less complex circuits) for the same frequency response.
IIR filters allow zeros and poles, so it can be more selective for a given filter order.
• Disadvantages:
Resulting digital filter has the potential to become unstable ( Poles must be
inside unit circle |z|<1).
6.3.1.2.2. FIR Filters
FIR filters constitute a class of digital filters having a finite length impulse response. An FIR filter
can be realized using nonrecursive as well as recursive algorithms. However, the latter is not
recommended due to potential stability problems while nonrecursive FIR filters are always
stable. Hence, nonrecursive FIR filter algorithms are preferable for implementation. An FIR filter
can be described by the difference equation:
∑ (6-48)
A nonrecursive FIR filter can be realized using many different structures. Here, only two FIR
filter structures are considered; the direct form and the transposed direct form.
Direct Form FIR Filter Structure The direct form FIR filter structure, shown in Figure below, is easily derived from the first
Equation. An Nth-order direct form structure is composed by N memory elements (registers)
holding the input value for N sample periods, N+1 multipliers and N additions for adding the
results of the multiplications.
[83]
Figure 6-57 Nth-order direct form
Transposed Direct Form FIR Filter Structure The transposed direct form FIR filter structure, shown in Figure below, is derived from the
direct form structure using the transposition theorem. This theorem states that by interchanging
the input and the output and reverse all signal flows in a signal-flow graph of a single input
single output (SISO) system, such as the direct form FIR filter, the transfer function of the filter
remains unchanged.
Figure 6-58 Nth-order transposed direct for FIR filter
Linear-Phase FIR Filter Structures A property of FIR filters is that they can be implemented with an exact linear phase response. To
obtain this, the FIR filter must have a symmetric impulse response. The impulse response of a
linear phase FIR filter is either symmetric around n = N/2. Where N is the filter order. For a
linear-phase FIR filter the number of multiplications required can be reduced by exploiting the
symmetry of the impulse response, as shown as in Figure below. From the figure it can also be
seen that the number of additions remains the same while the number of multiplications is
halved, compared to the corresponding direct form implementation.
Figure 6-59 Linear phase FIR filter structure
[84]
• Advantages: Linear phase characteristics.
BIBO stable (all input and outputs are bounded).
• Disadvantages:
Need a various number of memory places.
Multipliers consume more power dissipation.
From the previous Advantages and disadvantages of FIR and IIR filters, we can use the most
optimum one for the LPF and the decimation filter, and this also depend on the accuracy of the
device. [37]
[85]
6.4. Frequency synthesizer (PLL)
6.4.1. Theory of PLL
PLL is a negative feedback system that compares the output phase with the input phase and produces the output frequency which is proportional to the input phase difference. The main application of PLL is to produce a frequency that doesn’t change with time by controlling the VCO:
o Stable output frequency is obtained using a reference source (crystal) running at
a low frequency
o Important building block is the phase detector
Figure 6-60 shows the basic block diagram of PLL.
Figure 6-60 Basic PLL Block diagram
A phase detector is a circuit whose average output voltage is proportional to the phase difference ∆ϕ, between two inputs. In the ideal case relation between average output voltage and input phase difference is linear, crossing the origin for ∆ϕ=0 as shown in Figure 6-61.
Figure 6-61 Phase detector characteristics
The slope of the straight line is called gain of PD and expressed in V/rad.
The output of PD is then passed through a low pass filter, so as to remove the high
frequency content in PD output voltage. This is required because; the control voltage of
oscillator must remain quit in steady state. This filtered control voltage is then applied
to the input of Voltage Controlled Oscillator. Control voltage forces the VCO to change
the frequency in the direction that reduces the difference between input frequency and
output frequency. If two frequencies are sufficiently close, the PLL feedback mechanism
[86]
forces the two PD input frequency frequencies to be equal and the VCO is locked with
incoming frequency. This is called as locked state of PLL.
Figure 6-62 shows the basic operation of PLL.
Figure 6-62 Operation of PLL
Once the loop is in locked state, there will be small phase difference between the two PD
input phase signals. This phase difference results in a dc voltage at the phase detector
output which is required to shift the VCO from its free running frequency to input
frequency and keeps the loop in locked state.
Model of simple PLL
A linear model of PLL [38] can be constructed mathematically by considering Figure
6-63, which shows the linear model of type I PLL. Low pass filter is assumed to be of first
order for simplicity.
Figure 6-63 Linear model of type I PLL
The overall PLL model consists of the phase sub tractor, the LPF transfer function 1/(1+
s/ ) , where is the 3 dB bandwidth and the VCO transfer function KVCO/s. Here
Φin and Φout are the excess phases of input and output waveforms, respectively.
[87]
The open loop transfer function is given by equation 6-49:
|
|
=
-
The closed loop transfer function can be obtained as:
|
-
Since the frequency and phase are related by a linear operator, the transfer function of
6-51 can be expressed as:
-
Using the control theory approach the natural frequency and damping ratio are given
by:
√ -
√
-
The step response is given by:
[
√
( √ )] 6-54
Using control theory approach, we can say that, the step response will contain a
sinusoidal component with frequency √ that will decay with time constant
( )-1
From the above equations, we conclude the following:
Using equations (6-52) and (6-53), yields,
-
[88]
1. This result shows the critical tradeoff between settling speed and ripple on the VCO
control line. If we reduce the cutoff frequency of filter, spurs (greater high frequency
components) at the output of VCO are suppressed but settling time increases.
2. is an important factor, if ζ is less than typically 0.5, step response exhibits high
amplitude oscillations before settling. Hence in order to avoid this ringing, the value of
damping ratio is normally kept 0.707 or greater than or equal to 1.
3. Equation (6-53) shows that both phase error and ζ are inversely proportional to KPD
and KVCO. Hence lowering the phase error makes the system less stable. Thus this
simple PLL (type I) has a drawback of trade off between the settling time, the ripple on
the control voltage, the phase error and the stability.
6.4.2. Terminology of PLL
Lock range:
The range of input signal frequencies over which the loop can maintain the lock is called
as Lock Range or Tracking Range of PLL
Capture range:
The range of input signal frequencies over which PLL can acquire a lock is called as
Capture Range or Acquisition Range of PLL.
Pull in time:
The total time taken by the PLL to capture the signal (or to establish the lock) is called as
Pull in Time of PLL. It is also called as Acquisition Time of PLL.
Band width of PLL
Bandwidth is the frequency at which the PLL begins to lose the lock with reference.
A high bandwidth PLL provides a fast lock time and tracks jitter on the reference clock
source, passing it through to the PLL output. A low bandwidth PLL filters out reference
clock jitter, but increases lock time.
6.4.3. Types of PLL
These different architectures of PLL can be considered as different types of PLL.
Following types of PLL are classified according to their application.
Programmable PLL: This type of PLL can be programmed for wide range of signals.
Single and multi-phase PLL: These can control a single or many phases. They are used in
digital clock networks.
Digital Phase Locked Loop: They are used digital input signals for application like
Manchester coding.
[89]
PLL with lock detector: It uses a lock on one of the pins and is used in frequency
modulation.
PLL frequency synthesizer: These are used to synthesize the frequency of different range
and band.
Super PLL: It is used for frequency synthesizing of radios, networks of GSM, cordless
phones, etc.
6.4.4. Non Ideal Effects in PLL
Many imperfections always remain in practical PLL circuit. These lead to high ripple on
the control voltage even when the loop is locked. These ripples modulate the VCO
frequency, which results in non periodic waveform. This section will discuss non ideal
effects in PLL [39].
Jitter
A Jitter is temporal variations in clock edges at a given point on the chip, results in continuous clock period variation.. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly.
Common sources of jitter include:
o Intrinsic transistor noise. o Power supply variations o Noise coupling from a noisy digital circuit through the substrate. o Capacitive coupling from a high switching interconnect.
Phase noise
Phase noise is the ratio of the power in a 1Hz bandwidth a frequency fm away from the carrier, to the power in the carrier itself. (dBc/Hz) as shown in Figure 6-64
Figure 6-64 PSD of a signal-
The phase noise equation is given by:
(
)
[90]
Common sources of phase noise include:
o Oscillator noise
o Frequency divide noise
o Phase detector noise
Spur noise
Spurs are spurious emissions that occur from the carrier frequency at an offset equal to the channel spacing. These are usually caused by leakage and mismatch in charge pump of PLL. Reference spur mainly occurs in Charge Pump PLL. Though there is no phase difference between reference and feedback signal, in the locked state, the phase detector (or phase frequency detector) produces very narrow pulse width error voltage which drives the charge pump. Although these pulses have a very narrow width, the fact that they exist means that the dc voltage driving the VCO is modulated by a signal of frequency equal to input reference frequency. This produces reference spurs in the RF output occurring at offset frequencies. Now if is the input reference frequency, is loop bandwidth, is the frequency
of pole in loop filter and N is the division value then the amount of reference spur in PLL is given by:
(
√
) (
) [ ] -
If reference spur is not enough to meet the requirement, the loop bandwidth should be
further narrowed or charge pump current should be increased. It is also helpful to
reduce the division value to relax the charge pump design
6.4.5. Applications of PLL
PLL continues to find new applications in electronics and communication; examples
include memories, microprocessors, hard disk drive electronics, RF and wireless
transceivers, clock recovery circuits on microcontroller boards and optical fiber
receivers. Some of the applications are as follows .
Frequency multiplication and synthesis
A PLL can be modified such that it multiplies its input frequency by factor of M. Figure
6-65 shows basic frequency multiplication concept.
[91]
Figure 6-65 Frequency Multiplication
Skew reduction Since clock typically drives a large number of transistors and logic interconnects, it is
first applied to large buffer. Thus, the clock distributed on chip may suffer from
substantial skew.
Now consider the circuit as shown in Figure 6-66. Here input clock is applied to on
chip PLL and buffer is placed inside the loop. Since PLL guarantees a nominally zero
phase
Figure 6-66 Skew reduction
6.4.6. Limitations of Simple PLL architecture
For type I PLL there are always trade-offs between damping ratio of loop filter, loop
filter bandwidth and the phase error. Hence the performance of PLL cannot improve
beyond certain limit. Apart from this, a simple PLL suffers from a critical drawback i.e.
limited acquisition range [40].
Suppose when a PLL circuit is turned on, its oscillator operates at a frequency far from
the input frequency, i.e., the loop is not locked. Now PLL starts acquiring a lock. The
transition of the loop from unlocked to locked condition is very nonlinear process
because phase detector senses unequal frequency. Also for this kind of PLL, the
“acquisition range” is on the order of , that is, the loop locks only if the difference
between and is less than roughly . If is reduces to suppress the ripple
on control voltage, the acquisition range decreases. Even if the input frequency has a
precisely controlled value, a wide acquisition range is often necessary because the VCO
frequency may vary considerably with the process and temperature.
Hence in order to remove this problem, frequency detection is also incorporated in
addition to phase detection. The concept is such that let the two frequencies (reference
and VCO output frequency) be equal, once these two frequencies are equal, phases are
compared and VCO is tuned such that phases of reference and feedback waveform are
[92]
equal. Frequencies are compared using frequency detector which generates a dc voltage
equal to the difference of two input frequencies and drives the VCO such that = .
When | - | is sufficiently small, phase locked loop takes over, acquiring lock. Such
scheme increases the acquisition range to the tuning range of VCO.
6.4.7. Phase frequency detector
For the periodic signal it is possible to merge the phase and frequency detector, such
that it can detect both phase and frequency. It is called as phase-frequency detector
(PFD) and illustrated conceptually in Figure 6-67. Outputs QA and QB are called the “UP”
and “DOWN” pulses, respectively.
Figure 6-67 Concept of Phase Frequency Detector
Figure 6-68 shows the implementation of PFD. It consists of two edge triggered resettable
D flip-flops with their D inputs tied to logical ONE. Inputs A and B serve as clock of flip-
flops.
Figure 6-68 Implementation of PFD
If QA=QB=0 and A goes high, QA rises. If this event is followed by a rising transition on B,
QB also goes high and the AND gate resets both flip-flops. In other words, QA and QB are
simultaneously high for a short time but the difference between their average values still
[93]
represents the input phase or frequency difference correctly. Figure 6-69 shows the
operation of phase frequency detector.
Figure 6-69 PFD timing diagram It can be seen, that PFD effectively converts the input phase or frequency difference
information into the proportional UP and DOWN pulses. But, how to use this information
to generate a voltage which is used to the VCO? Since the difference between the average
values of QA and QB is of interest, the two outputs can be low pass filtered and sensed
differentially. However a more common approach is to interpose a “CHARGE PUMP”
between PFD and LPF.
6.4.8. The Charge Pump
A charge pump [41] is a three position electronic switch which is controlled by the three
states of PFD. When switch is set in UP or DOWN position, it delivers a pump voltage
±VP or a pump current ±IP to the loop filter. When both UP and DOWN of PFD are off.
i.e. N position, the switch is open, thus isolating the loop filter from the charge pump and
PFD. Figure 6-70 shows the basic charge pump.
Figure 6-70 Implementation of Basic Charge Pump
Figure 6-70 shows the combined architecture of the charge pump and loop filter.
Current sources and are identical. Two outputs of PFD QA and QB are given to
the UP and DOWN inputs of charge pump (CP) respectively. Capacitor Cp serves the
purpose of loop filter. Figure 6-71 shows the CP accompanied with PFD and loop filter.
[94]
Figure 6-71 PFD-CP-Loop Filter Combination
If QA=QB=0, then S1 and S2 are off and Vout (or Vcont) remains constant. If QA is high
and QB is low, then Iup (UP current) charges Cp. Conversely if QA is low and QB is high,
then Idn (DOWN current) discharges Cp. Hence, if suppose, A leads B, then QA continues
to produce pulses and Vcont rises steadily. Figure 6-72 shows the response of PFD-CP
combination [42].
Figure 6-72 Response of PFD-CP combination Basic Charge Pump
The basic PLL using charge pump PLL is discussed here. Figure 6-73 shows such
construction.
[95]
Figure 6-73 Simple Charge Pump PLL
The reference input is given to the one of the PFD while VCO output is given to another
input. This implementation senses the transition at the input and output detects phase
or frequency difference and activates the charge pump accordingly. When loop is turned
on, may be far , and the PFD and charge pump vary the control voltage such that
ωout approaches ωin. When input and output frequencies are sufficiently close, the PFD
operates as phase detector, performing phase lock.
Now consider a case, that Φout – Φin drops to zero. In this case PFD simply produce QA
= QB = 0. The charge pump thus remains idle and Cp sustains a constant control voltage.
But this does not mean that PFD and CP are no longer needed. If Vcont remains constant
for a long time, the VCO frequency and phase begin to drift. In particular, the VCO create
random variations in the oscillation frequency that can result in large accumulation of
phase error.
The PFD then detects the phase difference, produces corrective pulses on QA or QB that
adjusts the VCO frequency through charge pump and filter. Also, as phase comparison is
performed in every cycle, the VCO phase and frequency cannot drift substantially.
Since the open loop gain has two poles at origin, this topology is called as “type II” PLL.
The closed loop transfer function is given by:
6-58
This result is alarming, because closed loop system contains two imaginary poles and
therefore unstable. In order to stabilize the system, we add a zero in the loop gain by
adding a resistor Rp in series with the loop filter capacitor. This system is shown in
Figure 6-74 with additional capacitor C2 whose purpose will be explained later.
The closed loop system contains a zero at
.
[96]
But this compensated type PLL suffers from a drawback. Since the charge pump drives
the series combination of Rp and Cp, each time a current is injected into the loop filter,
the control voltage experiences a large jump. Even in the locked condition, mismatches
between Iup and Idown and the charge pump injection and clock feed through of S1 and S2
introduce voltage jump in Vcont.
Figure 6-74 Addition of and C2 to Improve Stability
The resulting ripple severely disturbs the VCO, corrupting the output phase. To solve
this problem, a second capacitor C2 is usually added in parallel with Rp and Cp,
suppressing the initial step. The loop filter is now of second order, yielding a PLL of type
III. Generally C2 if about one-fifth to one-tenth of Cp and does not affect the closed loop
time and frequency response. Figure 6-74 shows the third order PLL construction.
Limitations of basic CP architecture
There are some non ideal effects in basic CP-PLL, these limitations are discussed below.
1. Switches are constructed using PMOS and NMOS. The inherent mismatches between these two
switches results in mismatch in charging and discharging current in addition to timing
mismatch. Hence there is variation in control voltage at the output. In fact the W/L ratios are
adjusted so as to have equal UP and DOWN currents. however, mismatching takes place between
these currents. This means, since two current sources are themselves mismatched, the control
voltage experiences the random changes in it.
2. There is also problem of charge sharing between output node of CP (in fact between filter
capacitor) and the parasitic capacitances between drain and source of switch transistors. This
results in sudden change in control voltage which may disturb the VCO.
3. Another effect is clock feed through. The high frequency signal provided at the gate of switch
transistor passes to the output node via gate to drain parasitic capacitor Cgd. This also results in
jumps in control voltage. Since the VCO sensitivity is high, even a small jump in control voltage
results a large jump in output frequency.
[97]
4. Another effect is limited output voltage. If we want higher output voltage the current source
value must be increased. This is not possible in every condition, since that increases power
consumption also. In Figure 1-17, control voltage rises only up to some 550mV, but desired
value is around 632mV for 40MHz. Hence PLL fails to acquire the lock.
Figure 6-75 Implementation of Basic Charge Pump
To remove the non ideal effects in CP, so many different architectures are proposed. In practice
charge pumps are roughly classified into two categories. “Single ended charge pump” and
“Differential charge pump”.
Source CP Architecture
Figure 6-76 shows the source charge pump Invalid source specified.. The topology uses simple
current mirrors to generate charging and discharging current from two identical current
sources. Switches are placed at the source of current mirror MOS transistor.
Figure 6-76 Source Charge Pump
This architecture gives the faster switching time than other topologies in which switches are
implemented at the drain or gate terminals of the transistors; since the switch is connected to
single transistor with lower parasitic capacitance.
[98]
Advantages of Source CP:
1. Ripples in the control voltage in the locked state of PLL is drastically reduced.
2. Also CP builds enough voltage (632 mV in fact) to tune the VCO to the reference input
frequency.
3. Loop roughly locks into 4μs.
4. The power consumption is quite higher.
5. Minimize Mismatch in UP and DOWN currents.
Limitations of Source CP:
1. The simple current mirror used in this topology has low output impedance. To have
output current constant over a supply range the output impedance of current mirror
must be high.
2. If we want optimum output voltage across the CP as well as optimum pull in time of
PLL, the bias current requirement is also high required here.
3. Two current sources are required here, which add further power consumption,
because large number of transistors are required building a constant current source.
4. The mismatch between PMOS and NMOS is not fully removed. Also the clock feed
through effect is not minimized fully.
Considering all these limitations, in next section a new topology will be discussed in
order to have CP-PLL free of these limitations.
Transmission Gate CP Architecture
Many architectures were proposed to reduce the non ideal effects in charge pump. Transmission
gate charge pump PLL is one of such proposed topology. Following points were considered while
designing this topology.
1. If we derive both UP and DOWN current from same current source, the inherent
current mismatch can be minimized. This also removes requirement of two current
sources, hence also reduces power consumption.
2. Use of high output impedance current mirror, so that there is no variation in charging
and discharging currents.
3. If we use transmission gate switches instead of normal NMOS or PMOS switches,
switching time will increase as well as we can remove switching mismatch.
Figure 6-77 shows the Transmission Gate CP topology.
[99]
Figure 6-77 Transmission Gate Charge Pump (TGCP)
This topology tries to bring the advantages of differential charge pumps. The switches in
this circuit are implemented using transmission gates (TG) which are driven by
complementary clock signals. The usage of TG almost eliminates the clock feed through.
Both UP and DOWN currents are derived from same reference current source via
current mirrors. So, it can avoid the current mismatch caused by the case in which these
two currents are derived from two different sources. The high gain folded cascode
operational amplifier (OP Amp) is added to CP to make the voltage VREF at REF node, to
follow the voltage VC (voltage at output node or across capacitor) at the output of the CP
branch. In other words, OP Amp and Current mirror combination forms the regulated
input current mirror in which the VDS of current mirrors are forced to be the same,
which makes CP immune to channel length modulation effects.
Advantages of TG CP:
1. No ripple in the control voltage after loop is locked.
2. The pull in time is found to be lower than that of source CP-PLL.
3. Power consumption is found to be less than source CP-PLL.
4. Almost removes current mismatch between UP and DOWN current with lower
reference spur.
Limitations of TG CP:
1. Though the pull in time of PLL is improved (reduced, as it is primary requirement),
the power consumption has not reduced in that proportion (due to usage of OTA).
2. Further, design of OP Amp is itself tedious process. Hence if requirement of OP Amp
are not met, total circuit malfunctions.
3. This circuit consumes large area on silicon wafer since design of OP Amp needs
resistors and capacitors which are major area consumption elements in chip. A large by
pass capacitor used also consumes more area on chip.
[100]
4. The value of reference spur is higher than source CP reference spur. Hence we can say
that relative to source CP`s noise performance is poor.
6-5 Comparison of different CP Architectures
6.4.9. Voltage Controlled Oscillator
Voltage controlled oscillator is one of the important elements of PLL. An oscillator is an independent system that generates a periodic output without any input signal. A voltage-controlled oscillator is an electronic oscillator designed such that its oscillation frequency is controlled by a voltage input. .The frequency of oscillation is controlled by the applied DC voltage. The frequency of oscillation must be tunable for the phase of a PLL to be adjustable. Figure 6-78 shows the circuit diagram and Figure 6.79 shows the characteristics of VCO.
Figure 6-78 Current starved VCO
[101]
Figure 6-79 VCO characteristics
A CMOS ring oscillator shown in Figure 6-80 is an example of an oscillator, the frequency
of an inverter ring can be adjusted by controlling the supply (voltage or current) of the
inverters. The slope of frequency vs control signal curve at the oscillation frequency is
called voltage-to-frequency conversion gain. Ideally, for linear analysis to be applicable
over a large range of frequencies, the voltage gain of the VCO has to be relatively
constant.
Figure 6-80 Ring Oscillator
6.4.10. Frequency divider
For clock generation, mostly reference frequencies are limited by the maximum
frequency decided by a crystal frequency reference, (mostly in the range of 10 MHz),.
The divider‘s purpose is to scale down the frequency from the output of the voltage
controlled oscillator so that 16the system can operate at a higher frequency than the
reference signal Thus the VCO has to be designed such that the output of VCO is = N
times the reference frequency. So the output of the VCO is passed through a divide by N-
counter and feedback to the input.
The D flip flop based divider has been chosen for this particular application because of
practical reasons. Some phase locked loops also include a divider between the oscillator
and the feedback input to the phase detector to produce a frequency synthesizer.
A programmable divider is especially useful in radio and transmitter applications, as a
large number of transmit frequencies can be produced from a stable and accurate quartz
crystal–controlled reference oscillator.
[102]
6.4.11. Mixed PLL/DLL
Low-jitter clock generation [43] is required for reliable operation of high-speed synchronous designs such as microprocessors and data communication links. A clock signal sets the timing reference with respect to which computation and propagation of synchronous data occurs. Variations in this timing reference (i.e., clock jitter) requires designs to incorporate additional margins that degrade performance, we focus on two types of noise sources that can cause clock jitter in integrated clock generators – noise on the input reference clock and on-chip noise sources. In order to accommodate a wide range of noise conditions, a mixed PLL/DLL architecture that merges the characteristics of the two loops is used.
Overview on DLL
DLL is a first order feedback loop used in generating clock with zero phase error. It is
not used for clock multiplication as there is no VCO, and VCDL is used to control the
delay of the output and locks when the out signal lags the ref signal by multiple number
of clock cycle.
Figure 1-23 shows the DLL block diagram
Figure 1-24 shows how DLL operates
Figure 6-81 DLL Block diagram
[103]
Figure 6-82 Operation of DLL
Principle of operation
A block diagram of the MP/DLL architecture is presented in Figure 6-83. 1. It resembles the architecture presented in, which is a 500MHz clock frequency synthesizer that can be configured to operate either as a multiplying PLL or a multiplying DLL. The ability to switch between the two modes of operation is determined by whether the delay-elements are configured as a ring oscillator or a delay line via a multiplexer. The main difference between that design and the proposed MP/DLL is that the multiplexer has been replaced with an interpolator. Depending on the interpolation weight setting, the clock generator loop can operate with merged characteristics of both a PLL and a DLL.
Figure 6-83 Mixed PLL/DLL diagram
Configuration of the delay elements determines whether the loop acts like a PLL, a DLL, or a combination of the two, which are all possible through different settings of the interpolator. When w = 1, the clock edge, Φout, from the end of the delay chain feeds back around to the beginning. The input reference clock edge sees a weighting of 0 and, therefore, does not contribute any energy to the input of the chain. Hence, the delay elements are configured as a ring oscillator and the overall loop essentially operates like a PLL.When w = 0, the opposite case occurs. The signal at the end of the delay chain does not contribute any energy to the beginning. Instead, only the input reference clock edge, Φin, passes through. Hence,
[104]
the delay elements implement a delay line and the loop is a DLL. When 0 < w < 1,energy from both the input reference clock edge, Φin, and Φout feed into the input of the delay elements. Therefore, the resulting loop is a mixture of a PLL and DLL. It is important to point out one subtle aspect of the loop to clarify how it can operate either as a PLL or a DLL. In DLL mode, a rising transition at Φin exits the delay chain at Φout as a falling edge transition, but two passes through the delay chain are required to complete a full clock cycle. So, in order to share the PFD (that compares rising clock edges) for both PLL and DLL modes of operation, the interpolator must fully switch (i.e., w = 1) to pass the falling edge every half cycle when there is no clock multiplication. For clock multiplication, multiple consecutive edges recircultate through the delay line. The divider and control circuit (CTRL) coordinate this process. The CTRL block sends an enable signal to selection gates to pass the appropriate rising edges to the PFD and phase error detection is only done at the rising edge of every reference cycle.
[105]
6.5. Automatic Gain Control Loop (AGC)
Figure 6-84 AGC characteristics
The line A, B, C in Figure 6-84 represents a system that has no AGC applied. The output increases
linearly with the input signal until point B is reached, when some element in the signal chain
overloads and becomes non-linear. Generally from point B to C the output signal is distorted and,
unless the input signal is reduced, the system is unusable. The line A, D, E represents a system
that has AGC applied. The slope A, D is greater than unity and indicates that the AGC has gain
prior to the AGC detector. The transition from a linear to constant output at D is known as the
AGC ‘knee’ or threshold. From D to E the output level does not increase in response to an
increase in input signal. The alternate line D, F shows an AGC system whereby stronger signals
are allowed stronger output.
Figure 6-85 a) feedback b) feedforward
The role of the AGC circuit is to provide relatively constant output amplitude so that circuits
following the AGC circuit require less dynamic range. Automatic Gain control is best described as
the input signal VIN is amplified by a variable gain amplifier (VGA), whose gain is controlled by a
signal VC. In order to adjust the gain of the VGA to its optimal output level VOUT, the AGC
generally, first detects the strength level of the signal using the peak detector; it then compares
this level with a reference voltage VREF and finally, it filters and generates the required control
voltage.
This function can be performed by detecting the signal at the output of the VGA, so the
architecture is called “feedback” AGC (Figure 6-85a), or at the input, in which case it is identified
as “feedforward” AGC (Figure 6-85b)
[106]
One of the advantages of feedback AGC is that the dynamic range required at the detector input
is reduced in the same way the AGC gain range; on the other hand it may exhibit instabilities.
Feedforward AGC has faster response. However, the feedforward AGC is easily affected by mis-
adjustments between an envelope detector and a VGA, or by parameter variations in the circuit.
[44] high linearity loop and wide dynamic range input detector are required.
Other than classifying AGC as feedback and feedforward they can by classified whether
implemented analog or digital. The digital option is much simpler and commonly employs Digital
signal processor to control the programmable gain amplifier in a feedback loop. However, this
solution does not allow fast settling response. This problem is solved by using a digital solution
in feedforward loop.
Now we’ll be discussing different AGC structures
6.5.1. Design 1
This is a high-dynamic all-digital AGC, the circuit does not contain general purpose multipliers
and requires a rather small amount of memory. Moreover, various solutions are used to reduce
its complexity resulting in an efficient implementation. [45]
This is a feedforward design which is more robust and it does not involve the problem of
stability.
Figure 6-86 Architecture of digital AGC
The architecture of the proposed AGC circuit is shown in Figure 6-86. The samples of the input
signal, x(k), are represented by X-bit wide signed binary fractions taking the values from −1 to
1−2−(X−1). The output signal, y(k), is represented by Y-bit wide signed fractions with the values
from −1 to 1−2−(Y−1). Note that X>Y, for example X=23 and Y=12. Only some lower significant bits
in x(k) are occupied by the signal, depending on its amplitude. The AGC ensures that y(k)
contains the upper Y occupied bits of x(k), tracking its changes over time. It is accomplished by
using a digital VGA. In our case, its gain is determined by floating-point numbers with mantissa
m(k) and exponent e(k). They are obtained from the estimated peak amplitude of the absolute
value of x(k).
[107]
6.5.1.1. Envelop Detector
Figure 6-87 Continuous time envelop detector
To adapt continuous time envelop detector from Figure 6-87 to a digital detector a specific
analysis was made and found that [45]
The model in 6-59 can be digitaly implemented, for simplification K1 and K2 were approximated
by power of 2 values K1*=2_N1 and K2*=2-N2
These approximations allowed implementing multiplication in 6-59 as shifts of N1 and N2 bits.
Figure 6-88 Digital implementation of envelop detector
The input word of the envelope detector is G bits wide, including the sign bit. The output word is
P bits wide. Note that the width of the register, C, must be somewhat larger than P. Namely, after
register's output is shifted right by N2, at least the least significant bit of p(k) should remain
within c(k). Similar requirement arises from shifting g(k)−c(k). Therefore, the width of the
register should not be less than
[ ]
6-59
[ ]
6-60
[ ]
6-61
[108]
6-62
P and N2 in practice always take the values resulting in C>G. Therefore, g(k) is extended by C−G
LSB zeros, as shown in Figure 6-88.
g(k) and x(k) have the same word length, that is G=X. However, g(k), c(k) and p(k) are always
positive. Therefore, their most significant bits (MSBs) are always zero. [45]
6.5.1.2. Gain calculator
Figure 6-89a) shows the desired relationship between the peak amplitude of AGC's input signal
and the peak amplitude of the corresponding output signal. These amplitudes are denoted by A in
and Aout. Figure 6-89b) shows the gain, GAGC, needed to achieve this relationship. As shown in the
figures, for Ain<AT a constant gain of Gmax is used. For Ain≥AT, the output signal is forced to have
the peak-amplitude of Amax. [45]
Figure 6-89 a) relationship between peak Amplitude input signal and output signal b) AGC's Gain
As shown before the signal p(k) represents peak amplitude of AGC's input signal. Here, p(k) is
processed to obtain AGC's gain. The implementation of the gain calculator is shown in Figure
6-90. The gain is calculated from each sample of p(k). Note that only P−1 LSBs are used since
p(k) is always positive. First, the samples are converted to the floating-point format. Each
sample is loaded into the shift register SR which is then shifted left until the first bit equal to 1
arrives to the top of the register. The number of shifts is counted by the counter CNT to obtain
the exponent. If the sample being processed is less than AT, the shifting is stopped after G−T−1
shifts, resulting in the exponent of the AT, rather than the exponent of p(k). It is needed because
for Ain<AT the gain is calculated from AT rather than from Ain,
[109]
Figure 6-90 Digital implementation of Gain calculator
Figure 6-91 FSM of Gain calculator
After the shifting is finished, an M-bit mantissa is taken from the top of SR. in the process of
calculating gain approximations are made. The error obtained from them is tolerable. And it
simplifies the circuit significantly as it allows the gain to be found by processing the mantissa in
a look-up table and calculating the exponent as e+1.
First bit of mantissa is always equal 1 so a LUT of 2M-1 is sufficient. Gain calculator is controlled
by a FSM, it’s state diagram is shown in Figure 6-91. The output of the gain calculator is the
mantissa, m(k), and the exponent, e(k), of the AGC's gain. These signals are further processed in
the variable-gain amplifier.
[110]
6.5.1.3. Variable Gain Amplifier
Figure 6-92 Digital implementation of VGA
Figure 6-93 FSM of VGA
The implementation of the variable-gain amplifier is shown in Figure 6-92 . Each sample of the
input signal, x(k), is multiplied by the required gain, which is given by m(k) and e(k). First, x(k)
is multiplied by m(k) using addition and left shifting. The registers SR1 and SR2 are used for
shifting. The sum is stored in SR3. Before each shift of SR1 and SR2, the MSB in SR2 is tested. If it
is equal to 1, the content of SR1 is added to the content of SR3. This process finishes when SR2
contains only zeros. It is tested by an M-input OR gate. After the multiplication with the mantissa
is completed, the exponent is processed. The content of SR3 is shifted left by e(k) bits. According
to the values of Rise time and attack time, the amplifier output may clip. To handle this properly,
Two MSBs of SR3 are always checked during the processing of exponents, they should have
same value during shifting before it is completed. They are checked by an XOR gate. If they
posses different values the output is forced to maximum +ve/-ve value [45]. VGA is controlled by
FSM,IT’s state diagram is shown is Figure 6-93. The output of the variable-gain amplifier, y(k), is
also the output of the AGC circuit.
As a sum up for this design, it is useful for high dynamic systems. The design is based on
approximations that result in simple structures, ensuring efficient implementation.
[111]
6.5.2. Design 2 The principle of the digital AGC module is shown in Figure 6-94. Here the AGC loop consists of an
amplitude extractor and PI controller. The filtered drive detection signal Vout_drivewill be
multiplied by itself through an x2 type amplitude detector to get square term and the DC term.
Through a low pass FIR its effective amplitude will then be derived. The error between the
actual signal amplitude and expected reference amplitude Vref will be calculated. In the PI
controller, the error value Verr will be sent to two branches. One is to calculate the proportional
term by multiplying KP (proportional coefficient) and the other is to calculate the integral term
by multiplying Ki (integral coefficient) and accumulating the previous results. Next, the key
variable gain will be generated using superposition of the proportional term and the integral
term. Last, prior to a D/A convertor, the changing drive detection signal Vout_drive will be real-time
multiplied by the variable gain Vgain to get an adjustable driving signal Vin_driveto push the proof
mass of the gyroscope steadily. [46]
Figure 6-94 Digital AGC schematic
We can use a three output comparator ( A<B, B<A, A=B) or a one output comparator with diff
levels, this will be determined according to the selected PI controller design
Filters are discussed in section 6.3.1.2 To construct a PI controller we need to mention some basic arithmetic circuits relevance to
speed and capacity. These basic characteristics provide important indication in constructing a
controller
Adders; for example basic parallel circuit and carry look up circuit formula, the carry look up
circuit formula is superior compared with parallel circuit formula in computation time, but the
parallel circuit formula is superior compared with carry look up in capacity. [47] So according
to application needs we determine priority. Same idea for Multiplier for example the
combinational circuit has advantage in computation time. While the sequence circuit formula
has advantage in capacity. [47]
The PI algorithm is well known as
(
)
).I(s)
6-63
[112]
Following discrete PI controller algorithm
( )
6-64
For implementation of the above PI algorithm two structures have been proposed one is speed
priority and the other is capacity priority
6.5.2.1. PI controller (Speed Priority)
The structure of speed priority method is shown in Figure 6-95 . It uses two multipliers so it
needs more gate arrays but it has high execution speed. We have to pay attention to the bit
length changes because it changes before and after multipliers
Figure 6-95 PI controller (Speed priority)
6.5.2.2. PI controller (Capacity Priority)
The structure of capacity-priority method is shown in Figure 6-96. It only uses one multiplier,
but takes more clock cycles
Figure 6-96 PI controller capacity priority
6.5.3. AGC Sum up From different topologies we discussed we came up with some broad outline about some major
differences between them. We can choose which one we use after determining specific specs to
the system. We discussed a high dynamic range circuit, a high capacity and a high speed.
[113]
6.6. Design Flow will be used
6.6.1. Analog
[114]
6.6.2. Digital
[115]
7. Conclusion and Future work
The chapter of tuning fork gyroscope has explained the principle of operation and the design
of it. We found that TFG is depending on the transfer of energy like any gyroscopes with
some advantage that differ it from the other architectures. TFG can double the magnitude of
the output and has the ability to reject the common mode. Although they are not as sensitive
as traditional vibrating ring gyroscopes. In Chapter 4, we explored the Vibrating Ring
architecture, discussed it features, and redesigned an already made gyroscope.
Up to this point, we have explored different MEMS and common electronics building blocks
architectures. We have concluded a design methodology for the whole system. The MEMS
part can be described in Figure 7-1. We start from the point we set the system specifications
after we choose an application (expected to be a consumer application). We choose
fabrication technologies for the device and the ASIC parts. Next, both the circuit designers
and the MEMS designers will agree about the initial device specifications like (actuation
voltages, resonant frequencies, noise floors …etc.) to start working on the device for the
MEMS team and the system level for the circuits team. The MEMS part will start by the
mechanical design of the device, which would be verified by modal FEA. The electrical design
part comes next, then simulate the system level again.
System Initial Specs
Choose Fabrication Technologies
Set Device Specs Mechanical Design FEA Electrical Design System Simulation
LayoutCircuits Team
Kick off
Figure 7-1: Design Methodology of MEMS Part.
[116]
Bibliography
[1] V. Kaajakari, Practical MEMS. Las Vegas: Small Gear Publishing, 2009.
[2] Andrei Shkel Cenk Acar, MEMS Vibratory Gyroscopes – Structural Approaches to Improve
Robustness.: Springer, 2009.
[3] G. Hames, et al. A. Cowen, SOIMUMPs Design Handbook, 8th ed.: MEMS Inc.
[4] A. Trusov, M. Shkel R. Schofield, "Multi-Degree of Freedom Tuning Fork Gyroscope
Demonstrating Shock Rejection," Sensors, pp. 120-123, October 2007.
[5] M. Shkel, P. Prikhodko, A. Zotov A. Trusov, "Low-Dissipation Silicon Tuning Fork Gyroscopes for
Rate and Whole Angle Measurements," Sensors, vol. 11, pp. 2763-2770, November 2011.
[6] R. Schofield, M. Shkel A. Trusov, "Gyroscope Architecture with Structurally Forced Anti-phase
Drive-mode and Linearly Coupled Anti-phase Sense-mode," solid-state sensors, actuators, and
microsystems, pp. 660-663, June 2009.
[7] M. F. Zaman, "-Per-Hour Mode-Matched Micromachined Silicon Vibratory Gyroscopes," Georgia
Institute of Technology, PhD Thesis 2008.
[8] M. W. Putty, "A Micromachined Vibrating Ring Gyroscope", Ph.D Thesis, Electrical Engineering,
University of Michigan, 1995.
[9] S. Lee, K. Najafi S. W. Yoon, "Vibration sensitivity analysis of MEMS vibratory ring gyroscopes,"
Sensors and Actuators, vol. 171, pp. 163-177, August 2011.
[10] S. W. Yoon, "Vibration isolation and shock protection for MEMS”, PhD Thesis, Electrical
Engineering, University of Michigan, 2009.
[11] S.W. Lee, N.C. Perkins, K. Najafi S.W. Yoon, "Vibration Sensitivity of MEMS Tuning Fork
Gyroscopes," in Dig. Tech. Papers, IEEE Sensors Conference, Atlanta, GA, USA, 2007.
[12] K. Najafi F. Ayazi, "A HARPSS Polysilicon Vibrating Ring Gyroscope," MICROELECTROMECHANICAL
SYSTEMS, vol. 10, no. 2, pp. 169-179, June 2001.
[13] E. Rodríguez G. Gesnouin, "Effective Mass of an Oscillating Spring," Spring he Physics Teacer, vol.
45, pp. 100-103, February 2007.
[14] Chinwuba David Ezekwe, "READOUT TECHNIQUES FOR HIGH-Q MICROMACHINED VIBRATORY
RATE GYROSCOPES," 2007.
[15] Ajit Sharma, "CMOS SYSTEMS AND CIRCUITS FOR SUB-DEGREE PER HOUR MEMS GYROSCOPES,"
2007.
[16] J. Raman, "A DIGITALLY CONTROLLED MEMS GYROSCOPE WITH UNCONSTRAINED SIGMA-DELTA
FORCE FEEDBACK ARCHITECTURE," 2006.
[117]
[17] Ran Fang, "A LOW-NOISE INTERFACE CIRCUIT FOR MEMS VIBRATORY GYROSCOPE," 2010.
[18] Huikai Xie,Hongzhi Sun Robert M. Fox, "A CMOS-MEMS GYROSCOPE INTERFACE CIRCUIT DESIGN
WITH HIGH GAIN AND LOW TEMPERATURE DEPENDENCE," 2011.
[19] Ajit Sharma, M. Faisal Zaman Farrokh Ayazi, "A 104-DB DYNAMIC RANGE TRANSIMPEDANCE-
BASED CMOS ASIC FOR TUNING FORK MICROGYROSCOPES ," 2007.
[20] H. Rodjegard, "A DIGITALLY CONTROLLED MEMS GYROSCOPE WITH 3.2 DEG/HR STABILITY,"
2005.
[21] YÜKSEL TEMİZ, "ADVANCED READOUT AND CONTROL ELECTRONICS FOR MEMS GYROSCOPES,"
2007.
[22] DEYOU FANG, "LOW-NOISE AND LOW-POWER INTERFACE CIRCUITS DESIGN FOR INTEGRATED
CMOS-MEMS INERTIAL SENSORS," 2006.
[23] Navid Yazdi, "PRECISION READOUT CIRCUITS FOR CAPACITIVE MICROACCELEROMETERS," 2004.
[24] D. Fang, and H. Xie H. Qu, "HIGH-RESOLUTION INTEGRATED MICRO-GYROSCOPE FOR SPACE
APPLICATIONS," 2004.
[25] Jiangfeng Wu, "SENSING AND CONTROL ELECTRONICS FOR LOW-MASS LOW-CAPACITANCE
MEMS ACCELEROMETERS ," 2002.
[26] Marcel J.M. Pelgrom, Analog-to-Digital.: Springer Dordrecht Heidelberg London New York, 2010.
[27] David A. Johns, Kenneth W. Martin Tony Chan Carusone, ANALOG INTEGRATED CIRCUIT DESIGN.,
2 edition.
[28] razavi, principles of data conversion system design by razavi., 1995.
[29] Uwe Meyer-Baease, "Digital signal processing with field programmable gate array".
[30] SAGARA PANDU, "Design and VLSI Implementation of a Decimation filter for Hearing Aid
Applications ," 2007.
[31] Bibin John, "Comparison of Decimation Filter Architectures for a Sigma-Delta Analog to Digital
Converter ," 2011.
[32] Walt Kester, ANALOG-DIGITAL CONVERSION.: Analog Devices, Inc., March 2004.
[33] WANG Yuelin, "A Digital Demodulation Solution to Achieve Stable Driving for a Micro-machined
Gyroscope with an AGC Mechanism," 2004.
[34] MOUMITA GHOSH, "DESIGN AND IMPLEMENTATION OF DIFFERENT MULTIPLIERS USING VHDL ,"
2007.
[118]
[35] "University of California, Berkeley Handouts," 2009.
[36] V.Alekhya, "Architectural Level Power Optimization Techniques for Multipliers ," 2012.
[37] John G. Proakis, Digital signal processing.
[38] H R Pota. (2005, June) [Online]. http://www.seit.adfa.edu
[39] B.Razavi,., pp. 532-578.
[40] D.H.Wolaver,., pp. 47-80.
[41] M. Brownlee,K. Mayaram P. K. Hanumolu. (2004) Analysis of charge pump phase locked loops.
[42] S.V.SOLANKE, "CHARGE PUMP ARCHITECTURE FOR PHASE LOCKED LOOP," 2009.
[43] J.G.Maneatis,., 1996, pp. 1723-1732.
[44] Wang Wenzhao, Chen Yaqin, and Zhou Qi, "Implementation of mixed feedback/feedforward
analog and digital AGC," , 2004, pp. 377- 381.
[45] Mladen Vucic and Marko Butorac, "All-Digital High-Dynamic Automatic Gain Control ," , 2009, pp.
1032- 1035.
[46] Cheng Yu and Yuliang Wang Dunzhu Xia, "A Digitalized Silicon Microgyroscope Based on
Embedded FPGA," pp. 13153-13154, 2012 September.
[47] Y. Shiroishi and 0. Ichinoha Hai-Jaio GUO, "Digital PI controller for high frequency switching
DC/DC converters based on FPGA," in Telecommunications Energy Conference, 2003, pp. 536 -
541.
[119]
Appendices
Appendix A – ANSYS Script to Calculate the Stiffness of a Fixed-Guided
Straight Beam /FILNAME, Calculate_K
/title, Calculate the Spring Constant and Modes
/UNITS, uMKS
!* 1- BUILDING A MODEL-----------------------------------------------------
/PREP7
KEYW,PR_STRUC,1 !(Structural Analysis)
!* --1.1- Define Parameters------------------------------------------------
beamLength = 500
beamWidth = 4
youngsModulus = 150E03 !(Real Value: from 127G to 180G)
appliedForce = 10
dt = appliedForce/100
!* --1.2- ELEMENT TYPES AND REAL CONSTANTS---------------------------------
ET,1,PLANE183,,,3
R,1,25,
!* --1.3- DEFINING MATERIAL PROPERTIES-------------------------------------
MP,EX,1,youngsModulus !(Young's Modulus = youngsModulus)
!* --1.4- CREATING THE MODEL GEOMETRY--------------------------------------
!* ----1.4.1- MODELING-----------------------------------------------------
RECTNG,-(beamWidth/2),(beamWidth/2),0,beamLength, !A1
!* ----1.4.2- MESHING------------------------------------------------------
ESIZE,beamWidth/8 ! element size
AMESH,all ! Mesh the area
FINISH
!* ------------------------------------------------------------------------
!* 2- APPLYING LOADS AND OBTAINING THE SOLUTION----------------------------
/SOL
!* --2.1- DEFINIGN THE ANALYSIS TYPE AND ANALYSIS OPTIONS------------------
ANTYPE,STATIC !(Static analysis)
NLGEOM,ON !(Nonlinear geometry, toggle OFF for linear
analysis)
NSUBST,100,4000,1
OUTRES,ERASE
OUTRES,ALL,ALL
DELTIME,dt,dt,dt,Off
AUTOTS,OFF
LNSRCH,ON
NEQIT,1000
!* --2.2- APPLYING LOADS---------------------------------------------------
DL, 1, ,ALL,0,
DL, 3, ,UY ,0,
*DO,I,1,10
Time,(I/10)*appliedForce
FK,4,FX,(I/10)*appliedForce,
LSWRITE,I,
*ENDDO
LSSOLVE,1,10,1
FINISH
!* ------------------------------------------------------------------------
!* 3- REVIEWING RESULTS----------------------------------------------------
/POST26
FILE,'Calculate_K','rst','.'
/UI,COLL,1
NUMVAR,200
SOLU,191,NCMIT
STORE,MERGE
[120]
FILLDATA,191,,,,1,1
REALVAR,191,191
NSOL,2,18,U,X, UX_2
STORE,MERGE
XVAR,1
PLVAR,2,
PRVAR,2,
/AXLAB,Y,DEFLECTION !(Changes y label)
/AXLAB,X,LOAD !(Changes X label)
/REPLOT
FINISH
[121]
Appendix B - ANSYS Script to Calculate the Stiffness of Fixed Guided Curved
Beam
B.1 Horizontal and Vertical Stiffness /FILNAME, Calculate_K
/title, Calculate the Spring Constant
/UNITS, uMKS
!* 1- BUILDING A MODEL-----------------------------------------------------
/PREP7
KEYW,PR_STRUC,1 !(Structural Analysis)
!* --1.1- Define Parameters------------------------------------------------
w_ring = 4
h_ring = 80
r_spring = 235
youngsModulus = 150e+3 !(150 GPa)
appliedForce = 1000
dt = appliedForce/100
!* --1.2- ELEMENT TYPES AND REAL CONSTANTS---------------------------------
ET,1,PLANE183,,,3
R,1,80,
!* --1.3- DEFINING MATERIAL PROPERTIES-------------------------------------
MP,EX,1,youngsModulus !(Young's Modulus = youngsModulus)
CYL4,0,0,r_spring,0,r_spring+w_ring,180 ! create half circle
ESIZE,w_ring/10 ! element size
AMESH,all ! mesh the Area
FINISH
!* 2- APPLYING LOADS AND OBTAINING THE SOLUTION----------------------------
/SOL
!* --2.1- DEFINIGN THE ANALYSIS TYPE AND ANALYSIS OPTIONS------------------
ANTYPE,STATIC !Static analysis
!*
###########################################################################
!* ---------------------------------FOR KHA--------------------------------
!* --2.2- APPLYING LOADS---------------------------------------------------
DL, 2, ,ALL,0, !Displacement of Line 2 in All DOF = 0
DL, 4, ,UY ,0, !Displacement of Line 4 in Y DOF = 0
FK,1,FX,appliedForce, !Horizontal Force
Solve
!* 3- REVIEWING RESULTS----------------------------------------------------
/POST1
/EFACET,1
PLNSOL, U,X, 0,1.0
FINISH
!*
###########################################################################
!* ---------------------------------FOR KVA--------------------------------
!* --2.2- APPLYING LOADS---------------------------------------------------
DL,2,,ALL,0, !Displacement of Line 2 in All DOF = 0
DL,4,, UX,0, !Displacement of Line 4 in X DOF = 0
FK,1,FY,appliedForce, !Vertical Force
Solve
FINSIH
[122]
!* 3- REVIEWING RESULTS----------------------------------------------------
/POST1
/EFACET,1
PLNSOL, U,Y, 0,1.0
FINISH
!* ------------------------------------------------------------------------
B.2 45o Stiffness /FILNAME, Calculate_K
/title, Calculate the Spring Constant
/UNITS, uMKS
1- BUILDING A MODEL--------------------------------------------------------
/PREP7
KEYW,PR_STRUC,1 !(Structural Analysis)
!* --1.1- Define Parameters------------------------------------------------
w_ring = 4
h_ring = 80
r_spring = 235
youngsModulus = 150e+3 !(150 GPa)
appliedForce = 1000
dt = appliedForce/100
!* --1.2- ELEMENT TYPES AND REAL CONSTANTS---------------------------------
ET,1,PLANE183,,,3
R,1,80,
!* --1.3- DEFINING MATERIAL PROPERTIES-------------------------------------
MP,EX,1,youngsModulus !(Young's Modulus = youngsModulus)
!* --1.4- CREATING THE MODEL GEOMETRY--------------------------------------
!* ----1.4.1- MODELING-----------------------------------------------------
wpro,45.000000,,
CYL4,0,0,r_spring,0,r_spring+w_ring,180
wpro,-45.000000,,
!* ----1.4.2- MESHING------------------------------------------------------
ESIZE,w_ring/10 ! Element size
AMESH,all ! mesh the Area
FINISH
!* 2- APPLYING LOADS AND OBTAINING THE SOLUTION----------------------------
/SOL
!* --2.1- DEFINIGN THE ANALYSIS TYPE AND ANALYSIS OPTIONS------------------
----ANTYPE,STATIC !(Static analysis)
NLGEOM,OFF !(Nonlinear geometry on)
!* --2.2- APPLYING LOADS---------------------------------------------------
DL, 2, ,ALL,0, !Displacement of Line 2 in All DOF = 0
DL, 4, ,UX ,0,
FK,1,FY,appliedForce,
Solve
FINISH
!* 3- REVIEWING RESULTS----------------------------------------------------
/POST1
/EFACET,1
PLNSOL, U,Y, 0,1.0
FINISH
[123]
Appendix C - ANSYS Script for Modal Analysis of Tuning Fork Gyroscope /FILNAME, Modal_Analysis
/title, Display the modes
/UNITS, uMKS
!* 1- BUILDING A MODEL-----------------------------------------------------
/PREP7
KEYW,PR_STRUC,1 !(Structural Analysis)
!* --1.1- Define Parameters------------------------------------------------
height = 400
width = 500
heightmass = 270
widthmass = 400
beamLength = 562
beamWidth = 10
anchorwidth = 7
beamPos = 198 !(From Edge)
appliedPressure = 10.6E+03
youngsModulus = 150E+03 !(Real Value: from 127G to 180G)
poissonsRatio = 0.2 !(Real Value: from 0.2 to 0.278)
density = 2330E-18
!* --1.2- ELEMENT TYPES AND REAL CONSTANTS---------------------------------
ET,1,PLANE183,,,3
R,1,25,
!* --1.3- DEFINING MATERIAL PROPERTIES-------------------------------------
MP,DENS,1,density
MPTEMP,,,,,,,,
MPTEMP,1,0
MPDATA,EX,1,,youngsModulus !(Young's Modulus = youngsModulus)
MPDATA,PRXY,1,,poissonsRatio !(Poisson's Ratio = poissonsRatio)
!* --1.4- CREATING THE MODEL GEOMETRY--------------------------------------
!* ----1.4.1- MODELING-----------------------------------------------------
RECTNG, -(beamLength+beamwidth/2),-(beamLength-beamWidth/2),
(heightmass/2), (heightmass/2+beamLength), !A3
RECTNG, -(beamLength+beamwidth/2),-(beamLength+beamwidth/2+beamLength/2.5),
(heightmass/2+beamLength-beamWidth), (heightmass/2+beamLength), !A7
RECTNG, (beamLength-beamwidth/2), (beamLength+beamwidth/2),
(heightmass/2), (heightmass/2+beamLength), !A5
RECTNG, (beamLength+beamwidth/2), (beamLength+beamwidth/2+beamLength/2.5),
(heightmass/2+beamLength-beamWidth), (heightmass/2+beamLength), !A10
RECTNG, -(beamLength+beamwidth/2+beamLength/2.5),-
(beamLength+beamwidth/2+beamLength/2.5+beamwidth),
(heightmass/2+beamLength-beamWidth), (heightmass/2+11*beamLength/10), !A11
RECTNG, (beamLength+beamwidth/2+beamLength/2.5),
(beamLength+beamwidth/2+beamLength/2.5+beamwidth),
(heightmass/2+beamLength-beamWidth), (heightmass/2+11*beamLength/10), !A13
RECTNG, -(beamLength+beamWidth/2+beamLength/2.5+beamwidth),
(beamLength+beamWidth/2+beamLength/2.5+beamwidth),
(heightmass/2+beamLength+beamLength/10),
(heightmass/2+beamLength+beamLength/10+1.5*beamWidth), !A16
AADD,ALL
RECTNG, -(0.4*anchorwidth), (0.4*anchorwidth), (heightmass/2+beamLength/4),
(heightmass/2+beamLength+beamLength/10),
[124]
ARSYM,Y,1, , , ,0,0 !*REFLECT ABOUT XZ Plane => Produces A1
ARSYM,Y,8, , , ,0,0
AGLUE,2,3
RECTNG, -(widthmass/2+beamLength), -(beamLength-widthmass/2),
-(heightmass/2), (heightmass/2), !A4
RECTNG, (beamLength-widthmass/2),
(beamLength+widthmass/2), -(heightmass/2),
(heightmass/2), !A5
AGLUE,ALL !(Glue all Areas Together)
!* ----1.4.2- MESHING------------------------------------------------------
AESIZE,1,(beamwidth/6)
AESIZE,2,(beamwidth/6)
AESIZE,4,(beamwidth/6)
AESIZE,9,(beamwidth/6)
AESIZE,6,0.01*(width*height) !(Element Size of Area 1 = width*height/1E04)
AESIZE,7,0.01*(width*height) !(Element Size of Area 1 = width*height/1E04)
MSHAPE,0,2D !(Element Shape: 0=>Quadrilateral, 2D=>Area
Mesh)
MSHKEY,0 !(Use Free Meshing)
AMESH,ALL
FINISH
!* ------------------------------------------------------------------------
/SOL
!* --2.2- APPLYING LOADS---------------------------------------------------
DL,14,,ALL,0 !(Displacement of Line 33 in All DOF = 0)
DL,16,,ALL,0 !(Displacement of Line 33 in All DOF = 0)
DL,6,,ALL,0 !(Displacement of Line 33 in All DOF = 0)
DL,8,,ALL,0 !(Displacement of Line 33 in All DOF = 0)
!* --2.2- DEFINING THE ANALYSIS TYPE AND ANALYSIS OPTIONS------------------
ANTYPE,MODAL
EQSLV,SPAR
MXPAND,10, , ,0
LUMPM,0
PSTRES,0
MODOPT,LANB,10,1E3,20E3, ,OFF
SOLVE
FINISH
!* 3- REVIEWING RESULTS----------------------------------------------------
/POST1
SET,FIRST !(FIRST or NEXT or LAST or PREVIOUS)
PLDI, ,
ANMODE,50,0.1E-01, ,0 !(Animate Mode, 50 Frame Captures, 0.01
Seconds Delay, 0: Linear Acceleration)
!* ------------------------------------------------------------------------
SET,NEXT !(FIRST or NEXT or LAST or PREVIOUS)
PLDI, ,
ANMODE,50,0.1E-01, ,0
FINISH
[125]
Appendix D - Plotting Vibrations of the Ring Structure using SciLAB theta = [0.005:0.005*%pi:2*%pi];
R_ring = 550*(theta')./(theta');
theta_o= 22.5*%pi/180;
//------Mode Shapes ------------------------------------------------------
phi1r = cos(theta'-theta_o);
phi2r=sin(theta'-theta_o);
phi3r=cos(2*theta'-2*theta_o);
phi4r=sin(2*theta'-2*theta_o);
figure(5);clf(5);polarplot([theta' theta'],[phi1r phi2r],[2,5]);
figure(6);clf(6);polarplot([theta' theta'],[phi3r phi4r],[2,5]);
//------------------------------------------------------------------------
//------Ring Vibrations---------------------------------------------------
q = [5 15 30 45];
q1 = q; q2 = q; q3 = q; q4 = q
//--------Evolution of the first Translational Mode Vibrations -----------
figure(1);clf(1);polarplot([theta' theta' theta' theta' theta'],[R_ring
q1(1).*phi1r+R_ring q1(2).*phi1r+R_ring q1(3).*phi1r+R_ring
q1(4).*phi1r+R_ring], [2,5,5,5,5]);
q1 = -q1;
figure(1);polarplot([theta' theta' theta' theta' theta'],[R_ring
q1(1).*phi1r+R_ring q1(2).*phi1r+R_ring q1(3).*phi1r+R_ring
q1(4).*phi1r+R_ring], [2,5,5,5,5]);
//--------Evolution of the second Translational Mode Vibrations ----------
figure(2);clf(2);polarplot([theta' theta' theta' theta' theta'],[R_ring
q2(1).*phi2r+R_ring q2(2).*phi2r+R_ring q2(3).*phi2r+R_ring
q2(4).*phi2r+R_ring], [2,5,5,5,5]);
q2 = -q2;
figure(2);polarplot([theta' theta' theta' theta' theta'],[R_ring
q2(1).*phi2r+R_ring q2(2).*phi2r+R_ring q2(3).*phi2r+R_ring
q2(4).*phi2r+R_ring], [2,5,5,5,5]);
//--------Evolution of the Drive Mode Vibrations -------------------------
figure(3);clf(3);polarplot([theta' theta' theta' theta' theta'],[R_ring
q3(1).*phi3r+R_ring q3(2).*phi3r+R_ring q3(3).*phi3r+R_ring
q3(4).*phi3r+R_ring], [2,5,5,5,5]);
q3 = -q3;
figure(3);polarplot([theta' theta' theta' theta' theta'],[R_ring
q3(1).*phi3r+R_ring q3(2).*phi3r+R_ring q3(3).*phi3r+R_ring
q3(4).*phi3r+R_ring], [2,5,5,5,5]);
//--------Evolution of the Sense Mode Vibrations -------------------------
figure(4);clf(4);polarplot([theta' theta' theta' theta' theta'],[R_ring
q4(1).*phi4r+R_ring q4(2).*phi4r+R_ring q4(3).*phi4r+R_ring
q4(4).*phi4r+R_ring], [2,5,5,5,5]);
q4 = -q4;
figure(4);polarplot([theta' theta' theta' theta' theta'],[R_ring
q4(1).*phi4r+R_ring q4(2).*phi4r+R_ring q4(3).*phi4r+R_ring
q4(4).*phi4r+R_ring], [2,5,5,5,5]);
[126]
Appendix E - ANSYS Script for Modal Analysis of Ring Gyroscope /FILNAME, Ring_Gyroscope
/title, Calculate the Resonance Frequencies and and Modes
/UNITS, uMKS
!* ------------------------------------------------------------------------
!* 1- BUILDING A MODEL-----------------------------------------------------
/PREP7
KEYW,PR_STRUC,1 !(Structural
Analysis)
!* --1.1- Define Parameters------------------------------------------------
R_ring = 550 !Ring Radius
W_ring = 4 !Width of the ring
h_ring = 80 !Height of the ring
structure
r_spring = 235 !Radius of the spring
R_post = 60 !Radius of the Post
delta_Rect = R_ring-R_post-2*r_spring !space between spring
and ring
youngsModulus = 150E+03 !Young’s Modulus
poissonsRatio = 0.2 !poisson’s Ratio
density = 2328e-18 !desnity of silicon
Izz = w_ring*w_ring*w_ring*h_ring/12 !Moment of Area
CrossSection = w_ring*h_ring !Cross-section Area
dr = 1E-2 !used to tune the
geometry
!* --1.2- ELEMENT TYPES AND REAL CONSTANTS---------------------------------
ET,1,BEAM3 !Element: Beam
r,1,CrossSection,Izz,beamWidth !area, izz, height of beam
!* --1.3- DEFINING MATERIAL PROPERTIES-------------------------------------
MP,DENS,1,density
MPTEMP,,,,,,,,
MPTEMP,1,0
MPDATA,EX,1,,youngsModulus !(Young's Modulus = youngsModulus)
MPDATA,PRXY,1,,poissonsRatio !(Poisson's Ratio = poissonsRatio)
!* --1.4- CREATING THE MODEL GEOMETRY--------------------------------------
!* ----1.4.1- MODELING-----------------------------------------------------
K,1,0,0,0
CIRCLE,1,R_ring,P,,360,8
CIRCLE,1,R_post,P,,360,8
CIRCLE,1,R_ring-delta_Rect,P,,360,8
*DO,I,17,24
LDELE,I
*ENDDO
K,, (R_post+R_spring), R_spring,0
K,,((R_post+R_spring)*cos(45)-r_spring*cos(45)),
(R_spring+R_spring*cos(45)),0
K,,-(R_spring), (R_post+R_spring),0
K,,-(R_spring+R_spring*cos(45)),((R_post+R_spring)*cos(45)-
r_spring*cos(45)),0
K,,-(R_post+R_spring),-R_spring,0
K,,-((R_post+R_spring)*cos(45)-r_spring*cos(45)),-
(R_spring+R_spring*cos(45)),0
[127]
K,, (R_spring),-(R_post+R_spring),0
K,,(R_spring+R_spring*cos(45)),-((R_post+R_spring)*cos(45)-
r_spring*cos(45)),0
LARC,10,18,26,r_spring+dr,
LARC,11,19,27,r_spring+dr,
LARC,12,20,28,r_spring+dr,
LARC,13,21,29,r_spring+dr,
LARC,14,22,30,r_spring+dr,
LARC,15,23,31,r_spring+dr,
LARC,16,24,32,r_spring+dr,
LARC,17,25,33,r_spring+dr,
L,18,2,0
L,19,3,0
L,20,4,0
L,21,5,0
L,22,6,0
L,23,7,0
L,24,8,0
L,25,9,0
LGLUE,All
!* ----1.4.2- MESHING------------------------------------------------------
ESIZE,0.04999858094171871699 ! element size s
LMESH,all ! mesh the line
FINISH
!* ------------------------------------------------------------------------
!* 2- APPLYING LOADS AND OBTAINING THE SOLUTION----------------------------
/SOL
!* --2.1- APPLYING LOADS---------------------------------------------------
*DO,I,0,7
DL,(9+I), ,ALL,0
*ENDDO
!* --2.2- DEFINING THE ANALYSIS TYPE AND ANALYSIS OPTIONS------------------
ANTYPE,MODAL
MODOPT,LANB,5
EQSLV,SPAR
MXPAND,5, , ,0
LUMPM,0
PSTRES,0
MODOPT,LANB,5,10,5E6, ,OFF
SOLVE
FINISH
!* ------------------------------------------------------------------------
!* 3- REVIEWING RESULTS--------------------------------------------------
/POST1
SET,FIRST !(FIRST or NEXT
or LAST or PREVIOUS)
PLDI,2,
ANMODE,50,0.1E-01, ,1
FINISH
[128]
Appendix F: Project Timeline