bridging the gap in the risc-v memory models · trippel, micro top picks] [dan lustig, risc-v...
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![Page 1: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/1.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Bridging the gap in the RISC-V
memory models
Stefanos Kaxiras1,2
Alberto Ros1,3
1Eta Scale AB, Sweden2Uppsala University
3University of Murcia
![Page 2: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/2.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
RISC-V Memory Model
The memory consistency model:
• Specifies the values returned by every load
• Contract between the programmer and the machine
Main memory model in RISC-V:
• RVWMO: RISC-V Weak Memory Order
Two memory model extensions: – Zam: for misaligned atomics
– Ztso: for RISC-V Total Store Order (RVTSO)
![Page 3: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/3.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
RISC-V Weak Memory Model
• Defined by 13 ordering rules
• Complex
• “bugs” already found w.r.t C++11 memory model
and non-Multi-Copy-Atomic architectures [C.
Trippel, Micro Top Picks]
[Dan Lustig, RISC-V Memory Consistency Model Tutorial]
![Page 4: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/4.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
RISC-V Total Store Order
Defined as a extension of RVWMO
• All loads acquire semantics
• All stores release semantics
• All AMOs acquire & release semantics
• BUT: RCPC not RCSC:
.rl .aq does not apply : relaxes storeload
[Dan Lustig, RISC-V Memory Consistency Model Tutorial]
![Page 5: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/5.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
How to compare ?
• Advantage RVTSO simpler semantics
• But what is its cost/performance?
• Perception:
– WMO is Faster: enforces less ordering
• TSO enforces more
– WMO is Cheaper: fences enforce order
• TSO must enforce all order in HW
![Page 6: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/6.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Fallacies
TSO Enforces more ordering
• Not true– [Ros, Kaxiras, Micro’16, Micro Top Picks Honorable Mention,
Ros & Kaxiras “Racer”]
• Hardware can speculatively reorder memory operations
• Reacts only on conflicts and enforces order
• In contrast WMO: Statically fencing code for every possible conflict even if the conflict does not appear at runtime!
TSO More costly to implement: requires speculation
• Not true
• Non-speculative load-load reodering– [Ros, Kaxiras, ISCA’17, Micro Top Picks]
• Non-speculative store-store reodering– [Ros, Kaxiras, ISCA’18]
![Page 7: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/7.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Ordering in Consistency Models
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
SC TSO WMO
…
fence_LLfence_LSfence_SSfence_SL
Enforce ordering via statically-placed fences
Speculative reordering: Enforce ordering on
dynamic events (misspeculation)
![Page 8: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/8.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Ordering in Consistency Models
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
SC TSO WMO
…
NON-SPECULATIVELY:
• Allow load-load reordering (hit-under-miss, MLP) but guarantee ldld when it can be observed [ISCA’17]
• Allow store-store reordering (store coalescing) but guarantee stst when it can be observed [ISCA’18]
![Page 9: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/9.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Ordering in Consistency Models
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
SC TSO WMO
…
NON-SPECULATIVELY:
• Allow load-load reordering (hit-under-miss, MLP) but guarantee ldld when it can be observed [ISCA’17]
• Allow store-store reordering (store coalescing) but guarantee stst when it can be observed [ISCA’18]
• ldst : inconsequential
• Store atomicity
![Page 10: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/10.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
Speculative load Reordering in TSO
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
misshit
![Page 11: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/11.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
Inval.
ldld x
Caught!
st x
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Store
Buffer
Cache
Core
![Page 12: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/12.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
Squash & Re-execute
st x
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Store
Buffer
Cache
Core
![Page 13: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/13.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
A New Non-Speculative Solution
st x
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Store
Buffer
Cache
Core
![Page 14: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/14.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
A New Non-Speculative Solution
st x
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Store
Buffer
Cache
Core
NACK:
Don’t come out now
or you might
see me
![Page 15: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/15.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
A New Non-Speculative Solution
st x
ACK: You can
come out now, I’m
decentShared Cache/Dir/Memory
Core
Store
Buffer
Cache
NACK:
Don’t come out now
or you might
see me
Store
Buffer
Cache
Core
![Page 16: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/16.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
A New Non-Speculative Solution
st x
ACK: You can
come out now, I’m
decentShared Cache/Dir/Memory
Core
Store
Buffer
Cache
NACK:
Don’t come out now
or you might
see me
Store
Buffer
Cache
Core
Key Insight: In a tight spot, use uncacheable
transactions (“Tear-off” data)
no Deadlock, no Livelock
![Page 17: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/17.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
ld ld
ld st
st st
st ld
ldld x
A New Non-Speculative Solution
st x
ACK: You can
come out now, I’m
decentShared Cache/Dir/Memory
Core
Store
Buffer
Cache
NACK:
Don’t come out now
or you might
see me
Store
Buffer
Cache
Core
Same performance & traffic as
speculative solution;
BUT: No SPECULATION COST
Opens new possibilities:
In-order cores, OoO Commit,
No Load Queue!
![Page 18: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/18.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Memory Consistency Models
18
ld ld
ld st
st st
st ld
ld ld
ld st
st st
st ld
TSO RC
…
fence_LLfence_LSfence_SSfence_SL
Enforce ordering via statically-placed fences
Non-Spec. Enforce ldld
ordering on conflicts
• Can we do the same for stst?
• Why? Coalescing in the SB!
– Violates stst when coalescing
non-consecutive stores
– Solution: Atomic group writes
![Page 19: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/19.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Atomic group writes in L1
deadlock
Known solutions:
1. Mutual exclusion
(centralized resource)[TCC ISCA’04, BulkSC
ISCA’07, Racer Micro’06]
2. Transactional (spec.)[Oklahoma PDTSA’03,
Store-wait-free ISCA’07]
![Page 20: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/20.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
![Page 21: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/21.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
![Page 22: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/22.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
await
![Page 23: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/23.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
wait
![Page 24: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/24.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
wait
![Page 25: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/25.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
![Page 26: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/26.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
![Page 27: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/27.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
ba
![Page 28: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/28.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
ba
![Page 29: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/29.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
a
b
![Page 30: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/30.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Simple Solution: Order in
{atomic group} does not
matter use a non-
deadlocking order
Lexicographical order :
physical address
a
b
a
b
![Page 31: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/31.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
An {atomic group} does
not fit in one of the set-
associative structures
(L1, L2, Dir, LLC, … )
needed for a write
a b c
![Page 32: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/32.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
a b c
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB:
• always fits in any set-
associative structure in
the system
• OR: has to wait for
others occupying
shared resources
![Page 33: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/33.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB:
• always fits in any set-
associative structure in
the system
• OR: has to wait for
others occupying
shared resources
a b c
There is a global sub-address (part of the address) lex orderthat guarantees deadlock-freedom in all set-associative
structures of the hierarchy!
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Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Non-Speculative Store Coalescing
a
b
c
c
b
a
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB:
• always fits in any set-
associative structure in
the system
• OR: has to wait for
others occupying
shared resources
There is a global sub-address (part of the address) lex orderthat guarantees deadlock-freedom in all set-associative
structures of the hierarchy!
![Page 35: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/35.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
b
{ } { }
a
![Page 36: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/36.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
b
{ } { }
c await
![Page 37: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/37.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
b
{ } { }
c await
b c
![Page 38: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/38.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
{ } { }
ab c b
![Page 39: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/39.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
{ } { }
a bb c
![Page 40: Bridging the gap in the RISC-V memory models · Trippel, Micro Top Picks] [Dan Lustig, RISC-V Memory Consistency Model Tutorial] Stefanos Kaxiras Bridging the Gap in RISC-V Memory](https://reader031.vdocuments.us/reader031/viewer/2022013002/5e40770829cd5d0892736f2e/html5/thumbnails/40.jpg)
Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
b
Non-Speculative Store Coalescing
a
b
c
c
b
a
Shared Cache/Dir/Memory
Core
Store
Buffer
Cache
Core
Store
Buffer
Cache
{ } { }
Resource Deadlocks!
Key insight: manage the
formation of an atomic
group in the SB
{ } { }
a bb c
This is TSO.Results: SAME coalescing potential as Release Consistency
(RC) [ISCA’18]
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Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Store Atomicity
• Store atomicity has a huge impact on memory model implementations– Multi-Copy-Atomic (MCA): all cores see same store at
same time
– read-own-write-early MCA (rMCA): core can see own stores (in SB) early (e.g., x86)
– non-MCA: everything goes
• In TSO, a store atomicity “violation” (rMCA, nMCA) may appear as a violation of loadload (e.g., source of complexity in the x86-TSO)
• Observation: it’s not a crime, if you don’t get caught– A store atomicity violation only matters if it causes
loadload to be violated
– Find the conditions that allow this to happen and prevent it!
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Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Store Atomicity
• Same as every other consistency rule: react dynamically to conflicting accesses and appear to be store atomic
• Clean Stote-Atomic-TSO: like SC without the storeload
• Speculation & rollback– Negligible HW overhead
– Speculative Store-Atomic-TSO: 3% overhead over rMCA TSO
– MCA TSO: > 40% overhead over rMCA TSO
(paper under submission)
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Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Conclusions
• Enforcing order dynamically in TSO potentially better than static fencing in WMO …
• In the past reordering in TSO meant speculation overhead
• We have shown (in TSO): – non-speculative ldld
• No LQ needed!
– non-speculative stst (coalescing)• Coalescing on par with RC
– speculative-MCA TSO in rMCA architectures
• Future:– Speculative and non-speculative store atomicity, in
nMCA architectures
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Stefanos Kaxiras
Bridging the Gap in RISC-V Memory Models
Thank you!
Questions ?