bridging design and manufacture of analog/mixed-signal...
TRANSCRIPT
IEEE Solid-State Circuits Society / Central Texas Chapter
Bridging Design and Manufacture of Analog/Mixed-Signal (AMS) Circuits in Advanced CMOS
Alvin Loke, Ray Stephany, Dennis Fischette, Tin Tin Wee,John Faricelli, Hoang Dao, Larry Bair, Jim Buller, Dru Cabler,
Bruce Doyle, Shawn Searles, Emerson FangAdvanced Micro Devices
Jia Feng, Joanne Wu, Jung-Suk Goo, Christoph Schwan, Xin LiGLOBALFOUNDRIES
Joddy Wang, Dehuang Wu, Song Zhou, Weidong LiuSynopsys
July 6, 2012
AUTHORIZATIONAll copyrights to the material contained in this document are retained by me or by my employer.
© Loke et al., Bridging Design and Manufacture of AMS Circuits Slide 1
DDR3 I/OPLL Clock
Core PLL Clocks (voltage/frequency islands)Regulators & Thermal Sensors
32nm SOI-CMOS “Orochi” server processor with Bulldozer cores
HT3+ I/OsPLL ClocksRegulators
AMS is Essential in Processors
Fischer et al., Ref. [1]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Outline
• Background & Motivation• Device-Level Characterization• Circuit-Level Characterization• Circuit Simulator Developments• Conclusions
Slide 2
© Loke et al., Bridging Design and Manufacture of AMS Circuits
CMOS Scaling Driven by Logic Needs
Slide 3
Keating, Ref. [2]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
The Roads to Higher Performance
Slide 4
source
drain
channel
Decrease L – steepen the hill
source
drain
channel
lithographyscaling
Increase µ – move carriers faster
source
drain
channel
strain engineeringfaster materials
source
drain
channel
Increase Cox – move more carriers
high-K dielectricmetal gate
tdelay Cload ∆V
IFET
• Doing it all without parasitic R & C undoing all the IFET gains
© Loke et al., Bridging Design and Manufacture of AMS Circuits
AMS Design Realities• Difficult to co-optimize process for both AMS and
logic and stay cost-effective• So we generally have to live with what we get
– Voltage headroom – FETs: gain , output resistance , variation , leakage – Passives: as cheap as possible, choices , less ideal– Layout proximity effects – Circuit options
Slide 5
© Loke et al., Bridging Design and Manufacture of AMS Circuits Slide 6
Bleeding-Edge Processor Development• Design concurrently developed with technology to shorten
product time-to-market
InitialDesign
Time
UpdatedDesign
FinalDesign
• Multiple models• Multiple iterations• Design feedback• Earlier start/finish
Bair, Ref. [3]
Test Chip
Mod
el U
ncer
tain
ty
SpeculativeModels
Silicon-InfluencedModels
Silicon-BasedModels
© Loke et al., Bridging Design and Manufacture of AMS Circuits Slide 7
Let The Truth Be Told About Our Models• Speculative and inherently uncertain• Historically tailored to logic, not analog or passives
– Go digital if it makes sense (complexity, power, area, etc.)… fab will take better care of you, easier to port to next node
• Limited to fab understanding of design usage• Intrinsically late to capture new effects
– e.g., STI stress, well implant proximity, stress proximities
• Understand their limitations
© Loke et al., Bridging Design and Manufacture of AMS Circuits
0.0
0.5
1.0
1.5
0.0 0.2 0.4 0.6 0.8 1.0
I D (m
A)
VDS
(V)
Analog vs. Digital Regions of Operation
Slide 8
VGS
0.5V
0.7V
1.0V
0.2V
VDD=1.0V
• Analog design needs accurate modeling of slopes (gm, gds, etc.) as well as points (IDsat, IDoff, etc.)
IDsat
IDoff
IDlow
IDhigh
IDeff
IDeff is better metric than Idsat for effective inverter current in CV/I
typical analog biasingVGS=VT to VT+0.2V
Na et al., Ref. [4]
© Loke et al., Bridging Design and Manufacture of AMS Circuits Slide 9
Don’t Overlook the Circuit Simulator• HSPICE calculates FET parameters (terminal
currents & voltages, transconductances, capacitances, etc.) and reports them in output templates
• Parameters (as basic as VT) may not be measured the same way on silicon
• We’ll cover examples of simulator limitations and co-development to overcome them
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Outline
• Background & Motivation• Device-Level Characterization
– MOSFETs• Current-Based gm, gds & gmb
• Drain saturation margin
– Passives
• Circuit-Level Characterization• Circuit Simulator Developments• Conclusions
Slide 10
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Analog Usage of MOSFETs
Slide 11
• Transconductor in saturation, want IDS=f(only VGS)• Fab measures gm, gds & gmb at VGS = VT+VON or VDD• Scaled supply VON & VDSVDSsat as low as 50mV• Constant-current VT definition somewhat arbitrary
– Simulated VT criterion Fab VT criterion– Cumbersome to correlate simulation to silicon
• Analog circuits typically biased by IREF
• Examine gm, gds & gmb at realistic min/max IDS usage
© Loke et al., Bridging Design and Manufacture of AMS Circuits
D GS
D0
GS0
m
DS0
ds
DS DS0BS BS0
GS GS0BS BS0
BS0
mb
GS GS0DS DS0
D BSD DS
ID-Based gm, gds & gmb
Slide 12
GS
D
VI
DS
D
VI
BS
D
VI
© Loke et al., Bridging Design and Manufacture of AMS Circuits
ID-Based gm, gds & gmb Example
Slide 13
VDS0 = 0.4VVBS0 = 0V
0.01
0.1
1
10
100
1000
0.1 1L (m)
g m, g
ds, g
mb
(µA
/V)
NMOS 4IT0n×W/LNMOS 16IT0n×W/LPMOS 4IT0p×W/LPMOS 16IT0p×W/L
0.1 1L (m)
28nm
0.1 1L (m)
gm gds gmb
30nm Lmin
IT0n = 300nA (NMOS)IT0p = 70nA (PMOS)
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Saturation Margin• Analog folks adamant about biasing
FETs safely in saturation, i.e., device stays in “pinch-off”
• Need for saturation margin– Signal swing (sometimes with gain)– Modeling errors– Supply droop
• Saturation margin usually VDS VDSsat
• VDSsat depends on model & is difficult to measure
• Tough to have ample margin with decreasing VDD
Slide 14
Vin1 Vin2
Vout
MN1 MN2
MP1 MP2
MtailVBIAS
VDS
ID
badfixedVGS
better
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Introducing VDmargin
Slide 15
• Find VDS margin available before gds by X%
• VDmargin can be simulated & measured uniquely
• VDmargin is much smaller in linear vs. saturation region
© Loke et al., Bridging Design and Manufacture of AMS Circuits
0.0
0.1
0.2
0.3
0.4
0.5
0.1 1L (m)
VDmargin Example for gds=+20%
VDS0=0.4V, VBS0=0V
Slide 16
NMOS
ID0=4IT0n×W/L
ID0=16IT0n×W/L
28nm
0.1 1L (m)
PMOS
ID0=4IT0p×W/L
ID0=16IT0p×W/L
V Dm
argi
n(V
)
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Outline
• Background & Motivation• Device-Level Characterization
– MOSFETs– Passives
• Across-Chip Variation of Poly Resistor• Series Resistance of Accumulation-Mode Varactor• Diode Ideality
• Circuit-Level Characterization• Circuit Simulator Developments• Conclusions
Slide 17
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Z0
Calibration of Poly Resistance Variation
Slide 18
CommonCalibration
TX Lane 20
TX Lane 1
~4mm
TX Lane 2TX Lane 3
RX Lane 20
RX Lane 1RX Lane 2RX Lane 3
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Across-Chip Variation of Poly Resistor
Slide 19
Scribe lane monitor has array of cropped I/O receiver layout to minimize scribe-to-die bias
0
1
2
3
4
5
6
7
8
1.2 1.3 1.4 1.5 1.6Mean Resistance (k)
3 /
Mea
n (%
)
Product Die
I/O
across-chip resistorvariation monitors
32nm
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Series Resistance of Varactor n-Well
Slide 20
• n-type accumulation DECAP built for VDD noise reduction• Need accurate Q modeling for LC-VCO application
finetuningcontrol
VCO output
tailcontrol
45nm
0
2
4
6
8
-2 -1 0 1 2
Shee
t Res
ista
nce
(k
/sq)
0,50,100°C
inversion
depletion
accumulation
VGS
(V)
Fischette et al., Ref. [5]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Bandgap Voltage Reference
Slide 21
• PTAT+CTAT using voltage• Resistors determine weighted voltage summing• Applications: absolute voltage references, references
for regulators delivering quieter power
VNqkT
RRV
RR
NII
qkT
II
qkT
V
RRVVRIVV
D
S
R
S
R
D
DDRDREF
2.1ln
lnln
1
2
21
21
2
1
22
1
111
CTAT + PTAT zero tempco
Razavi, Ref. [6]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Low-Voltage Bandgap Reference
Slide 22
R2N
R1
R2D1 D2
R3
VD1 VD2
VD
VREF
I3 = S I1I1 I2 = I1
M1 M2 M3
VA VB
VBIAS
VB VA
VBIAS
MN1 MN2
MP1 MP2
typical implementation OTA
NqkT
RSRV
RSRR
RN
RV
SRRV
RV
SRSIV DqkT
DDDREF ln
ln
1
3
2
33
123
1231 1
11
CTAT PTAT• PTAT+CTAT using current• Resistors determine weighted summing Banba et al., Ref. [7]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Temperature Sensing
Slide 23
NqkT
II
qkT
INI
qkTVVV
S
D
S
DDDD lnlnln21
• Sense PTAT ∆VD between identical diodes with ratio’ed currents• Average/integrate with Dynamic Element Matching (DEM) to
eliminate impact of current source mismatches• Swap inputs to difference amp to average out offset
N+1 identical current sources partitioned into 1 and N
VD1 VD2
DifferenceAmp
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Diode Ideality
Slide 24
• Need to operate at constant η for accurate ∆VD computation• Factor some margin to cover PVT variation• Monitor η at forward-bias current range of interest
usablebias range
100
Normalized Diode Current Density101 102 103 104 105 106 107 108
Idea
lity
Fact
or, η
VD
ln(ID) seriesresistance
space chargerecombination
slope=q/ηkT
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Outline
• Background & Motivation• Device-Level Characterization• Circuit-Level Characterization
– Voltage-Starved Ring Oscillators– Transmitter Differential Output Driver– Pseudo-Bandgap Voltage Reference
• Circuit Simulator Developments• Conclusions
Slide 25
© Loke et al., Bridging Design and Manufacture of AMS Circuits
HyperTransport™ Die-to-Die Link
Slide 26
Loke et al., Ref. [8]
Embe
dded
Nor
thB
ridge
(NB
)
Embe
dded
Nor
thB
ridge
(NB
)
© Loke et al., Bridging Design and Manufacture of AMS Circuits
DLL for Data Recovery
Slide 27
align clockto data
transitions
sampledata
• Need ability to adjust clock phase for optimum sampling of data
• Generate phases spaced by 30° for subsequent phase interpolation to achieve finer phase resolution
• Use cascade of variable delay stages to generate required phases
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Voltage-Starved Ring Oscillator
Slide 28
• Monitor FET digital behavior at low VDD (0.5-0.7V)
0
2
4
6
8
0.5 0.7 0.9I/O
Dat
a R
ate
(Gb/
s)V
RO (V)
32nm
© Loke et al., Bridging Design and Manufacture of AMS Circuits
HT Transmitter Architecture
Slide 29
• 4-tap FIR filter to equalize channel losses
• Tunable driver output resistance to match channel Z0 for minimal reflection
Half-rate Clock
DatafromNB
TXPLL
TXOutputBumps
StagingLatches
4
DQ
DQ
DQ
De-Emphasis Logic
pre
main
post1
post2
4:2 Serializer
FIFO
DQ
DQ
DQ
DQ
DQ
4
RetimingMuxes
Poly ResistorCalibration
OutputDriver
© Loke et al., Bridging Design and Manufacture of AMS Circuits Slide 30
• Monitor FET Rlinear, resistors, ratio, mismatch
-4 -2 0 2 4Resistance
Mismatch (%)
1.1 1.2 1.3 1.4 1.5.01
.115
102030507080909599
99.999.99
Cum
ulat
ive
Perc
enta
ge
TerminationResistance (k)
Rdn+Rdn-
Rup+Rup-
Rup+ Rup-Rdn+ Rdn-
32nm
Transmitter Differential Output Driver
Rup+ Rdn+Rup- Rdn-
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Pseudo-Bandgap Voltage Reference
Slide 31
Low-SupplyPseudo-Bandgap Reference
• Less PMOS mismatch• More systematic PVT
variation which can be removed by calibration
N
VREF
IREF
Classic Low-SupplyBandgap Reference
• PTAT+CTAT with current• Prone to PMOS mismatch
N
VREF
Banba et al., Ref. [7]
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Pseudo-Bandgap Measurements
Slide 32
• Monitor long-L FETs, diodes, resistors, mismatch
0.4 0.5 0.6 0.7 0.8.01.115
102030507080909599
99.999.99
Cum
ulat
ive
Perc
enta
ge Monte Carlosimulation
measured
VREF
(V)
32nm
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Outline
• Background & Motivation• Device-Level Characterization• Circuit-Level Characterization• Circuit Simulator Developments
– VT Measurement– VDmargin Measurement – Macromodel Output Templates
• Conclusions
Slide 33
© Loke et al., Bridging Design and Manufacture of AMS Circuits
ox
depbFBT C
QVVTHV 20
Revisiting the Most Basic of Basics
Slide 34
p-typebody
poly gate
n+
sourcen+
drainp+ bodycontact
VDS
VGS
VBS M O S
Energy Band
Diagram
– – –
+
– – –
– – – – – – – – – – – –
+ + ++ + + ++ + + ++ + + ++ + + ++ + +
–
–– – –
ox
depbFBT C
QVV 2
ss
qb
qsqVT
qs = qb
inversionlayer
© Loke et al., Bridging Design and Manufacture of AMS Circuits
ox
depbFBT C
QVVTHV 20
DSeff
effBDS
t
eff
BSeff
sbi
t
effeff
tw
effeff
seff
BSeffseff
ox
BSeffoxeff
sBSeffsoxT
VDVTPDVTPLL
qTknV
lLDSUB
VETABETA
V
lWLDVT
WDVT
lWLWDVT
WDVT
WWTOXEVBKK
LLPEBK
VKL
LPEBKVKVTHV
1exp10ln
21cosh
0
211cosh
0
11cosh
0
03311
110
0
''
'1
21
BSIM4.6.2 VT Equation – The Band-Aids
Yang et al., Ref. [9]
Slide 35
• Reported in LV9 output template
© Loke et al., Bridging Design and Manufacture of AMS Circuits
• Based on “fundamental” strong inversion criterion• Extended to behaviorally model
– Body effect (VBS < 0 in NMOS, VBS > 0 in PMOS)– Short-channel effect including DIBL– Narrow-width effect– Non-uniform lateral doping – halo implants– Non-uniform vertical doping – retrograded well– LOD effect from STI compressive stress– Well proximity effect from implant mask scattering
• Model late to include new silicon VT dependencies• Impossible to measure in silicon
Please… Physics NOT Math
Slide 36
© Loke et al., Bridging Design and Manufacture of AMS Circuits
drawn
drawnDS L
WIIGST VV
0
• Sweep log IDS vs. VGS at fixed VBS
• Choose VDS depending on region of operation
• Find VGS when IDS crosses user-specified threshold I0normalized to W/L
VGS
log IDShigh VDS low VDS
I0×W/L
VTsat VTlin• Typical I0 ~ 10 to 500 nA• No physical connection to onset
of strong inversion• Be careful when you compare VT
across foundries know their I0
DIBL
Slide 37
Fab Measurement – Constant-Current VT
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Simulating What The Fab Measures
Slide 38
• .OPTION IVTH=val | IVTHN=val1 | IVTHP=val2• Freeze FET node voltages at given instant• Determine VGS for IDS = I0 × Wdrawn / Ldrawn
• Report extracted VT in LX142 output template• VDS limited to VDSMIN (50mV default)• Feature available since HSPICE-2009.09
VD
VS
VBVGVGS = ? forIDS = IVTHN×W/L
IDS
© Loke et al., Bridging Design and Manufacture of AMS Circuits
10-8
10-7
10-6
10-5
10-4
10-3
10-2
0.0 0.2 0.4 0.6 0.8 1.0
I DS
(A)
VGS (V)
VDS = 1.00 V0.05 V
15 µA
VTlin = 305 mVVTsat = 158 mV
Slide 39
Loke et al., Ref. [10]
LX142 Example
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.2 0.4 0.6 0.8 1.0Vo
ltage
(V)
Time (µs)
LX142LV9
VGS
VDS
VDS
VGS
32nm SOI-CMOS, I0 = 300nA
© Loke et al., Bridging Design and Manufacture of AMS Circuits
• Body doping levels have increased by 2-3 orders of magnitude over the decades
• Surface charge density way more conductive at strong inversion condition based on “fundamental” VTdefinition
• Best to treat VT as just a reference point
• IOFF vs. ION plots have become universally more important for reporting device characteristics
Slide 40
M O S
Energy Band
Diagram
ss
qb
qsqVT
qs = qb
inversionlayer
Not So Fundamental After All
ox
depbFBT C
QVV 2
© Loke et al., Bridging Design and Manufacture of AMS Circuits
VDmargin in HSPICE
• Feature recently implemented in HSPICE-2012.06
• LX286 output template• Usage example.IVDMARGIN M3 DELTAGDS=0.2.PRINT DC VDMARGIN(M3)
Slide 41
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Macromodel Output Templates• Models late to capture new silicon observation• Meanwhile, foundries build subckt wrappers
around intrinsic models• Output templates report device characteristics
of intrinsic model BUT what really matters are characteristics of the subckt
• Example– VDS-controlled voltage source in series with gate to
degrade VT and gds for better correlation to observed silicon at process corners
– “DIBL wrapper” took over a year to implement into BSIM4.7
• Co-development with Synopsys R&D in progress to provide subckt output templates
Slide 42
VDS
D’
S’
G’ B’G
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Extending Macromodel Concept• Scaling of conventional planar devices continues to
constrain analog design, e.g., poor gds
– Stronger halo implants for short-channel control– Stricter Lmax from replacement-gate HKMG integration
• More frequent usage of source degeneration to reduce gds
Slide 43
• Really interested in output template of composite device
© Loke et al., Bridging Design and Manufacture of AMS Circuits
Conclusion• Scaling will continue to be more restrictive on AMS• Co-development improves model quality and fab
monitoring of device behavior for AMS designs• Pay attention to details, don’t overlook CAD
Slide 44
technology design
limitations
usage
MODELS
© Loke et al., Bridging Design and Manufacture of AMS Circuits
References
Slide 45
[1] H. McIntyre et al., “Design of the two-core x86-64 AMD “Bulldozer” module in 32 nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 1, Jan. 2012, pp. 164–176.
[2] M. Keating, “Science fiction or technology roadmap: a look at the future of SoC design,” in SNUG San Jose Conf., Mar. 2010.
[3] L. Bair, “Process/product interactions in a concurrent design environment,” in Proc. IEEE CICC, pp. 779782, Sep. 2007.
[4] M. Na et al., “The effective drive current in CMOS inverters,” in IEEE IEDM Tech. Dig., pp. 121–124, Dec. 2002.
[5] D. Fischette et al., “A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O,” in IEEE ISSCC Tech. Dig., pp. 246247, Feb. 2010.
[6] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.[7] H. Banba et al., "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-
State Circuits, vol. 34, no. 5, pp. 670–674, May 1999.[8] A. Loke et al., “An 8.0-Gb/s HyperTransport™ transceiver for 32-nm SOI-CMOS server
processors,” to be published in IEEE J. Solid-State Circuits, vol. 47, no. 11, Nov. 2012.[9] W. Yang et al., BSIM4.6.2 MOSFET Model User's Manual, Regents Univ. California,
Berkeley, CA, 2008.[10] A. Loke et al., “Constant-current threshold voltage extraction in HSPICE for nanoscale
CMOS analog design,” in SNUG San Jose Conf., Mar. 2010.