8/16/2019 Blockages and Halo

1/2

Blockages and Halo

BlockagesBlockages are specified locations where placing cells are prevented or blocked. These act asguidelines for placing standard cell* in the design. Blockages will not be guiding the

placement tool to place standard cell at some particular area, but it won't allow placement

tool to place standard cell at specified locations. This way blockages are act as guidelines to

placement tool.

*Standard cell: standard cell is a group of transistors and interconnects structures that

provides a boolean logic function !e.g. "#, $%, &$%, &"$%, "$T or a storage function

!flipflops or latch.

Types of blockages describes as below,

Soft (Non-buffer) blockage:

(oft blockage specifies a region where only buffer can be placed. That means standard cells

cannot be placed in this region. )t blocks!prevents the placement tool from placing non

 buffer cells such as std. cell in this region.

 

Hard blockage:Hard blockage specifies a region where all standard cells and buffers cannot be placed. )t

prevents the placement tool from placing standard cells and buffers in this region.

Hard blockage are mostly used to

• Block standard cells to certain regions in the design,

•  void routing congestion at macro conners,

• +ontrol power rail generations at macro cores.

•

Partial blockage:The blockage factor for any blockage is -- by default. (o no cells can be placed in that

region, but the fle/ibility of blockages can be chosen by partial blockages.

Placement blockage:

0lacement blockage prevent the placement tool from placing cells at specified regions.

0lacement blockages are created at floor planning stage.

8/16/2019 Blockages and Halo

2/2

0lacement blockage are used to

#efine standard cells and macro* area,

%eserve channels for buffer insertion,

0revent cells from being placed nearer to macros,

0revent congestion near macros.

*Macros: 1acros are intellectual properties that can be directly used in the design. These

are need not to be design. 2or e/ample memories, processor core, 033 etc.

Routing blockage:

%outing blockages block routing resources on one or more layers. )t can be created at any

point in the design.

Halo (keep-out-region):Halo is the region around the boundary of fi/ed macro in the design in which no other

macro or standard cells can be placed. Halo allows placement of buffers and inverters in its

area.

• Halos of two ad4acent macros can be overlap.

• )f macro are moved from one place to another place, halos will also be moved. But incase of blockages if the macros are moved from one place to another place the blockagescan't be moved.