Bit Cell Ratio Testing

Thin CellAdvantages: Smallest possible area of 6T Bit Cell, Can be mirrored (saves area = can reduce distance between n-wells and p-wells)

2by2 Array of Thin Cell LayoutAdvantages: WLs are horizontal, VDD/VSS/BL/BLB are vertical, Mirrored Thin Cells save area and make it easy to add N/P Taps, Easy to Cascade to other 2by2 Arrays

Buffers (First Inv = Min Size, Second Inv = 4x Min)Advantages: Needs to be thin to have 2 Buffers to be smaller than the width of a Thin cell, Easy to souce VDD and VSS, Easily connect inputs and outputs (top and bottom of diagram), Easily N-Tapped, P-Tapped

Word Select (1to2 DEMUX) – Sends Data to ColumnAdvantages: Data comes from top, Address from side (design decision), N-wells together, P-wells together (easy to add N-taps and P-taps), easily mirrored

TX Gates (4x Min Size) – Disconnects BL Drivers, Avoids Fight between Bitcells and BL DriversAdvantages: Outputs nicely spread apart, Select lines are all tied together and come in from side, Inputs from top, Outputs on bottom, Easily N-Tapped and P-Tapped from left or right side, Easily mirrored.

Precharge/BL/BLB GeneratorAdvantages: Pitched Matched (Made it as thin as possible while fitting it in with rest of circuit), BL/BLB are on the outsides running vertically, Easily P-Tapped, N-Tapped, Thin, PRECH, WRITE, and Data Signals

Sense AmpAdvantages: Wanted as short as possible, but width had to be smaller than width of Thin Cell, Similar to Thin Cell by using Cross Coupled Inverter layout, Easily mirrored, Easily P-Tapped, N-Taped

1 SRAM BlockAdvantages: Symmetrical, Pitched Match (All separate components fit in nicely), 1 VDD/VSS source for Bit Cell Array, Can be mirrored, Most inputs, Inputs come in from Left and Top side

Block Pair Merger Schematic

Block Pair Merger

Block Pair

Decoder

Layout Diagram(Connections Removed to Reduce Clutter)