bis application @linac4 and outlook for post ls1
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BIS Application @Linac4 and outlook for post LS1. Maxime Audrain TE-MPE TM, 2014-04-03 On behalf of the TE-MPE-MS Software Team: D. Anderson , M . Dragu , K. Fuchsberger , J.-C. Garnier , A . Gorzawski, M . Koza , K.H. Krol , A . Moscatelli , K.Stamos , P.C . Turcu. Content. - PowerPoint PPT PresentationTRANSCRIPT
M.A - TE-MPE TM - 3rd of April 2014
BIS Application @Linac4 and outlook for post LS1
Maxime AudrainTE-MPE TM, 2014-04-03
On behalf of the TE-MPE-MS Software Team:D. Anderson, M. Dragu, K. Fuchsberger, J.-C. Garnier, A. Gorzawski,
M. Koza, K.H. Krol, A. Moscatelli, K.Stamos, P.C. Turcu
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Content
Status of BIS in operation during LS1
BIS software for the restart
Wishes and Vision
Summary
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Architecture overview
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Introduction
BIS hardware changes involve a follow-up on the software side. RIO3 not supported by CO, running out of spares, Migration to MEN A20 controller involves defining a new driver
for the communication from the FESA classes to the board registers.
At the same time, provide monitoring for new hardware and operational deployments during LS1.
Focusing on clean-up and unification during LS1 to ensure increased maintainability until BIS2 is specified.
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Status of BIS in operation during LS1
Status of BIS in operation during LS1
BIS software for the restart
Wishes and Vision
Summary
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BIS@LN4, Hardware status
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Courtesy: Bruno Puccio
Already installed
To be installed E.T.A End of April
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BIS@LN4, Driver
Encore 2 (DriverGen3 version 2) driver deployed :
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Pros : generate the driver from the Hardware type defined in the CCDB,
Cons : no versioning (one hardware definition per driver type).
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BIS@LN4, FESA
Old “Bic” FESA class is deprecated: Unused properties, deprecated functionalities (old History
Buffer), lot of redundancies,
“New” (since 2011) CIB FESA class in version 2.10 Initially defined for the new deployments with Linux controller
in the LN4 and PSB, Reduced number of properties -> easier to maintain, Validated during the last 3 years, “Generic” -> support specificities from board types
(CIBM/CIBX/CIBDS boards handled by one FESA class).
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BIS@LN4, GUIs – BIS supervisor
Refactored version of the old LHC/SPS/TL BIS supervisor,
Cleaned, no deprecated functionalities, expert oriented,
But not adapted for cyclic machines (LN4, PSB, TL, SPS).
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BIS@LN4, GUIs – Cycle BIS GUI
A generic monitoring GUI for cyclic machines,
Plot per cycle/per channel, with time markers,
Filtering per masked, disabled and interlocking inputs (more will come).
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CIBDS, Hardware status
Additional asynchronous beam dump trigger to the LBDS,
First version in the LAB, will be installed in point 6 for LBDS reliability dry-run (April).
M.A - TE-MPE TM - 3rd of April 2014Courtesy: Stéphane Gabourin
More info
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CIBDS, Driver / FESA / GUI
Hardware type defined in the CCDB: Driver generated, deployed and running in the LAB, Follow-up HW deployment in point 6 (April),
CIB FESA class modified to allow communication with the CIBDS board: Added a board type that links to a driver type and
enable/disable properties depending on this board type.
GUI to be defined at a later stage.
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Summary of the current status
3 Driver types: CIBM -> handles CIBM/CIBX boards CIBG, CIBDS -> CIBG/CIBDS boards
2 FESA classes: CIB -> handles CIBM/CIBX/CIBDS boards CIBG -> handles CIBG board
2 GUIs for Linac 4 and PSB: BIS supervisor Cycle BIS GUI
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BIS software for the restart
Status of BIS in operation during LS1
BIS software for the restart
Wishes and Vision
Summary
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Priorities qualification
mandatory for BIS operation after LS1,
highly recommended for BIS operation after LS1,
Can reuse/recycle functionality from previous/other GUIs!
Functionality already provided!
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Hardware changes
LynxOS to Linux migration: Change 33 FEC controllers, Reprogram VME interface on 58 CIBM/X & 7 CIBG.
Installation: SPS in April, Transfer lines and LHC this summer.
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Drivers
Regenerate CIBG driver using new driver version (Encore 2),
Deploy the 3 driver types on all related FECs.
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FESA
CIB FESA class will stay with version 2.10. Reuse PM property to allow PM data push in case of PM trigger, Inform users of class change (LHC Sequence, SIS).
CIBG FESA class (2.10) to adapt to a Linux controller: Plug the class to the Encore driver, Failing rearm issue (delay between A and B loops) to be followed
with Verena, Will be done in the following weeks to be ready for the LBDS
reliability run.
Deploy the 2 classes types on all related FECs.
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BIS GUI - harmonization
Merge functionalities from our current BIS applications into one central application: The minimum: harmonized and
cleaned application, BIS monitor functionalities to be
merged (follow-up with Jorg), Other non BIS related
functionalities to be moved to Fabio Follin application.
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BIS GUI – main tasks
Define more filters for device monitoring (per accelerator, beam, location, etc…)
Statuses : list of current interlocks, hidden interlocks and masks
Commands : executing any command on 1..N BICs
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BIS GUI prototype - overview
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BIS GUI prototype – cyclic monitor
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BIS GUI prototype – static monitor
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BIS GUI prototype – statuses
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BIS GUI prototype – commands
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Pre-Current-Post operational checks
DIAMON checks have to be defined ASAP! No control on the implementation of the checks (we only
provide specifications), pros are no additional software to maintain, cons are that it might need several iterations to make it right,
Set communication between hardware guys and DIAMON guys.
Pre-operational checks (sequencer) needs to be reviewed and adapted to the change of the FESA class,
Post-operational checks (PM modules) : same hardware as pre-LS1, same PM Buffers, only need to commission the analysis modules.M.A - TE-MPE TM - 3rd of April 2014
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Wishes and Vision
Status of BIS in operation during LS1
BIS software for the restart
Wishes and Vision
Summary
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Wishes !
Operators wishes : Input masked by who, when and why! Information on how to resolve in case of an interlock
(application link, procedure, etc…),
Use the analysis language to perform pre-operational checks,
A common server for SMP and BIS Providing information for all applications at CERN (Beam
permit flag, decoding information, etc…).
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Vision – Board specifications
A single source for board specifications: Providing information on board and registers, how to decode
them and which commands can be performed.
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Register decoding module (JAVA)
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Vision - FESA
Abstract our FESA classes to avoid code duplication: Might be provided by FESA3 after the LS1
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Summary
Status of BIS in operation during LS1
BIS software for the restart
Wishes and Vision
Summary
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Main tasks
Deploy drivers and FESA classes, Add PM property, inform users of class changes,
BIS GUI available for all accelerators and all roles, Add statuses and commands panels,
DIAMON checks specification have to be defined ASAP!
Pre-operational checks to be adapted to the new FESA class.
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Planning
3 sprints starting from the 23rd of April until the 19th of June -> BIS software layers ready for SPS ring commissioning,
A few sprints depending on priorities for Transfer lines and LHC integration in the application,
Probably not many more dedicated sprints before the restart : time has to be shared with other projects.
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Thank you for your attention
Do you have any questions?
M.A - TE-MPE TM - 3rd of April 2014