biltbuilt-ir ialiin repair analysis · 2010-11-01 · previous works 4. summary 1/ 38. 1. ra 2....
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Contents
1. RA
2. BIRA
1. RA
3. Previous Works
4. Summary
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1. RA
2. BIRA
1. RA
3. Previous Works
4. Summary
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Repair
What is Repair ?Replacing a faulty cell with a healthy redundant cellReplacing a faulty cell with a healthy redundant cell
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RA (Redundancy Analysis)
What is RA (Redundancy Analysis) ?Finding address information to be repaired for each spare nd ng dd n o on o p d o h pline
C1: 4 C2: 5Column address
R
1:3
Row address
R2:
-Row address
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Spare Architecture (1)
Bit spare architecture- PPR (Post Package Repair)R ( o k g R p )
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Spare Architecture (2)
1D line spare architecture- Some simple SoCo p o
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Spare Architecture (3)
2D line spare architecture- Most of high density memorieso o h gh d n y o- Difficult RA
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Fault Classification
Three types of faults
RS (CS): # of row (column) spares. k: # of repetitive faults on a line.
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p
Observations on RA
Observation 1A single fault can be replaced with either a spare row or spare A ng n p d h h p o o p
column.
Observation 2Observation 2A sparse faulty row (column) line can be replaced with a spare row
(column). However, it can also be replaced with several spare columns (rows) according to the number of available sparescolumns (rows) according to the number of available spares.
Observation 3A t i f lt ( l ) t b l d ithA must-repair faulty row (column) must be replaced with a spare row
(column) line.
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RA Classification
Three types of RA- Fault storing spaceo ng p
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RA Example
0 1 2 3 4 5 6 7 C0 C1F lt
X XX X
X X
0123
R0R1
Faulty cell
2 Column spare lines
XX
4567
R0
R1C0C1 2 Row spare
R0R1
C1
Failure bitmap Repair solution
ow sp elines
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RA Example
0 1 2 3 4 5 6 7 C0 C1
X XX X
X X
0123
R0 1R1 3
XX
4567
R0
R1 3C0 4C1 6 R0
R1C1 6
Failure bitmap Repair solution
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1. RA
2. BIRA
1. RA
3. Previous Works
4. Summary
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BIRA vs. BISR
BIRA: Built-in Repair Analysis (b, c)p y ( , )
BISR: Built-in Self Repair = BIRA (b, c) + Soft repair (d)
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HistoryRM(1984),B&B (1986)RA algorithm
Cresta(2000)
BIRA
LRM, ESP, LO(2003)
(2000)
IntellignetSolve(2007)
SFCC (2009)
BRANCH (2010)
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Key Features of BIRA
AreaOverhead
RepairRate
AnalysisTime
GoodGood
Bad
ESP, LRM CRESTA IntelligentSolveFirst
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Classification by features
RepairRateRate
Non-optimal Optimal
Low AreaOverhead
Parallel Analyzer
SingleAnalyzer
ESP CRESTAIntelligentSolveFirst
SFCC BRANCH
High area Low area
LRM
Low areaHigh analysis speed
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Middle area
Repair Rate
Optimal repair rate p p= 100% of normalized repair rate= Always find solutions if exists
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RA for single (sparse) Fault
Single faultg
Can be repaired by either a row or a column
Requires at least one spare line
Repairble if # of single faults ≤ # of available Repairble if # of single faults ≤ # of available spares
Repairable if # of Maximum sparse faults
2*R *C= 2*RS*CS
Where, R (C) is # of row (column) spares
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RA for Must-repair
Must-repairp
Do not need to be analyzed
Requires one spare line
# of must-repair ≤ # of available spares # of must-repair ≤ # of available spares (# of single faults + # of must-repair) ≤ # of available
spares
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Binary Search Tree
# of branches in a tree= (RS+CS)! /(RS!*CS!)S S S S= (2+4)!/(2!*4!) = 15
where, RS: # of rowsCS: # of columns
# of nodes in a branch= (RS+CS) = (2+4) = 6
branchbranch
node
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1. RA
2. BIRA
1. RA
3. Previous Works
4. Summary
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RM(Repair Most [1984])
F t b t N ti l i ffi iFast but, Non-optimal repair efficiency.
Not searching all cases.
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LRM(Local Repair Most [2003])
Local bitmap scheme.The size of bitmap depend on the defect distribution.Non optimal repair efficiency
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ESP(Essential Spare Pivoting)
Non optimal repair efficiency but smallest area overhead
Fail address comparing d th l dd i
Fail addressF BIST
Post RA processing block
During test sequences running After finishing test sequences
and orthogonal address saving
ress
From BIST
1 13 3
time Orthogonal
addressEssential
flagX X
X XX X
0123
0 1 2 3 4 5 6 7 8 9 10 11 12 13 C0 C1
1 13 32 7on
al a
ddr
구분
3 32 76 71 5
1 01 01 1
flag
d of
RA
X X
X
X
34567892 7
9 9
( ) f il ddOrt
hogo3 5
2 99 9
1 10 1 En
d X910111213R0R1(a) fail address save area
Orthogonal address : address has different x, y address against previous orthogonal addresses
R1
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orthogonal addresses first address is orthogonal address
CRESTA(Comprehensive Real-time Exhaustive Search Test and Analysis)
Implementation the entire searching treeOptimal repair rate & fastp pHigh area overhead
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How to RA on CRESTA
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 C0 C1 Fault Row Col.1st 1 1
< Policy >1. Compare with pre-
X XX X
X X
X
0123456
1 1 12nd 3 33rd 2 74th 6 7
p plogged address
2. If there is no same address then update
dd lX
X
6789101112
4th 6 75th 1 56th 3 57th 2 9
new address else skip.
3. If there is no more spaces to log, it is not 12
13R0R1
7th 2 98th 9 9
p g,a correct solution.
R0 1
R1 3
R0 1
C0 3
R0 1
C0 3
C0 1
R0 3
C0 1
R0 3
C0 1
C1 3
C0 7
C1 9SubSub--analyzeranalyzer
R1 2
C1 7
C1 7
R1 3
R1 2
C1 7
C1 7
R1 1
R0 2
R1 6SubSub--analyzeranalyzer SubSub--analyzeranalyzer SubSub--analyzeranalyzer SubSub--analyzeranalyzer SubSub--analyzeranalyzer
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SubSub analyzeranalyzer#1#1
SubSub analyzeranalyzer#2#2
SubSub analyzeranalyzer#3#3
SubSub analyzeranalyzer#4#4
SubSub analyzeranalyzer#5#5
SubSub analyzeranalyzer#6#6
IntelligentSolve(First)
Single RA analyzerSequential analysis (node by node) with must-repair skipq y ( y ) p pOptimal repair rateNot fast
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SFCC(Selected Fail Count Comparison)( p )
Building binary search tree based on line faultsmust-repair skipp pAnalyze by comparison of fail count of linesOptimal repair rate and fast
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SFCC1) Repairable if (SFC >= (TFC- unused line counts)),2) Repairable if (SFCR >= (TFC- unused line counts)),
where TFC : total fail count of sparse faultswhere, TFC : total fail count of sparse faultsSFC : sum of fail counts of most-failsSFCR : SFC – interchanging fail count each other
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BRANCHSingle RA analyzerBased on ESP but optimal repair rateComaparing Parent (Orthogonal) vs. Child (non-orthogonal)p g ( g ) ( g )Analyze Faster (parallel comparison of all nodes in a branch)
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BRANCH
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Result – area(fault saving area calculation only)
3000CRESTA
2500 LRM ESP INTELSFCC
1500
2000
of b
its]
SFCC BRANCH
1000
1500
Area
[# o
500
0 1 2 3 4 5 6 7 8 9 10 11
Column spares (Cs)
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Result – area(fault saving area calculation only)
180001900020000
30001700018000
CRESTALRM
2000
2500
of b
its]
LRM ESP INTELSFCC
1500
Are
a [#
o SFCC BRANCH
500
1000
64x64 128x128 256x256 512x512 1024x1024 2048x20480
M i [M N]
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Memory size [MxN]
Result – Repair rate
95100105
808590
rate CRESTA
RM (LRM )
657075
d R
epai
r r RM (LRM max.) ESP INTELSFCC
50556065
orm
aliz
ed SFCC BRANCH
35404550
No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 183035
Random faults [ea]
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Random faults [ea]
Result – Analysis Speed
1000
1100
1200
RM (LRM )
800
900
1000 RM (LRM max) INTEL SFCCBRANCH
600
700
cycl
es
BRANCH
300
400
500
Clo
ck c
100
200
300
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0
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Random faults [ea]
Result – Overall Performance
180
200 IntelligentSolveFirst
140
160
cycl
es
80
100
120
ecut
ion
c
40
60
80
BRANCH
SFCC
RA
exe
05
10
0
20
1 5%2.0%
2.5%3.0%
BRANCHIdeal BIRA
ed Spares
St 1520
2530
35 0 0%0.5%
1.0%1.5%
of Over-u
sedStorage requireme
CRESTA
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35 0.0%
Rate oments
Summary
Complexity of RA depends onS hit t d # f Spare architecture and #of spares
Area overhead depends on Spare architecture, #of spares and kind of BIRA
To achieve optimal repair rate,p p ,All sparse faults must be stored by using single RA analyzer
To enhance analysis speed,To enhance analysis speed,reducing binary search tree, parallel operation, etc.
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