bhaskar
TRANSCRIPT
Transformer-less Inverter topologies for grid
connected solar PV Applications
M.Tech. Dissertation
Submitted in partial fulfillment of the requirements
of the degree of
Master of Technology
in
Energy Systems and Engineering
By
Annepu Vivek
(Roll No : 133170015)
Under the guidance of
Prof. B. G. Fernandes
Dept. of Electrical Engineering
Department of Energy Science and Engineering
Indian Institute of Technology Bombay
June 2015
Dedicated to
My Mother, Father and my Sister
Acknowledgment
I wish to thank the Department of Energy Science and Engineering at Indian In-
stitute of Technology Bombay for providing with this opportunity to pursue my M.Tech.
I express my sincere gratitude towards my guide Prof. B. G. Fernandes for the con-
tinuous guidance and encouragement he provided during my project work.
I would like to thank Mr. Ch. Anand Babu who shared his knowledge for the com-
pletion of this project. I thank Chakridhar, Om Sekhar, Ashok for being such wonderful
batchmates. I, also thank my seniors B. H. Varun, P. Manikanta, S. Rohit whose influence
on me would remain for long. I thank Lab Assistant Mr. A. Khandekar for his sugges-
tions while setting up the hardware. I thank Muni, Vijay, Nanditha, Pratik, DC and all
others who made my stay at IIT Bombay a memorable one. Fianlly, I thank Mr. V. V.
S. Pradeep Kumar whose encouragement and support i never forget and Mr. H. S. V. S
Kumar Nunna for mentoring me during the initial phases of my campus life.
Vivek Annepu
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M. Tech. Dissertation Approval Sheet
This is to certify that the dissertation titled “Transformer-less Inverter Topolo-
gies for Grid Connected Solar PV Applications” submitted by Mr. Annepu
Vivek(Roll No. 133170015) is approved for the award of degree of Master of Technol-
ogy in Energy Systems Engineering.
Supervisor:
Internal Examiner:
External Examiner:
Chairman:
Date: 29 - June - 2015
Place: IIT Bombay, Mumbai.
ii
Declaration
I declare that this written submission represents my ideas in my own words and where
other’s ideas or words have been included, I have adequately cited and referenced the orig-
inal sources. I also declare that I have adhered to all principles of academic honesty and
integrity and have not misinterpreted or fabricated or falsified any idea/data/fact/source
in my submission. I understand that any violation of the above will be cause for disci-
plinary action by the institute and can also evoke penal action from the sources which
have thus not been properly cited or from whom proper permission has not been taken
when needed.
Vijay Bhaskar
Date: 29 - June - 2015
IIT Bombay, Mumbai
Maharashtra - 400076
iii
Abstract
Distributed energy resources make the grid sustainable. Unlike the conventional grid-
tied inverters, transformer-less inverter do not have any provision for energy storage. This
makes a Transformer-less system less costly with high efficiency and energy density. But,
eliminating a transformer results in high ground leakage currents due to the effect of PV
stray capacitance between the panel and ground. Leakage current results in very high
EMI, causes safety issues to the operating personnel. Hence, transformer-less inverters
are designed to eliminate leakage current and its effect. In this report, an extensive liter-
ature survey of single stage transformer-less voltage source inverters is covered. Various
topologies are classified on the basis of their circuit configuration. A simplified model for
a H-Bridge inverter system is developed to identify the source for leakage current and thus
generalized for all the topologies. Also, basic transformer-less system is analyzed taking
the non-ideal factors like junction capacitance of the switching devices and circuit dead
time into account and their effect on the leakage current. In this point of view, some of
the popular inverter topologies are analyzed and the root cause (and a solution) is iden-
tified. Finally, an improved neutral point clamped transformer-less topology (Improved
NPCTLI) is developed to address these issues on leakage current. Firstly, the presented
theory is demonstrated by thorough simulations. Secondly, A 1 kW generalized hardware
prototype is designed and developed to validate the topologies - H5, oH5, HERIC and
Improved NPCTLI. Finally, a comparative analysis is carried out on the basis of their
common mode characteristics and efficiency.
Contents
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Annual PV capacity additions . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Grid Integration through the power electronic interface . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization of the Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Overview of Grid Connected Transformer-less System 4
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 A Transformer-less grid connected PV system . . . . . . . . . . . . . . . . 4
2.2.1 PV stray capacitance, Cpv1, Cpv2 . . . . . . . . . . . . . . . . . . . . 5
2.2.2 EMI filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.3 Ground leakage current . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Leakage current analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Overview of grid connected transformer-less system . . . . . . . . . . . . . 11
2.4.1 Topologies derived from full-bridge inverter . . . . . . . . . . . . . . 11
2.4.2 Topologies derived from Full Bridge inverter . . . . . . . . . . . . . 13
2.4.3 Topologies derived the from the Half-bridge inverter . . . . . . . . . 15
2.5 Limitations of the study . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 An Improved Neutral-point Clamped Transformer-less Inverter 20
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Analysis of optimized H5 (oH5) Inverter . . . . . . . . . . . . . . . . . . . 20
3.2.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 Operation of Clamping branch . . . . . . . . . . . . . . . . . . . . . 23
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3.2.3 Effect of dead time on Common Mode Voltage . . . . . . . . . . . . 24
3.2.4 Improved transformer-less Inverter . . . . . . . . . . . . . . . . . . 26
3.2.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Hardware Implementation 32
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Selection of DC link Capacitor . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Design of output Filter . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.3 Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.4 Level Shifting Stage/ Buffer Circuit . . . . . . . . . . . . . . . . . . 35
4.2.5 Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.6 Measurement of leakage current . . . . . . . . . . . . . . . . . . . . 36
4.3 Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 Grid Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.2 Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.3 Block Diagram of the Control Scheme . . . . . . . . . . . . . . . . . 41
4.4 Hardware Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.1 H5 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4.2 Highly Efficient and Reliable Inverter concept (HERIC) . . . . . . . 43
4.4.3 Optimized H5 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4.4 Improved NPC Transformer-less Inverter . . . . . . . . . . . . . . . 47
4.5 Efficiency Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 Conclusion 55
Appendix 56
References 56
6 Appendix 56
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List of Figures
1.1 A Single phase grid connected system . . . . . . . . . . . . . . . . . . . . . 2
1.2 A Single phase transformer-less grid connected system . . . . . . . . . . . . 2
2.1 A Full bridge transformer-less inverter system . . . . . . . . . . . . . . . . 5
2.2 Schematic of a roof top installation along with parasitic capacitance [6] . . 6
2.3 EMI filter configuration (a) L filter (b) LC (c) LCL filter 1 (d) LCL Filter 2 7
2.4 A simple Full-bridge transformer-less system . . . . . . . . . . . . . . . . 8
2.5 Equivalent model using voltage sources step 1 & 2 . . . . . . . . . . . . . . 9
2.6 Equivalent model using voltage sources in Step 3 . . . . . . . . . . . . . . . 9
2.7 Equivalent model using voltage sources (a) Step I (b) Step II . . . . . . . . 10
2.8 Leakage current characteristic for a Bipolar PWM operation . . . . . . . . 11
2.9 Voltage across the PV stray capacitance in UPWM inverter . . . . . . . . 12
2.10 FFT analysis for (a) Bipolar PWM (b) Unipolar PWM . . . . . . . . . . . 13
2.11 HUPWM: Voltages across PV stray capacitance to ground . . . . . . . . 13
2.12 H5 Topology by SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13 HERIC Topology by Sunways . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.14 Common mode and differential characteristics of a HERIC inverter . . . . 15
2.15 A Full bridge Zero Voltage rectifier based transformer-less inverter . . . . . 16
2.16 FB-ZVR: common mode and differential mode characteristics . . . . . . . 16
2.17 Classification of transformer-less voltage source inverters . . . . . . . . . . 18
2.18 H6 inverter with DC bypass and Neutral point clamping . . . . . . . . . . 19
2.19 H6-DCBP: common mode and differential mode characteristics . . . . . . 19
3.1 An optimized H5 Inverter topology . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Switching strategy for oH5 topology . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Mode I : vg, ig > 0;S1, S4, S5 −ON . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Mode II : vg > 0, ig > 0;S2, S6−ON . . . . . . . . . . . . . . . . . . . . . 23
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3.5 Operation Modes of oH5 Inverter (a) Mode III (b) Mode IV (c) Clamping
through S6 (d) through D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Resonant circuit for (a) Differential mode for vAN > vBN (b) Common
mode for vAN = vBN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Circuit for Improved oH5 Inverter topology . . . . . . . . . . . . . . . . . . 26
3.8 Impedance(Z) vs Frequency (f) plot for H5, oH5, HERIC Inverters . . . . 28
3.9 Simulated waveforms for H5 topology: Zoomed view of vAN and vBN . . . 29
3.10 Simulated waveforms for improved H5 topology: Zoomed view of vAN and
vBN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11 Simulated waveforms for oH5 topology (a) Variations in CMV along with
vAN , vBN and (b) Waveforms for vAB, vg, 20× ig and iCM . . . . . . . . . 30
3.12 Simulated waveforms for Improved oH5 topology (a) Variations in CMV
along with vAN , vBN and (b) Waveforms for vAB, vg, 20× ig and iCM . . . 31
4.1 Circuit layout for experimentation . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 1 KW Hardware Setup for a transformer-less system 1) Programmable
DC supply, 2) DC link capacitors, 3) Generalized Power PCB, 4) Sens-
ing board, 5) Driver circuit, 6) Regulated DC power supplies, 7) Filter
inductors, 8) Auto-transformer (grid), 9) Controller : TMS320F28335, 10)
Level shifter(Buffer circuit with pull-up resistor) . . . . . . . . . . . . . . . 33
4.3 Simple Block diagram of phase locked loop (PLL) . . . . . . . . . . . . . . 37
4.4 Phase detector of enhanced phase locked loop (EPLL) . . . . . . . . . . . . 38
4.5 Frequency response of an Ideal P+R controller with compensation . . . . . 41
4.6 Closed loop current control scheme for a single phase PV based grid-tied
inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7 Differential and Common-mode characteristics of H5 topology, vAN(200V/div),
vBN(200V/div), vCM , vg (200V/div), ig (5A/div) . . . . . . . . . . . . . . 43
4.8 H5: Zoomed view of vAN(200V/div), vBN(200V/div) showing the oscilla-
tions during the free-wheeling period . . . . . . . . . . . . . . . . . . . . . 44
4.9 H5: Inverter output voltage, vAB (200V/div), and the leakage current iCM
(100 mA/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.10 H5: FFT analysis of the leakage current, FFT(iCM), 1mA/div . . . . . . 45
4.11 HERIC: Inverter pole voltages, vAN & vBN (200 V/div) CMV, vg(200V/div),
ig(5A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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4.12 HERIC Inverter: Oscillations performed by the pole voltages during the
transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13 HERIC Inverter: Differential voltagevAB(200V/div),leakage current, iCM(50mA/div),
Grid voltage, vg(200V/div), grid current, ig(5A/div) . . . . . . . . . . . . . 46
4.14 HERIC: FFT Analysis for the leakage current of (iCM = 1mA/div) . . . . 47
4.15 oH5 Inverter: Pole voltages, vAN & vBN (200 V/div) CMV, vg(200V/div),
ig(5A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.16 oH5 Inverter: Zoomed waveforms of Variations in CMV along with vAN ,
vBN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.17 oH5 Inverter: Differential voltagevAB(200V/div),leakage current, iCM(50mA/div),
Grid voltage, vg(200V/div), grid current, ig(5A/div) . . . . . . . . . . . . . 48
4.18 oH5 InverterFFT analysis of the leakage current iCM , 1 mA/div . . . . . 49
4.19 Improved NPCTLI: Pole voltages, vAN & vBN (200 V/div) CMV,
vg(200V/div), ig(5A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.20 Improved NPCTLI: Voltage distribution across the DC link capacitors,
CDC1, CDC2, VON (200v/div) . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.21 Improved NPCTLI: FFT analysis of the leakage current iCM , 1 mA/div 50
4.22 Improved NPCTLI: FFT analysis of the leakage current iCM , 1 mA/div 51
4.23 Efficiency comparison for H5, HERIC, oH5 and Improved NPCTLI . . . . 54
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List of Tables
2.1 Standards based on VDE 0126-1-1 . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 The Equivalent Resonant circuits with their resonant frequency . . . . . . 28
3.2 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Hardware Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 Device specifications and losses at rated power . . . . . . . . . . . . . . . . 53
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Chapter 1
Introduction
1.1 Background
The Renewable Industry (especially PV) experienced a very large growth compared to the
fossil fuels in the last fifteen years [1]. Due to the increasing demand, there is a huge deficit
in power which led to the exploration of new and renewable forms of energy. Wind, Solar,
biomass are some of the cleanest energy resources available in the earth’s atmosphere. The
renewable forms of energy are less reliable and the extraction methods are not efficient.
The highest conversion efficiency achieved for a solar cell is approximately 40%. One
should ensure that this energy generated has been utilized to the fullest. Maximum power
point tracking (MPPT) is done to extract maximum power available at a particular time
in a day. Also, the solar power available through PV is not suitable for direct use. Power
electronic converter helps convert the power according to the requirements.
1.1.1 Annual PV capacity additions
Most of the installations are from Germany and Italy. But only 0.2% of electricity gen-
eration is from PV. Around 80% of the global demand is from the European market [2].
Apart from these two countries, the major emerging markets are China, the Middle East,
South Korea, India and other Southeast-Asian countries.
1.1.2 Grid Integration through the power electronic interface
:
In the early 90’s, most of the applications (telecommunications, rural electric supply)
used to get the power from the stand-alone PV systems. And there are a lot of grid
1
connections available. The reduction in the overall cost of the system has led to such
a change. The grid connection is possible only through a DC to AC converter which
supports the interconnection of the distributed generation systems, storage elements, and
renewable energy systems to the electric power system.
Grid converter is mainly a semiconductor based circuit technology which inverts the
incoming signal (i.e., AC-DC and DC-AC). The rise in power demand has led to the
creation of new control methods to achieve more voltage levels leading to much more
complex topologies [4]. For example, a normal H-Bridge converter modified to multilevel
converters or interleaved structures etc.
1.2 Motivation
The power electronics convert the available power to the desired stage and it involves
various stages (Fig. 1.1):
1. Source conversion stage (Solar to Electric energy through PV modules)
2. Maximum power point tracking and DC-DC conversion stage
3. DC-AC conversion stage (Standalone/ Grid-tied mode)
Figure 1.1: A Single phase grid connected system
As the no. of stages increase, the size and cost of the system goes up. Also, the overall
efficiency of the system gets degraded. If the available PV string voltage is in the range of
(340−700)V , A single stage conversion is sufficient. Transformer-less inverter connections
(Fig. 1.2) offer high energy density with reduced cost and improved efficiency as the cost
of transformer costs around(14
)thof the total system cost [3].
Figure 1.2: A Single phase transformer-less grid connected system
2
1.3 Objective
Although the transformer-less grid connection has many benefits, they are limited by
inherent leakage current causing electric shocks to the operating personnel, DC current
injection into the grid frequent tripping of residual current monitoring units (RCMUs)
blocking the PV source from feeding the grid [5]. The objectives of my project are:
1. To study the effects of the circuit parasitics which influence the common mode
voltage(CMV) and hence the leakage current.
2. To develop a transformer-less topology which addresses the leakage current issue by
maintaining constant CMV.
1.4 Organization of the Report
The organization of the report is as follows:
Chapter 2 discusses various transformer-less inverter topologies presented in the literature.
A simplified leakage current model is developed based on a H-Bridge transformer-less
system where, mathematical expressions are derived for the common mode voltage (CMV)
and its effect on the leakage current is discussed.
In Chapter 3, The dead time and the switch capacitance effects are discussed in detail
and a new method to suppress them is identified. Simulation studies are done to validate
the effectiveness of the method
Chapter 4 deals with the hardware implementation to validate the simulations and
the results
Finally, Chapter 5, concludes the report by summarizing the observations and results
along with the future scope of study.
3
Chapter 2
Overview of Grid Connected
Transformer-less System
2.1 Introduction
In this chapter, a single-stage grid connected voltage source based transformer-less system
for PV applications is introduced. Based on the model developed, expressions for the
common-mode voltage and leakage current are derived and few popular topologies to
address this leakage current issue are discussed.
2.2 A Transformer-less grid connected PV system
AC-DC converters are classified based on their power rating:
1. Micro-inverters (< 200 W )
2. String inverters (0.5− 6.5 kW )
3. Mini-central/ Multi-string inverters (< 15 kW )
4. Central inverters (> 15 kW )
Single phase transformer-less inverter falls into the category of String inverters. A
Single phase full bridge based transformer-less topology is shown in the Fig. 2.1 where
L1 and L2 are filter inductors placed on both the output phases of inverter. The choice
of filter made is elaborated in the next section. Assumptions are made in a way that
there is enough PV string voltage available at input side. The PV stray capacitance is
4
denoted by CPV 1 and CPV 2 and the leakage current which is produced by a very fast
varying voltage(∼ kHz) across the stray capacitors is denoted by iCM .
Figure 2.1: A Full bridge transformer-less inverter system
Fig. 2.1 shows a PV based grid connected transformer-less inverter system. The various
components of this system are listed below:
1. Large PV string with the operating voltage range (300− 700)V hence no dedicated
boosting stage on the input stage
2. Inverter which converts available DC input to AC output
3. EMI Filter
4. PV stray capacitance Cpv1 and Cpv2
2.2.1 PV stray capacitance, Cpv1, Cpv2
The PV panel comes with a metallic frame which when charged by an external voltage
signal, the metallic frame forms a capacitance with ground as the other surface and air as
dielectric. So, the stray capacitance which when energized with a high frequency signal
allows a significant current to pass through it. The capacitance CPV is calculated using
the following relation:
Cpv1, Cpv2 = εoεrAcd
(2.1)
From the above equation, this value of capacitance depends on various factors like the
total surface area of the PV panel and its frame, distance between the layers, dust and
humidity :
5
Figure 2.2: Schematic of a roof top installation along with parasitic capacitance [6]
• C1 is the capacitance due to a layer of water (Fig. 2.2)
• C2 is the capacitance through the grounded frame
• C3 is through the roof surface area
The typical values of the capacitance varies from 60 nF/kW on a normal dry day to
110nF/kW on a rainy day. These values are applicable for Crystalline silicon PV panels.
2.2.2 EMI filter
EMI filters are used to block the high frequency component to avoid interference either
conductive or radiative. These filters ensure the current and voltage after the filter to be
sinusoidal. A variety of filter configurations are used for grid connected applications [7].
Traditional L filter is replaced by LC and LCL filters (Fig. 2.3) which are independent of
grid distortions [11]. Also, they provide high stability due to the addition of a pole on the
left hand side of S-plane and harmonic rejection capability. But according to the circuit
topology and modulation scheme, the filter configuration is chosen carefully.
2.2.3 Ground leakage current
In the above system discussed, there is no galvanic isolation due to the absence of a
transformer. As a result, the grid neutral is directly connected to the PV panel grounding.
The voltage near the PV terminals to ground vary at a very high frequency. This frequency
is determined by the resonant circuit formed by the PV parasitic capacitance to ground
and the cables. Due to this large variation in voltage, a very high current flows through
6
Figure 2.3: EMI filter configuration (a) L filter (b) LC (c) LCL filter 1 (d) LCL Filter 2
the system. This may cause electric shocks to the operator [8], [9]. The presence of high
leakage currents cause EMI, frequent tripping of inverters, additional system losses, grid
current distortion etc.
Limits of leakage current for safer operation
According to the German standards, V DE0126−1−1, the leakage current limits for nor-
mal operation of the inverter are given in Table. 2.1 [10]. It also suggests the installation
of residual current monitoring units (RCMUs) and the system should be disconnected
from the grid within 0.3 s after the rise
Table 2.1: Standards based on VDE 0126-1-1
Value of current Break time4icm > 30mA 0.3s4icm > 60mA 0.15s4icm > 100mA 0.04s
2.3 Leakage current analysis
A transformer-less inverter topology is derived to limit the leakage current. The leakage
current is estimated using an equivalent model of the system. From Fig. 2.1, i1 and i2
7
are the currents flowing through L1 and L2. The inductance of the grid is neglected.
vCM , vDM represents the common mode voltage (CMV) and the differential mode voltage
(DMV) of the inverter and are given by:
Figure 2.4: A simple Full-bridge transformer-less system
vDM = vAN − vBN
vCM =vAN + vBN
2
(2.2)
Similarly, the currents are
iCM = i1 + i2
iDM =i1 − i2
2
(2.3)
Where, vAN and vBN are the inverter pole voltages varying with switching frequency.
From Eq. 2.2 and 2.3,
vAN = vCM +vDM
2; vBN = vCM −
vDM2
i1 =iCM
2+ iDM ; i2 =
iCM2− iDM
(2.4)
The inverter pole voltages vAN and vBN are pulsating in nature. As a result currents
i1 and i2 are forced through L1 and L2 respectively. The equivalent circuit is shown in
Fig. 2.5 shows the most important components of the system considered in this analysis.
• L1 and L2 are filter inductors in which the current is controlled
• Lg is the inductance of the grid and is neglected as Lg << L1(L2)
8
Figure 2.5: Equivalent model using voltage sources step 1 & 2
• CAG and CBG are the parasitic capacitances between inverter output and the ground
All other parasitic effects are neglected for this analysis. For safety reasons, the grid
neutral is directly connected to the grounded aluminum frame.
The voltage vK at the node ‘K’ is expressed by,
vK = vAG −1
2vDM
= vBG +1
2vDM
(2.5)
The voltage difference of the parasitic capacitors of the heat sink (CAG, CBG) is zero
and do not attribute to leakage current. Hence, the loop is removed. The circuit is
Figure 2.6: Equivalent model using voltage sources in Step 3
reconfigured (Fig. 2.6) and the common mode leakage current model is derived. The
9
equivalent inductance is given by
Leq =L1L2
L1 + L2
+ Lg (2.6)
The total common mode voltage is derived as,
vtCM = vCM + evDM (2.7)
where, evDM is the effective DMV and is given by,
evDM =vDM
2
(L2 − L1
L2 + L1
)(2.8)
Figure 2.7: Equivalent model using voltage sources (a) Step I (b) Step II
The Leakage current model is shown in the (Fig. 2.7) forms a resonant circuit with
L and C elements. For the leakage current to be ideally zero, the total CMV according
to Eq. 2.7 has to be maintained constant. If the network has a symmetric inductor
configuration, then L1 = L2, this relation does not hold good otherwise [19], [32].
vtCM =
vAN+vBN
2+ vDM
2
(L2−L1
L2+L1
)if L1 6= L2
vAN+vBN
2if L1 = L2
This model is applicable to all types of transformer-less topologies. Every time a
new factor is considered, the equivalent circuit is modeled accordingly by making minor
changes. For half-bridge topologies, asymmetric inductor configuration is used. For full-
bridge networks, filter inductors are placed on both the phases. This will ensure a constant
CMV. The effect of grid voltage is not considered but it has a contribution of 7.2 mA/kW
at 50 Hz.
10
2.4 Overview of grid connected transformer-less sys-
tem
A simple full bridge transformer-less grid connected inverter with conventional pulse width
modulation (PWM) techniques is studied in order to explain the need for deriving new
transformer-less topologies.
2.4.1 Topologies derived from full-bridge inverter
Bipolar pulse width modulation :
As simple H-Bridge inverter is shown in Fig 2.4. In bipolar modulation technique, the
switches S1, S2 are complementary to S3, S4. The inverter output voltage varies from
+VPV to VPV , hence bipolar pulse width modulation. The output voltage and current of
the inverter has dominant switching frequency( fs) component. This technique is suitable
for transformer-less connection as the leakage current is well within the specified limits
(iCM < 30mA) as shown in (Fig 2.8).
Figure 2.8: Leakage current characteristic for a Bipolar PWM operation
Unipolar PWM
In unipolar PWM technique, both the legs are operated independently using comple-
mentary modulating signals. Here, the inverter output voltage is unipolar in nature (
VAB = +VPV - 0 - −VPV ). The output voltage consists of dominant 2 × fs component
having less ((12
)) filtering requirement compared to BPWM. The current ripple is half that
11
of the BPWM technique, thus having reduced core losses and switching losses. Unlike the
BPWM, this technique produces a very high leakage current as the VPG, VNG varies at
switching frequency (Fig 2.9).
Figure 2.9: Voltage across the PV stray capacitance in UPWM inverter
Fig 2.10 shows the FFT analysis for both the unipolar and bipolar modulation tech-
niques.
Hybrid Unipolar PWM (HUPWM)
Considering the above two techniques, a hybrid technique where one leg of the inverter(S1, S3)
is operated at fundamental frequency(50 Hz) and the other leg (S2, S4) at switching fre-
quency, fs. A unipolar output voltage is achieved having the advantages of BPWM and
UPWM techniques [24]. When there is no filter inductor on phase B, the voltage VPG, VNG
vary at fundamental frequency. Though the variation is very slow (50 Hz), large spikes
in the leakage current near the zero crossings and large/complex filtering requirements
makes it unfit for transformer-less connection Fig. 2.11.
In order to address these limitations, several transformer-less topologies are suggested
in the literature [12]- [27]. These inverters are classified based on the type of network
configuration proposed in the literature as shown in the Fig.2.17. The transformer-less
inverter topologies are classified on the basis of:
1. Depending on the filter inductor configuration and position Symmetric/Asy-
mmetric Inductor type
2. Depending on the side (DC/AC) of decoupling, inverters are classified into DC/AC
decoupling circuits
3. Other classification of circuits with and without Neutral point clamping(NPC)
12
(a)
(b)
Figure 2.10: FFT analysis for (a) Bipolar PWM (b) Unipolar PWM
Figure 2.11: HUPWM: Voltages across PV stray capacitance to ground
which are further classified into Active NPC (ANPC) where a controlled switch
is used in the clamping branch whereas diodes are used in a simple NPC circuits.
2.4.2 Topologies derived from Full Bridge inverter
H5 Inverter by SMA
An additional series switch S5 is used on the PV side to eliminate the path for leakage
current [28]. From Fig. 2.12 S1, S3 are operated at grid frequency and are complementary.
S4, S3 are operated at switching frequency during negative and positive cycles of grid
13
voltage [15]. S5 is operated in sync with S3 and S4 at switching frequency. During the
free-wheeling mode of the inverter, S5 is turned off, hence breaking the leakage current
path.
Figure 2.12: H5 Topology by SMA
But, this operation is valid only if all the switches are ideal, i.e., if all the switches are
perfectly open. But there exists some junction capacitance which provides path for the
current during the freewheeling period. As, the circuit is asymmetric, there is an unequal
thermal stress and the CMV during the freewheeling is floating.
Highly Efficient and Reliable concept Inverter (HERIC)
In 2006, a new transformer-less topology where two anti-parallel switches are connected
the AC side of the H-bridge inverter was patented by the Sunways, Fig 2.13 [29].
Figure 2.13: HERIC Topology by Sunways
The system is isolated during the free-wheeling period with the help of two AC bypass
switches S+ and S−. Only two devices conduct in the powering mode unlike H5 topology,
14
thus having very high efficiency.Hence, the name Highly Efficient and Reliable Inverter
Concept (HERIC).
Figure 2.14: Common mode and differential characteristics of a HERIC inverter
Fig. 2.14 shows the common mode and differential modes characteristics. From the
simulation results, it is clearly understood, the common mode voltage in H5 topology is
oscillating (not constant) and it gives rise to a very high leakage current. This is due to the
capacitive coupling between the grid and PV array. Though, the HERIC topology show
very less oscillations, as the grid is decoupled from the PV array using AC bypass network,
the CMV is still floating due to its inability to clamp the voltage. Also, this topology
with the above mentioned switching scheme do not support reactive power exchange.
2.4.3 Topologies derived the from the Half-bridge inverter
A simple half-bridge voltage sourced converter uses two switches ans the neutral is always
connected to the mid point of DC link. But the output voltage is bipolar and maintains
a constant CMV. This requires two seperate dc sources whereas the H-Bridge topology
require only one source. Although this inverter is suitable for transformer-less connection,
VDC> 1000 V or more is practically not viable. Some of the few popular topologies based
on full-bridge derived from the NPC action of half-bridge inverter are discussed as follows:
1. Optimized topology (oH5)
2. H-Bridge Zero Voltage Rectifier (HB-ZVR)
3. Full Bridge DC bypass topology (FB-DCBP)/ H6DCBP
15
Full-Bridge Zero Voltage Rectifier (FB-ZVR)
This topology is derived from HERIC topology. Instead of connecting two bypass switches
on the AC side, a ZVR- Zero voltage rectifier operating with a controlled switch is used [1]
as shown in the Fig. 2.15 to develop this. An extra clamping diode is added to maintain
constant CMV. The bi-directional diode bridge is clamped to the mid-point of DC link
capacitor using a diode and this is done during the free-wheeling period.
Figure 2.15: A Full bridge Zero Voltage rectifier based transformer-less inverter
Figure 2.16: FB-ZVR: common mode and differential mode characteristics
The positive vector is achieved by switching S1−S4 and negative vector by S2−S3. The
zero-vector is achieved by switching on the S5 by providing a small dead time (0.8−1.5µs)
to avoid short-circuit of the input capacitor. The current during the zero voltage free cycles
across the bridge rectifier. During the dead time, the grid current finds a way through
16
the diodes which incurring more losses. Hence, this topology has lesser efficiency than the
HERIC topology. Also 6 extra diodes are incorporated for implementing this topology
which makes it less reliable and more costly.
Full Bridge DC bypass Transformer-less inverter (FB-DCBP)
Fig. 2.18 [14] is a NPC based full bridge topology. Switches S1, S4, S5 conduct
during the positive half-cycle of grid voltage and S2, S3, S6 during the negative half-
cycle. This topology is symmetrical unlike the H5 inverter having uniform thermal distri-
bution. During the freewheeling period, the diodes D+ and D− clamp the CMV to +VPV
2.
The speed of clamping is solely dependent on the diodes D+, D−.
This inverter has excellent common-mode characteristics. Due to the conduction of
four devices during the active period, this converter is lossy. The diodes (D1, D2) forms
a capacitor divider, hence, the PIV of the switches S1 and S2 are halved. The leakage
current characteristics are excellent in comparison with the other topologies, but the effi-
ciency is very low due the conduction of 2 extra switches in the powering mode (Fig. 2.19).
Finally, the classification of various transformer-less inverters is shown in the next page
(Fig. 2.17)
2.5 Limitations of the study
The transformer-less topologies are analyzed by making the following assumptions
• All the devices are assumed to be ideal
• Effects of grid voltage [30] is not considered
• Dead time issues are not discussed [31]
But, in all practical situations, the junction capacitance of the inverter switches
and other parasitics influence the CMV depending upon the topology used. Thorough
study has to be carried out to analyze their effects.Hence, following needs to be done on
transformer-less inverters,
• Find a method to analyze the topologies when switch capacitance and dead time
are considered
• Study some of the sensitive topologies towards these effects
17
Fig
ure
2.17
:C
lass
ifica
tion
oftr
ansf
orm
er-l
ess
volt
age
sourc
ein
vert
ers
18
Figure 2.18: H6 inverter with DC bypass and Neutral point clamping
Figure 2.19: H6-DCBP: common mode and differential mode characteristics
• Devise a solution to overcome these effects and verify through simulations
• Validate the solution using hardware experimentation
2.6 Summary
An overview of the transformer-less topologies is presented in this chapter. A simplified
leakage current model is discussed and necessary conditions are formulated to maintain
low leakage current. An overall classification of the inverter topologies is presented by
virtue of their nature. Limitations for the study performed in the literature are pointed
out and a clear objective of this project is mentioned.
19
Chapter 3
An Improved Neutral-point
Clamped Transformer-less Inverter
3.1 Introduction
This chapter deals with the effects of junction capacitance of the inverter switches. Leak-
age current analysis is carried out during the freewheeling period and dead time as well.
Based on the analysis, a simple solution if suggested to reduce the leakage current
3.2 Analysis of optimized H5 (oH5) Inverter
An optimized H5 (oH5) transformer-less inverter is shown in Fig. 3.1 [25]. This topology is
derived from H5 by SMA ltd. where the pole voltages are floating during the freewheeling
period.
Figure 3.1: An optimized H5 Inverter topology
Under ideal operation, the CMV is maintained constant through a clamping branch.
This branch employs an IGBT-Diode based switch to do the necessary. Hence, this
20
topology falls into the category of Active NPC inverters. The shoot-through issue is dealt
by adding a small dead time between the complementary switches (S5, S6).
3.2.1 Modes of Operation
The modes of operation for this inverter are detailed below. The control is done such that
power is fed into the grid at unity power factor. Fig. 3.2 refers to the switching scheme for
the converter switches. S1 & S2 are complementary, operated at grid frequency(50Hz). S3
& S4 are operated at switching frequency and are turned off when S1 and S2 respectively
are turned on. And, S5, S6 are operated at switching frequency (fs) during both the half
cycles of grid period.
Figure 3.2: Switching strategy for oH5 topology
21
The inverter is operated in the following modes:
• Mode I: vg, ig > 0;S1, S4, S5 −ON
• Mode II : vg > 0, ig > 0;S2, S6−ON
• Mode III : vg < 0, ig < 0;S2, S3, S5 −ON
• Mode IV : vg < 0, ig < 0;S2, S6 −ON
Mode I
For vg, ig > 0, switches S1, S4 and S5 are conducting where S1 is continuously ON for half
the grid period. The current flows through P − S5− S1−L1−L2− S4−N . The voltage
across the inverter output terminals, vAB = +VDC and the pole voltages
Figure 3.3: Mode I : vg, ig > 0;S1, S4, S5 −ON
vAN = +VDC ; vBN = 0V (3.1)
Hence, the common mode voltage when L1 = L2 is given by
vtCM =vAN + vBN
2+ evDM
= +VDC
2(3.2)
Mode II
In this mode, both switches S4&S5 are turned OFF so that the current in L1&L2 free-
wheels through S1&D2 (Fig. 3.4). Hence the pole voltages vAN = vBN = +VDC
2and hence
22
the common mode voltage is,
vtCM = +VDC
2(3.3)
Any deviation in the inverter pole voltages, clamping branch bearing switches S6 − D6
Figure 3.4: Mode II : vg > 0, ig > 0;S2, S6−ON
clamps the voltage to +VDC
2, hence maintaining the CMV constant in both the powering
and free-wheeling mode.
Mode III & Mode IV
Operation of the inverter in Modes III & IV are similar to Modes I & II except for the
output voltage (either 0V or −VDC). Switch S2 and S3 conducts, where S2 operates at
50Hz and the latter at fs (Fig. 3.5(a),(b)). The common mode voltage remains +VDC
2.
3.2.2 Operation of Clamping branch
The DC side of the inverter is provided with two capacitors offering almost similar char-
acteristics. Hence, this mid point (‘O’) is accessed to clamp the pole voltages vAN &
vBN through S6. S6 is operated complementary to S5 when either S1 or S2 are turned
ON. The path for the current flow depends on the magnitude and polarity of the voltages
vAN(= vBN). When vAN < +VDC
2, then current flows through the diode D6 Fig. 3.5(c),(d)
otherwise the current will flow though the already turned S6 clamping the voltages to
+VPV
2. The effectiveness of the clamping circuit depends on how fast the switch S6 and
D6 can be turned ON [32].
Due to the unidirectional nature of the current through D6, the lower capacitor CDC2
discharges as soon as the inverter is started. To avoid this, a very large resistance can be
placed across the two capacitors or an active balancing circuit be employed to maintain
23
Figure 3.5: Operation Modes of oH5 Inverter (a) Mode III (b) Mode IV (c) Clampingthrough S6 (d) through D6
the mid point voltage. Here, a resistive divider circuit is used to maintain the mid point
voltage. The value of the resistor is too high (> 27kΩ) which influences the efficiency
very less(0.1%). Under non-ideal conditions, a small dead time, (0.5− 1.5)µs is provided
between S5 and S6 to avoid the short circuit of capacitor CDC1. As a result, large spikes
appear in the pole voltages and CMV which gives rise to spikes in leakage current.
3.2.3 Effect of dead time on Common Mode Voltage
Dead time is provided to avoid shoot through problems in a converter. In oH5 inverter, a
small dead time is provided between S6 and S5 to avoid short circuit of CDC1. Effective
clamping is not achieved during the dead time as the switch S6 is turned OFF. Realistic
assumptions are made to analyze the behavior of the converter during this period. All the
switches are realized by their junction capacitances [31], [14], [33] “Cce” when they are
switched OFF. During the transition between Mode I&II or Mode III&IV, the resultant
circuit is shown in the Fig. 3.6(a).
During the transition from Mode I to II, immediately after S5 is turned OFF and S6
is ON, the voltage vAN = +VPV and vBN = 0V . So, the diode D2 is reverse biased. The
inductor current free-wheels through the junction capacitance of the switches S2, S3, S4,
S5, S6. During this time, the capacitors C3, C2 discharges and C4 charges through C5 and
24
C6. When the voltages vAN = vBN , the diode D2 starts conducting
Figure 3.6: Resonant circuit for (a) Differential mode for vAN > vBN (b) Common modefor vAN = vBN
as in Fig. 3.6(b). By applying Kirchoff’s current law at nodes A and B,
ig = i2 + i3 + i5 + i6
ig = i2 + i4
i1 = i2 + i5 + i6
i4 = i3 + i5 + i6
(3.4)
From the equations, C5, C6, C3 are parallel to each other and by using charge conser-
vation theorem, the voltages vAN and vBN are found out to be by
vAN = vBN =C3 + C5 + C6
C3 + C4 + C5 + C6
VPV (3.5)
in mode I-II and,
vAN = vBN =C4 + C5 + C6
C3 + C4 + C5 + C6
VPV (3.6)
25
In mode III-IV
If all the capacitances assumed to be same, the common mode voltage(CMV) is given by,
vAN = vBN = vCM = +3VDC
4(3.7)
3.2.4 Improved transformer-less Inverter
From the Eq. 3.5, 3.6, the pole voltages are a relation of the junction capacitances of the
converter switches. To maintain the pole voltages and hence the common mode voltage
to +VPV
2,
vAN = vBN =C3 + C5 + C6
C3 + C4 + C5 + C6
VPV == +VPV
2(3.8)
and,
vAN = vBN =C4 + C5 + C6
C3 + C4 + C5 + C6
VPV = +VPV
2(3.9)
Figure 3.7: Circuit for Improved oH5 Inverter topology
The necessary and sufficient conditions to be met are given by
C3 = C4 + C5 + C6
C4 = C3 + C5 + C6
(3.10)
From Eq. 3.10, it is noted that, S3, S4 requires additional capacitors across collector-
emitter to satisfy the below equations:
C3 >> C5 + C6
C4 >> C5 + C6
(3.11)
26
The typical value of the capacitance C3 and C4 are ten times that of the C5 and C6. The
same analysis is applied for H5 inverter [15], [26], the common mode voltage is +23VDC if
all the switches are dissimilar (C6 = 0F ), then
vAN = vBN = vCM =C3 + C5
C3 + C4 + C5
VPV (3.12)
also,
vAN = vBN = vCM =C4 + C5
C3 + C4 + C5
VPV (3.13)
To maintain the CMV at +VPV
2,
C3, C4 >> C5 (3.14)
Selection of Transformer-less Inverter
One of the most important factor considered for validating the effectiveness is the circuit
symmetry. For example, all the derived full-bridge topologies have symmetrical inductor
configuration. Similarly, the symmetry of the circuit is evaluated on the basis of their
resonant circuit. As soon as the converter is forced to free-wheeling mode, the inverter
pole voltages vAN and vBN are a measure of CMV. These voltages are estimated using the
theory discussed in the previous section. Considering the topologies - H5, oH5, HERIC,
the resonant circuits along with their resonant frequency are shown in the Table. 3.1.
The symmetry of the circuit is decided by the charging and discharging process of
all the junction capacitance os switches. For a circuit to be symmetric, it requires equal
charging and discharging of both the switches C3 and C4. Also, once the circuit reaches
steady state (in a PWM half-cycle), the inverter pole-voltages settles to +VDC
2.
By evaluating the resonant frequencies for all the topologies and from the Fig. 3.8,
HERIC topology offers has the highest resonant frequency at fs, rest follows as
fs << fHERIC > fH5 > foH5 (3.15)
ZHERIC > ZH5 > ZoH5 (3.16)
From the above relations, the voltage oscillations are more in the HERIC topology
which is a symmetric circuit. Hence, leakage current is still present in the system. To
avoid this, a clamping branch is suggested in the literature.
27
Table 3.1: The Equivalent Resonant circuits with their resonant frequency
Topology Resonant Circuit vAN = vBN = vCM Ceq fr
H5 23Vdc 3C//eCPV ≈ 3C 1
π
√1
6LC
HERIC 12Vdc
12C//eCPV ≈ C 1
π
√1
2LC
oH5 34Vdc 4C//eCPV ≈ 4C 1
π
√1
8LC
Figure 3.8: Impedance(Z) vs Frequency (f) plot for H5, oH5, HERIC Inverters
3.2.5 Simulation Results
While simulating the inverter, all the switches are assumed to be same with junction
capacitance of 29 pF, device part no.IKW15N120H3. Additional capacitors (Ce = 330pF )
are used to validate the improved topology. Table. 3.2 gives the data used while performing
the simulation study.
Fig. 3.9 shows the simulated waveforms for H5 topology. Here, the voltages vAN and
vBN have switching oscillations while transitioning from powering to free-wheeling mode.
28
Table 3.2: Simulation Parameters
Rated Power 1kW
Input Voltage 380V
Grid voltage/ frequency 230V/50Hz
Switching Frequency 20kHz
Filter Inductor L1 & L2 3mH
Filter Capacitor Cf 2µF
PV Stray Capacitance, CPV 0.1µF
Extra Capacitor, Ce 330pF
IGBT, Cj 29pF (IKW15N120H3)
Figure 3.9: Simulated waveforms for H5 topology: Zoomed view of vAN and vBN
Figure 3.10: Simulated waveforms for improved H5 topology: Zoomed view of vAN andvBN
For every transition, there appears a spike followed by oscillations. Since this topology is
not a NPC based configuration, the oscillations die out at a very slow rate. Hence very
29
(a)
(b)
Figure 3.11: Simulated waveforms for oH5 topology (a) Variations in CMV along withvAN , vBN and (b) Waveforms for vAB, vg, 20× ig and iCM
high oscillations (∼ 220V ) appear in the CMV (Fig. 3.9) inducing very high leakage
current (>50 mA). When additional capacitors are connected across the switches S3 and
S4 are connected, the voltage oscillations are damped out (< 20V ).
As the free-wheeling period reduces, the voltage spikes increases, thus increasing the
leakage current at the zero-crossings of the grid reference.NPC based topologies are best
suited for this purpose. They clamp-out the pole-voltages to VPV
2by absorbing peaky
currents. If the dead time is to be provided, circuit parasitics forces a variable CMV
characteristics (oH5 Inverter) as shown in Fig. 3.11
3.3 Summary
In this chapter, some of the popular transformer-less topologies are investigated. The
effect of switch parasitics is analyzed during dead time. Based on the analysis, a simple
30
(a)
(b)
Figure 3.12: Simulated waveforms for Improved oH5 topology (a) Variations in CMValong with vAN , vBN and (b) Waveforms for vAB, vg, 20× ig and iCM
modification is suggested. Size and the efficiency are least effected. Various simulation
studies are performed to validate the theory discussed. Certain assumptions are made
studying the system. Fluctuations in input power is neglected whose variation contributes
to the leakage current.
31
Chapter 4
Hardware Implementation
4.1 Introduction
The hardware results implying the effects in all the presented topologies are shown and
the results for the improved NPC inverter are produced. Also, efficiency calculations are
done for all the four topologies and compared with the improved inverter.
4.2 Hardware Setup
A 1 kW hardware setup is designed and developed for a transformer-less grid connected
PV system. Fig. 4.1 shows a generalized layout [9] to validate four topologies namely:
Figure 4.1: Circuit layout for experimentation
32
• H5 Topology
• HERIC Topology
• oH5(Optimized H5) Topology
• Improved oH5 topology
Figure 4.2: 1 KW Hardware Setup for a transformer-less system 1) Programmable DCsupply, 2) DC link capacitors, 3) Generalized Power PCB, 4) Sensing board, 5) Drivercircuit, 6) Regulated DC power supplies, 7) Filter inductors, 8) Auto-transformer (grid),9) Controller : TMS320F28335, 10) Level shifter(Buffer circuit with pull-up resistor)
4.2.1 Selection of DC link Capacitor
The sizing of the DC link capacitor is estimated by neglecting the switching and conduc-
tion losses initially. Later, it is extended for non ideal case. In such case, using energy
balance balance equations for a grid connected system,
pac = vg.ig
= 2VgIg sin2(ωt+ ψ)
= Po + Po cos(2ωt) (4.1)
The ripple power varying at 2ω is provided by the DC side capacitor. Considering the
DC link voltage to be constant with some ripple (∼ 2%), the ripple power handled by the
33
DC link capacitor is
Pdc(t) = vc(t).ic(t) (4.2)
vc(t) = Vdc + vr (4.3)
Assuming unity power factor operation on the grid side, i.e., both vg and ig are in
phase,
vgig =VgIg
2− VgIg
2cos(2ωt)
= Po − Po cos(2ωt) (4.4)
If the DC link voltage is ripple free,
ic(t) =PoVdc
cos(2ωt)
= Cdcdvrdt
(4.5)
vr(t) = Vr sin(2ωt) (4.6)
From Eq. 4.3,4.4 and 4.5, Cdc is expressed as
Cdc =Po
2ωVdc∆vr(4.7)
The parameters considered are Po = 1kW , Vdc = 380V , ω = 100π radians, vr = 76V ,
the value of DC link capacitor is found out to be Cdc = 551µF .
4.2.2 Design of output Filter
The cut-off frequency (fc) of the output filter is 110th of switching frequency fsw (20kHz)
i.e., 2kHz. For unipolar output of the inverter, the value of filter inductor is calculated
by the following relation,
Lf = L1 + L2 =VDC
8∆iLfmaxfsw(4.8)
For, the ripple in the inductor current be 10% which is in acceptable range with a rated
power of 1kW , the value of Lf is evaluated to be 5.4 mH and the filter capacitor is found
34
out by the following relation of cut-off frequency.
fcut−off =1
2π√
(L1 + L2)Cf(4.9)
Thus, Lf is selected in order to limit the current ripple and Cf to absorb high frequency
ripple. Therefore, Lf = 6mH, Cf = 2µF .
4.2.3 Sensing Circuit
To perform closed loop operation (grid current control), some parameters are sensed and
fed back to the system control loop. In order to read the parameters, current and voltage
sensors are employed followed by stepping down the variables with in the readable range.
Isolation is provided using IC ISO122P between the high and low power circuits.
Voltage sensing
The voltage (both AC and DC) ranges from (0-400)V. To step-down the signal, a simple
op-amp based resistor divider is used which also provides isolated ground. For AC volt-
ages, since the DSP cannot take negative values, a small offset (1.5V) is provided at the
output of the ISO122P by adjusting the output of LM317 using resistors.
Current sensing
For current sensing, LEM based hall effect sensors (LA 55-P) are used for both AC and
DC quantities. Only AC current sensing is required for the experiment, hence, off-set of
1.5 V is provided.
4.2.4 Level Shifting Stage/ Buffer Circuit
The input voltage necessary to trigger the gate driver is 5V (SKHI 22BR). The con-
troller output varies from (0-3.3V). So, to increase the fan-out capability (to avoid load-
ing the input from output) and avoid having floating potential at the driver input pins,
Hex buffers (DM7417) with high output voltage (3-15V) along with a CMOS OR gate
(HEF4071 BP) is used.
35
4.2.5 Driver Circuit
To drive the power switches at 20kHz (IGBT, MOSFET), sufficient driving current (iGE)
is required. Here comes the application of gate drivers. SEMIKRON gate-drivers
(SKHI 22BR) with maximum operating frequency of 50kHz and a driving current of
8mA (peak) are used in this implementation. No blank time (dead-time) is provided as
a software delay of 0.8µs is provided between the complementary switches of an inverter
leg.
4.2.6 Measurement of leakage current
In Fig. 4.1, two measuring points are identified, represented by m1 and m2. The measuring
point m1 requires one current sensor where as, the point m2 requires two sensors along
with an extra computation. Thus, m1 is preferred over the m2. Also, the measurement
of current requires current sensor with a very high resolution. In this experiment, a
high precision resistor (1Ω/1 W ) is used to measure the voltage drop across it which is
numerically equal to the leakage current.
4.3 Control Strategy
In grid connected PV systems, the grid current is in direct relation with the power avail-
able on the input side of PWM DC/AC converter. The control of power is achieved by
controlling the current. This current reference is generated by the power available at the
input side or by regulating the DC link voltage. Following are the essential components
of the control scheme:
• Grid Synchronization
• Current Controller
4.3.1 Grid Synchronization
Grid synchronization is essential in single-phase photovoltaic systems. If a phase or mag-
nitude jump occurs at the PCC (point of common coupling), the system should respond
towards the disturbance created in a very less time. Hence, there should be a robust
mechanism to generate reference signals to drive the inverter during the disturbances/
faults. There are a number os synchronization methods employing mathematical com-
putation (Frequency locked loop through Fourier analysis) and PLL-based methods [42].
36
Adaptive PLLs are implemented the most and became popular with time. A simple PLL
block diagram is shown in the Fig. 4.3 consisting of a phase multiplier (PD), a low pass
filter (LF) and a voltage controlled oscillator (VCO). The PLL is a second order system
with a first order filter.
Figure 4.3: Simple Block diagram of phase locked loop (PLL)
The transfer function for the system is given by
θo(s)
θi(s)=
K1K2Kps+K1K2Ki
s2 +K1K2Kps+K1K2Ki
(4.10)
where,
Kp +Ki/s is the transfer function of loop filter
K1, K2 are the constants of phase detector (PD) and the voltage controlled oscillator
(VCO)
ζ and ωn is the damping ratio and undamped natural frequency of the system.
ζ =1
2
Kp√Ki
; ωn =√Ki (4.11)
And the settling time (K1 = K2 = 1) is given by,
ts =4.6
ζωn(4.12)
The PLLs are distinguished based on their characteristics of phase detector. Also, some
adaptive PLLs are proposed in the literature out of which only two of them Second
order generalized integrator based phase locked loop (SOGI-PLL) and Enhanced phase
locked-loop (E-PLL) are implemented the most. This project deals with the control of
instantaneous active current/ power, thus EPLL which requires less memory and responds
quickly is chosen to implement the hardware.
37
Enhanced Phase Locked Loop (E-PLL)
Enhanced PLL is an adaptive algorithm based filter which can track both the phase and
amplitude of the input signal. In the Fig. 2.3 shown below, the steepest descent algorithm
is used in F (.) to reduce the error signal [37]- [39]. Hence it is a function of both amplitude
and phase of the signal expressed as,
Bm(Vm, θ) =1
2e2 =
1
2(vi − vi)2 (4.13)
where Vm is the estimated value and is found out by a number of iterations such that,
Vm(k + 1) = Vm(k) + ∆Vm (4.14)
Here, k is the iteration number and ∆Vm is step change in the estimated value. The single
weighted adaptive filter whose objective function from Eq. 4.13 is optimized using LMS
(Least mean square approximation) whose final relations are as follows:
∆Vm = −µ∂Bm
∂Vm
= − ∂
∂Vm
(−1
2µe2)
= µe(k) sin( ˆθ(k)) (4.15)
From Eq. 4.14,4.15, the magnitude of the actual voltage vi is calculated to be
Vm =µe
Tssin(θ) (4.16)
Figure 4.4: Phase detector of enhanced phase locked loop (EPLL)
38
and if all the equations are linearized, the ratio VmVm
is expressed as
VmVm
=1
1 + sτ(4.17)
where, τ = 2ka
is the time constant,
4τ = 8ka
is the settling time, ts
The Fig. 4.4 illustrates the adaptive structure of phase multiplier(PD) of the enhanced
PLL with optimized adaptive filter. Here, ’µ’ decides the stability of the system, speed of
convergence and also the residual error of overall adaptive process [40], [38].
For optimum response in terms of rate of convergence, stability and error reduction
following values are chosen for implementation. ka = 100, Kp = 1.7, ki = 120 [?]
4.3.2 Current Controller
The control of power is achieved through an inner current loop controlling and an outer
voltage loop. The reference current i∗ref is generated through the voltage control. Various
current control techniques are used to inject the power such as
• Hysteresis control where in the generated current is directly compared to the ref-
erence and the switches are operated in such a way that the current is forced to
operate with in a band. This has inherent short circuit capability but the switching
frequency continuously varies with the reference. Thus, designing a filter is very
difficult.
• Adaptive-hysteresis control where the ripple is varied to maintain constant operating
frequency. But, the need for more sensing is a major drawback for this technique.
• 1 − φ d-q control where in a pseudo quadrature signal is generated using the PLL
and then transformed into synchronous frame. The error is forced to zero (ideally)
with the help of PI regulators which shape the modulating signal. This method
provides with control over both active and reactive power. This requires a lot of
computation which burdens the processor. But the need for compensation added
complexity in practical implementation.
• Proportional and Resonant controller is another way of tracking the reference signal
without any transformations. This control is capable of tracking a fastly moving
signal. The implementation for various compensations is practically simple.
39
Proportional and Resonant controller
The proportional Integral controllers suffers from limited band-width characteristics. How-
ever, a very high bandwidth is required to reduce the error for high frequency signals. Con-
ventional PI regulators are used to track constant (DC) signals [44], [45]. A small phase
shift and a non-zero error at steady state is present while tracking the higher frequency
signals.
The power electronic converters whose ratings lie in the range of kV A limits the
selection of switching frequency or the sampling rate of the controller. Thus, producing
high bandwidth requires very small sampling time. Additionally, ADCs with very high
sampling rate are required which will increase the effort and the system costs. This P+R
controller provides a very high gain (ideally infinite) at its resonant frequency and rest
all components are forced to zero. This P+R controller is derived by transforming the PI
transfer function from rotating frame to stationary reference frame.
The transfer function for proportional resonant controller is given by,
Gcos(s) = Kp +2Kiωos
s2 + ω2o
Gsin(s) = Kp +2Kiωos2 + ω2
o
(4.18)
where, Ki is the coefficient of resonant term and Kp is the proportional gain, ωo is the
resonant frequency of the controller. Gcos(s) is always preferred as it offers better gain
margin which in turn improves the stability. If the error signal consists of several har-
monics, transforming each and every component to a DC quantity and forcing them to
zero involves a lot of computation. Instead transforming them to stationary frame forces
the error to zero [43]. And the non ideal integrator Ki
1+ sωc
when transformed to stationary
frame is given by:
Gc(s) =2Kiωcs
s2 + 2ωcs+ (ω2c + ω2
o)
=2Kiωcs
s2 + 2ωcs+ ω2o
(4.19)
Ideal PR provides infinite gain at the resonant frequency which makes it practically
impossible to implement it on the chip. Owing to the processor limitations, ωc is chosen
in the range of (5− 15) rad/s. Also, ωc effects the dynamic response. Kp is tuned similar
40
to that of a PI regulator which effects the phase margin, transient response and stability
of the closed loop control system. Ki provides a very high gain at resonant frequency and
does not effect on the system dynamic response. Along with the single frequency tuning,
other lower order harmonics are compensated by cascading the PR transfer functions at
selective harmonic frequencies.
Figure 4.5: Frequency response of an Ideal P+R controller with compensation
Gh(s) =∑
h=3,5,7..
2Kihs
s2 + (hωo)2(4.20)
Gh(s) =∑
h=3,5,7..
2Kihωcs
s2 + 2ωcs+ (hωo)2(4.21)
The parameters for harmonic compensator Kih do not influence the response of the
PR controller at fundamental frequency. Proper compensation requires tuning of HC
(Harmonic Compensator) coefficients [35]. The PR + Harmonic compensator responses
are shown in Fig. 4.5 where compensation is performed for 3rd, 5th and 7th harmonics.
4.3.3 Block Diagram of the Control Scheme
The main aim of the control scheme is to generate switching pulse pattern for the grid
connected transformer-less inverter. Fig. 4.6 shows the block diagram of the control
scheme used for the power processing [34].The phase information is extracted through
the enhanced PLL (EPLL) and the current reference is set depending on the input power
available.
The inverter output current is compared with the reference and the error signal is
processed by the PR controller. A feed forward term vg = Vm sin(ωot) is added to the
obtained value of the PR +harmonic controller. The resultant output is the duty ratio
41
Figure 4.6: Closed loop current control scheme for a single phase PV based grid-tiedinverter
(modulation signal) for the inverter switches. The feed forward term is used to improve the
starting condition/response of the system and used for disturbance rejection. Though feed
control has its own advantages, it makes the control loop unstable due to its anticipation.
4.4 Hardware Results
A 1kW laboratory prototype is developed to test all the three inverter topologies - H5,
HERIC, optimized H5 (see Fig. 4.2)and the improved NPCTLI for their common mode
characteristics, i.e., CMV and leakage current. Component specifications for the power
circuit are shown in Table 4.1. A programmable DC source and a lumped capacitor of
0.1µF are used to imitate a PV source and its parasitic capacitance. A 32-bit floating
point processor (TMS320F28335) is used to implement the control. Various results corre-
sponding to the common mode voltage (CMV) - vAN , vBN , iCM along with vAB and the
grid current ig and voltage vg are collected to validate the simulation results. Later on,
device losses are calculated to compare the efficiencies of all the four topologies.
Table 4.1: Hardware Specifications
PARAMETER RATINGPower 1 kW
Input Voltage (360− 700) VGrid voltage/ frequency 230 V /50 HzSwitching frequency (fs) 20 kHzFilter Inductor L1 & L2 3 mH
Filter Capacitor Cf 2 µFPower IGBT IKW15N120H3
DC link capacitor, CDC1 & CDC2 2200 µFPV Stray Capacitor, CPV 0.1 µFAdditional Capacitor, Ce 330pF
IGBT, Cj 29pF (IKW15N120H3)
42
4.4.1 H5 Topology
In this inverter configuration, the common mode voltage varies from +VPV
2in powering
mode to +2VPV
3in the free-wheeling mode. This is due to the fact that the circuit is
asymmetric. The chances of the failure of S5 due to the uneven thermal distribution.
Moreover the maximum leakage current is very high (< 50 mA) due to fast variation in
CMV. From Fig. 4.8, it is evident that in powering mode (vg > 0), vAN falls from 380V
(+VPV ) to 260 V (+2VPV
3). Before settling to 260 V, it performs oscillations due to the
resonant circuit formed by line inductors (L1, L2), CPV and switch capacitances (C3, C4,
C5) and eCPV .
Figure 4.7: Differential and Common-mode characteristics of H5 topology, vAN(200V/div),vBN(200V/div), vCM , vg (200V/div), ig (5A/div)
Later, the voltage settles to VPV
2due to the damping provided by the track resistance.
Hence, from the Fig. 4.9, it can be seen that the leakage current exceeding the peak
value of 50 mA and violates the V DE 126 − 1 − 1 standard limitations. Fig. 4.7 shows
the variation of inverter pole voltages (vAN , vBN), CMV , vg and ig respectively. Fourier
analysis for the leakage current is carried out and the value of iCM is found out to be 7.1
mA at 20 kHz(see Fig. 4.10).
4.4.2 Highly Efficient and Reliable Inverter concept (HERIC)
This topology has a very low switch count after H5 by SMA. Unlike H5 inverter, this
topology is symmetric(equal charging and discharging of C3 and C4). The thermal distri-
43
Figure 4.8: H5: Zoomed view of vAN(200V/div), vBN(200V/div) showing the oscillationsduring the free-wheeling period
Figure 4.9: H5: Inverter output voltage, vAB (200V/div), and the leakage current iCM(100 mA/div)
bution is even.
Though the inverter is symmetric, due to the lack of any clamping circuit, CMV per-
forms certain oscillations before attaining +VPV
2i.e. 190 V. Fig. 4.11 shows the differential
and common mode voltages vAB and vCM with grid voltage (vg) and current(ig). As
the grid voltage approaches to 0V, the powering period is very less. This results in very
high rise in the inverter pole voltages and hence CMV. This induces spikes in the leakage
44
Figure 4.10: H5: FFT analysis of the leakage current, FFT(iCM), 1mA/div
Figure 4.11: HERIC: Inverter pole voltages, vAN & vBN (200 V/div) CMV, vg(200V/div),ig(5A/div)
current.
In Fig. 4.12, the variation of pole voltages and the CMV are illustrated. Every tran-
sition gives rise to 60V spike in the CMV. Due to this high frequency spike, significant
leakage current flows through the PV stray capacitance. Fig. 4.13 shows the leakage cur-
rent and Fig. 4.14 shows the FFT analysis of iCM , whose value is ' 6.5 mA at fs = 20
kHZ.
4.4.3 Optimized H5 Inverter
To avoid the short circuit of DC link capacitance CDC1 during the switching of S5, S6,
a small dead time (0.8 µs) is provided between the successive switchings. Due to this,
45
Figure 4.12: HERIC Inverter: Oscillations performed by the pole voltages during thetransitions
Figure 4.13: HERIC Inverter: Differential voltagevAB(200V/div),leakage current,iCM(50mA/div), Grid voltage, vg(200V/div), grid current, ig(5A/div)
the control over the CMV through the clamping branch is lost. Fig. 4.15 illustrates the
inverter pole voltages, the CMV along with the grid voltage and current.
The neutral point ’O’ is maintained at +VDC
2by using a simple resistive divider circuit.
No active voltage balancing is used to maintain the mid-point voltage. Fig. 4.16 shows the
common mode characteristics in a zoomed manner. In the same way, the FFT analysis
for the leakage current is done shown in Fig. 4.18 where, the iCM is 5.4mA at 20 kHz.
46
Figure 4.14: HERIC: FFT Analysis for the leakage current of (iCM = 1mA/div)
Figure 4.15: oH5 Inverter: Pole voltages, vAN & vBN (200 V/div) CMV, vg(200V/div),ig(5A/div)
4.4.4 Improved NPC Transformer-less Inverter
An improved NPC based transformer-less inverter is designed by connecting two capac-
itors of 330 pF each across switches S3 and S4. The resulting waveforms are shown in
Fig. 4.19,19,20. The rise in the voltage is 100V before the modification, where as the
voltage variation' 20V . But, the peaky current which is absorbed by the additional
capacitors induce losses into the system.
Losses due to Additional Capacitors
Connecting additional capacitors effects the efficiency of the converter. The stored en-
ergy of the capacitors in the active(free-wheeling) period is dissipated(transferred) and
considered as switching losses. The losses are evaluated as follows,
47
Figure 4.16: oH5 Inverter: Zoomed waveforms of Variations in CMV along with vAN ,vBN
Figure 4.17: oH5 Inverter: Differential voltagevAB(200V/div),leakage current,iCM(50mA/div), Grid voltage, vg(200V/div), grid current, ig(5A/div)
Pe =1
2CeV
2e fs (4.22)
=1
2(330× 10−12 × 3802 × 20× 103)W
= 0.476W (4.23)
48
Figure 4.18: oH5 InverterFFT analysis of the leakage current iCM , 1 mA/div
Figure 4.19: Improved NPCTLI: Pole voltages, vAN & vBN (200 V/div) CMV,vg(200V/div), ig(5A/div)
The total loss in two capacitors is 0.953 W (2×Pe) which accounts for 0.09% of the rated
power.
4.5 Efficiency Analysis
To estimate the efficiency of a converter, various losses due to the components are esti-
mated. The average duty ratio of the switches/ diodes are calculated by the following
relations:
dIGBT = M sin(ωt) ; ddiode = M(1− sin(ωt)) (4.24)
49
Figure 4.20: Improved NPCTLI: Voltage distribution across the DC link capacitors,CDC1, CDC2, VON (200v/div)
Figure 4.21: Improved NPCTLI: FFT analysis of the leakage current iCM , 1 mA/div
where, M is the operating modulation index
50
Figure 4.22: Improved NPCTLI: FFT analysis of the leakage current iCM , 1 mA/div
Conduction Losses
The average conduction loss in an IGBT operating at switching frequency is given by [20]
[13],
PIGBT (fs) =1
2π
2π∫0
i(t)vsw(t)dIGBT (t)d(ωt)
=M
4IMVt +
2M
3πI2MRce (4.25)
where, vsw(t) = Vt + i(t)Rce, Vt is the voltage drop when the current through the IGBT
is zero [24] and Rce is the on state resistance of the device. Also, IM is the peak induc-
tor current. Similarly, the diode conduction loss at switching frequency is given by the
relation,
Pdiode(fs) =1
2π
2π∫0
i(t)vdiode(t)ddiode(t)d(ωt)
= IMVf
(1
π− M
4
)+ I2MRak
(1
4− 2M
3π
)(4.26)
where, vdiode(t) = Vf + i(t)Rak, Vf is the voltage when current through it is zero, and Rak
is the ON drop resistance. Also, the conduction loss in IGBT operating at line frequency
51
is given by,
PIGBT (50Hz) =1
2π
2π∫0
i(t)vsw(t)d(ωt)
=IMVtπ
+1
4I2MRce (4.27)
and diode conduction losses,
Pdiode(50Hz) =1
2π
2π∫0
i(t)vdiode(t)d(ωt)
= I2MRak
(1
4− 2M
3π
)(4.28)
Diode recovery losses
During the turn of switches (IGBTs), the energy is induced into the diode and this can
be calculated [13] as,
Prr =1
2π
∫ π
0
(0.5VPV )(0.5Irr)fstbd(ωt)
= 0.125VPV Irrfstb (4.29)
where, fs is the operating frequency of the power switch, Irr is the reverse recovery current
in the diode and VPV is the input voltage.
Switching losses
The switching losses during the transition from ON to OFF for diode and the IGBT is
given in [25],
PIGBT−on =Vce (IM + Irr) (tr + ta)
2+VceIM tb
2+VceIrrtb
3(4.30)
Pdiode−off =Vf (IM + Irr) (tr + ta)
2+
(vdiode + Vf )Irrtb6
(4.31)
PIGBT−off =VceIM td
2+
11VceIM tf20
+VceIM ttail
20(4.32)
Pdiode−on =9VfIM tf
20+
19VfIM ttail20
(4.33)
Vce, tr, tf are the voltage across each IGBT, rise time, fall time. ta and tb are the recovery
times and ttail is the time taken for the tail current to go to zero. The total switching
52
losses is given by:
Psw = (PIGBT−on + Pdiode−off ) + (PIGBT−off + Pdiode−on) (4.34)
also,
Psw = (Eon + Eoff ) fs (4.35)
Eon and Eoff are the losses in energy in the switch at a particular operating point.
These vary w.r.t the operating voltage and maximum current. The second method from
Eq. 4.35 is used to calculate the switching losses and note that this equation is an ap-
proximate relation, which do not consider the diode ON losses.
Power loss in line inductors
The power loss in the line frequency inductors is due to their equivalent series resistance
(ESRL). Loss due to (ESRL) is calculated by the following expression:
Pesr =1
π
π∫0
i2(t)ESRLd(ωt)
=1
2I2MESRL (4.36)
Table 4.2: Device specifications and losses at rated power
PARAMETERS (IKW15N120H3) VALUESVt(V) 0.8Rce(Ω) 14 m
PIGBT (50Hz),W 2.29Pdiode(50Hz),W 0.13PIGBT (fs),W 1.45Pdiode(fs),W 1.04
Prr,W 0.31Psw,W 8.35
Ptotal(fs),W 11.15PL1&L2(fs),W 2.18
European Efficiency
Table. 4.2 illustrates each device loss using the above discussed expressions at a rated
output power of 1 kW .The inverters do not operate at their peak efficiencies all the time.
53
Efficiencies which are a function of power output, are averaged together to evaluate the
European efficiency. This is evaluated by assigning a fixed time(weights) for which the
inverter is operated at that power level. Mathematically,
ηeuro = 0.04η10% + 0.05η20% + 0.12η30% + 0.21η50% + 0.53η75% + 0.05η100% (4.37)
The ηeuro for the improved transformerless inverter is found out to be 96.9% and a peak
efficiency of 97.2%.
In Fig. 4.23, efficiency of all the four topologies are plotted against the output power
(Prated = 1 kW ). It is also observed that, though the HERIC topology has the highest
efficiency, its leakage current characteristics are worse. And H5 topology is better in terms
of leakage current but has low efficiency. The improved NPCTLI has very good leakage
current characteristics and high efficiency.
Figure 4.23: Efficiency comparison for H5, HERIC, oH5 and Improved NPCTLI
4.6 Summary
A 1 kW hardware setup is designed and developed for a transformer-less grid connected
PV system. The hardware results implying the effects in all the presented topologies
are shown and the results for the improved NPC inverter are produced which are in
agreement with the simulation results. Finally efficiency calculations are done for all the
four topologies and compared with the improved inverter.
54
Chapter 5
Conclusion
Based on the literature survey, classification of various transformer-less inverters is car-
ried out. Merits and demerits of some of the existing topologies are demonstrated through
simulations. Various non ideal factors effecting the leakage current are mentioned in this
report. Parameters like junction capacitance of the switches during the circuit dead time
are analyzed to study their effect on leakage current. For this study, some of the very
popular inverters are chosen and the root cause (solution) is found out. An improved neu-
tral point clamped transformer-less topology is developed. The effects are demonstrated
using thorough simulation studies. A 1 kW generalized hardware prototype is designed to
validate four topologies - H5, oH5, HERIC and Improved NPCTLI. Finally, a comparison
is made on the basis on their common-mode characteristics and efficiency.
Future scope of work
After effects like the DC current injection, parallel operation of several transformer-less
inverters having same input source and having discrete input sources are not discussed in
this report. Further work can be initiated in this direction.
55
Chapter 6
Appendix
56
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