best practices and results - home - springer978-0-387-68739-1/1.pdfpermission of the publisher...

Modern Circuit Placement Best Practices and Results

Series on Integrated Circuits and Systems

Series Editor: Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts

Modern Circuit Placement: Best Practices and Results Gi-Joon Nam and Jason Cong ISBN 978-0-387-36837-5

CMOS Biotechnology Hakho Lee, Donhee Ham and Robert M. Westervelt ISBN 978-0-387-36836-8 SAT-Based Scalable Formal Verification Solutions Malay Ganai and Aarti Gupta ISBN 978-0-387-69166-4, 2007

Ultra-Low Voltage Nano-Scale Memories Kiyoo Itoh, Masashi Horiguchi and Hitoshi Tanaka ISBN 978-0-387-33398-4, 2007

Routing Congestion in VLSI Circuits: Estimation and Optimization Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar ISBN 978-0-387-30037-5, 2007

Ultra-Low Power Wireless Technologies for Sensor Networks Brian Otis and Jan Rabaey ISBN 978-0-387-30930-9, 2007

Sub-Threshold Design for Ultra Low-Power Systems Alice Wang, Benton H. Calhoun and Anantha Chandrakasan ISBN 978-0-387-33515-5, 2006

High Performance Energy Efficient Microprocessor Design Vojin Oklibdzija and Ram Krishnamurthy (Eds.) ISBN 978-0-387-28594-8, 2006

Abstraction Refinement for Large Scale Model Checking Chao Wang, Gary D. Hachtel, and Fabio Somenzi ISBN 978-0-387-28594-2, 2006

A Practical Introduction to PSL Cindy Eisner and Dana Fisman ISBN 978-0-387-35313-5, 2006

Thermal and Power Management of Integrated Systems Arman Vassighi and Manoj Sachdev ISBN 978-0-387-25762-4, 2006

Leakage in Nanometer CMOS Technologies Siva G. Narendra and Anantha Chandrakasan ISBN 978-0-387-25737-2, 2005

Statistical Analysis and Optimization for VLSI: Timing and Power Ashish Srivastava, Dennis Sylvester, and David Blaauw ISBN 978-0-387-26049-9, 2005

Gi-Joon Nam Jason Cong

Modern Circuit Placement Best Practices and Results

123

Editors: Gi-Joon Nam Jason Cong IBM Austin Research Laboratory University of California, Los Angeles Austin, TX Los Angeles, CA USA USA

Series Editor: Anantha Chandrakasan Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge, MA 02139 USA

Library of Congress Control Number: 2007926182 ISBN 978-0-387-36837-5 e-ISBN 978-0-387-68739-1

Printed on acid-free paper.

2007 Springer Science+Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now know or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. 9 8 7 6 5 4 3 2 1 springer.com

Dedicated to VLSI circuit placement researchers and practitionerswhose creative and persistent efforts made it possible for us to handle

the exponential increase of circuit placement complexity in the pastfour decades. –Gi-Joon & Jason

Contents

Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Part I Benchmarks

1 ISPD 2005/2006 Placement Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 ISPD 2005 Placement Contest and Benchmark . . . . . . . . . . . . . . . . . . 41.3 ISPD 2006 Placement Contest and Benchmark . . . . . . . . . . . . . . . . . . 71.4 ISPD Placement Contest Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Locality and Utilization in Placement Suboptimality . . . . . . . . . . . . . . . 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Peko-MC Benchmark Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Monotone Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.2 The Peko-MC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Peko-MS Benchmark Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.1 Nonlocal Nets (Peko-MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.2 Parametrized White Space (Peko-MS) . . . . . . . . . . . . . . . . . . . 252.4.3 Suboptimality Under Both Parametrized White Space

and Nonlocal Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.4.4 Suboptimality of Detailed Placement . . . . . . . . . . . . . . . . . . . . 272.4.5 HPWL Suboptimality Comparison of Leading Academic

Tools on Peko-MS 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.4.6 Suboptimality of Routability-Aware Placement . . . . . . . . . . . 31

2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.6 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

viii Contents

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Part II Flat Placement Techniques

3 DPlace: Anchor Cell-Based Quadratic Placement with LinearObjective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.2 Preliminaries and the Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.1 Quadratic Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.2.2 Force-Directed Quadratic Placement . . . . . . . . . . . . . . . . . . . . 423.2.3 The Proposed Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Global Placement in DPlace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.1 Diffusion Preplacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.2 Anchor Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.3.3 Unconstrained Wire Length Minimization . . . . . . . . . . . . . . . 483.3.4 HPWL Transformation in a Quadratic System . . . . . . . . . . . . 503.3.5 Fixed Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.3.6 Wire Length Improvement Heuristics . . . . . . . . . . . . . . . . . . . 52

3.4 Legalization and Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 533.5 Overall Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.6 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.6.1 Advantages of our New Formulation . . . . . . . . . . . . . . . . . . . . 533.6.2 ISPD Placement Contest Benchmarks . . . . . . . . . . . . . . . . . . . 553.6.3 PEKO-MS Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4 Kraftwerk: A Fast and Robust Quadratic Placer Using an ExactLinear Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.2 Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.2.1 Clique Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.2.2 BoundingBox Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.2.3 Advantages of the BoundingBox Net Model . . . . . . . . . . . . . . 66

4.3 Quadratic Placement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.3.1 Additional Forces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684.3.2 Proof of Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.4 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.4.1 Engineering Change Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.4.2 Quality Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.4.3 Spring Constants of the Target Points . . . . . . . . . . . . . . . . . . . 754.4.4 Convergence Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.4.5 Control of the Module Density . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Contents ix

4.5.1 Clique and BoundingBox Net Model . . . . . . . . . . . . . . . . . . . . 824.5.2 ISPD 2005 Contest Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . 824.5.3 ISPD 2006 Contest Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . 834.5.4 PEKO-MS ISPD 2005 Benchmarks . . . . . . . . . . . . . . . . . . . . . 854.5.5 PEKO-MS ISPD 2006 Benchmarks . . . . . . . . . . . . . . . . . . . . . 884.5.6 Computational Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Part III Top-Down Partitioning-Based Techniques

5 Capo: Congestion-Driven Placement for Standard-cell and RTLNetlists with Incremental Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.2 Min-Cut Placement in Capo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.2.1 Row-Based Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.2.2 Min-Cut Bisection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3 Floorplacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005.3.1 Empirical Boundary Between Placement

and Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.4 Flexible Whitespace Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.4.1 Uniform Whitespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045.4.2 Minimum Local Whitespace . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055.4.3 Safe Whitespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.5 Detail Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075.5.1 RowIroning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075.5.2 Optimal Branch-and-Bound Placement . . . . . . . . . . . . . . . . . . 1075.5.3 Greedy Cell Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.6 Placement for Routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.6.1 Optimizing Steiner Wire length . . . . . . . . . . . . . . . . . . . . . . . . 1105.6.2 Congestion-Based Cutline Shifting . . . . . . . . . . . . . . . . . . . . . 112

5.7 Improved RTL Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.7.1 Selective Floorplanning for Multimillion Gate Designs . . . . . 1135.7.2 Temporary Macro Deflation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165.7.3 Whitespace Reallocation Using Linear Programming

and Min-Cost Max-Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.8 Incremental Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.8.1 General Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185.8.2 Fast Cutline Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195.8.3 Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205.8.4 Handling Macros and Obstacles . . . . . . . . . . . . . . . . . . . . . . . . 1225.8.5 Relaxing Overfullness Constraints . . . . . . . . . . . . . . . . . . . . . . 1225.8.6 Satisfying Density Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.9 Memory Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

x Contents

5.10 Performance on Publicly Available Benchmarks . . . . . . . . . . . . . . . . . 1255.10.1 Routing Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255.10.2 Mixed-Size Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265.10.3 ISPD Contest Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129


6 Congestion Minimization in Modern Placement Circuits . . . . . . . . . . . . 1356.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.2 Overview of Dragon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.2.1 Framework of Dragon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376.3 Mixed-Size Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.3.1 Macro-Aware Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396.3.2 Bin-Based Simulated Annealing . . . . . . . . . . . . . . . . . . . . . . . . 1416.3.3 Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6.4 Congestion Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426.4.1 Rent’s Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436.4.2 Peak Congestion Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436.4.3 Regional Congestion Estimation . . . . . . . . . . . . . . . . . . . . . . . . 146

6.5 Congestion Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536.5.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1546.5.2 Row White Space Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 1556.5.3 Grid White Space Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 1576.5.4 Placement Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576.5.5 Post-Allocation Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 157

6.6 Target Utilization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586.7 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Part IV Multilevel Placement Techniques

7 APlace: A High Quality, Large-Scale Analytical Placer . . . . . . . . . . . . . 1677.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677.2 Clustering and Unclustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697.3 Global Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

7.3.1 Constrained Minimization Formulation . . . . . . . . . . . . . . . . . . 1717.3.2 Quadratic Penalty Method and Conjugate Gradient Solver . . 1747.3.3 Multi-Level Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

7.4 Legalization and Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 1777.4.1 Global Moving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777.4.2 Whitespace Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787.4.3 Cell Order Polishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

7.5 ISPD’06 Contest and APlace3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Contents xi

7.5.1 Exploring Alternative Wirelength Functions . . . . . . . . . . . . . . 1817.5.2 Exploring Alternative Density Functions . . . . . . . . . . . . . . . . . 182

7.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

8 FastPlace: An Efficient Multilevel Force-Directed PlacementAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938.2 Overview of the Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948.3 Quadratic Placement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1968.4 Hybrid Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

8.4.1 Clique and Star Net Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988.4.2 Hybrid Net Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

8.5 Cell Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018.5.1 Shifting of Standard-cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018.5.2 Shifting of Macro-Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028.5.3 Addition of Spreading Forces . . . . . . . . . . . . . . . . . . . . . . . . . . 204

8.6 Iterative Local Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058.6.1 Bin Structure for r-ILR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068.6.2 ILR for Simultaneous Spreading and Wirelength

Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068.6.3 ILR for Handling Placement Blockages . . . . . . . . . . . . . . . . . . 2068.6.4 ILR for Placement Congestion Control . . . . . . . . . . . . . . . . . . 208

8.7 Clustering for Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098.7.1 Two-Level Clustering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 209

8.8 Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128.8.1 Legalization of Macro-Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 2128.8.2 Legalization of Standard-Cells . . . . . . . . . . . . . . . . . . . . . . . . . 215

8.9 FastDP: Efficient and Effective Detailed Placement . . . . . . . . . . . . . . 2158.9.1 Global Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158.9.2 Vertical Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198.9.3 Local Re-Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198.9.4 Single-Segment Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

8.10 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2228.10.1 Runtime Analysis of the Algorithm . . . . . . . . . . . . . . . . . . . . . 2228.10.2 ISPD-2005 Placement Contest Benchmarks . . . . . . . . . . . . . . 2228.10.3 ISPD-2006 Placement Contest Benchmarks . . . . . . . . . . . . . . 2248.10.4 PEKO-MS Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225


9 mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement . . . . 2299.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2309.3 Fixed Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

xii Contents

9.3.1 Fixed-Points and Force-Equilibrium State . . . . . . . . . . . . . . . . 2319.3.2 Fixed-Points Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

9.4 Fixed-Points Addition-Based Placement . . . . . . . . . . . . . . . . . . . . . . . 2359.4.1 Fixed Points vs. Constant Forces . . . . . . . . . . . . . . . . . . . . . . . 2359.4.2 Fixed Points in Global Placement . . . . . . . . . . . . . . . . . . . . . . . 2369.4.3 Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

9.5 mFAR: Multilevel Fixed-Point Addition-Based Placement . . . . . . . . 2409.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

9.6.1 ISPD05 Placement Contest Benchmarks . . . . . . . . . . . . . . . . . 2429.6.2 ISPD06 Placement Contest Benchmarks . . . . . . . . . . . . . . . . . 2429.6.3 PEKO 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2439.6.4 PEKO 2006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243


10 mPL6: Enhanced Multilevel Mixed-Size Placement with CongestionControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24710.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24710.2 Definitions and Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24810.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24810.4 Multilevel Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

10.4.1 Coarsening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25010.4.2 Relaxation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25310.4.3 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25310.4.4 Multilevel Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

10.5 Generalized Force-Directed Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 25510.5.1 Constrained Minimization Problem Formulation . . . . . . . . . . 25610.5.2 Problem Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26010.5.3 Analysis and Enhancements of the GFD Algorithm . . . . . . . . 263

10.6 Legalization and Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 27410.6.1 Macro Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27610.6.2 Cell Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28110.6.3 Further Wirelength Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 283

10.7 Numerical Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

11 NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs 28911.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28911.2 Analytical Placement Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29011.3 Core Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

11.3.1 Global Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29211.3.2 Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29711.3.3 Detailed Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

11.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30311.4.1 Dynamic Step-Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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11.4.2 Look-Ahead Legalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30311.4.3 HPWL and Runtime Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 30311.4.4 Wire-Model Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30611.4.5 PEKO-MS Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

12 Conclusion and Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Foreword

I have a very clear memory of the first time I ever read anything about placementalgorithms. I was a graduate student, and the research community was cracklingwith the excitement and challenges of the early days of the “VLSI” revolution. Iwent to my university’s library to track down a copy of the book chapter “PlacementTechniques” by Maurice Hanan and Jerome M. Kurtzberg, in Mel Breuer’s bookon Design Automation of Digital Systems. This was an eye-opening experience fora young student. The seminal Hanan-Kurtzberg material was a wonderfully clearreview of what was known at the time about placement problems; it was a beautifulmix of geometry, algorithms, heuristics, optimization, and real experiments on real(and by today’s standards, really small) designs. Reading this paper was a significant“Aha!” moment in my own career in the physical design area.

The intervening decades have dramatically broadened the portfolio of success-ful placer strategies, beyond the simple iterative improvement and partitioningapproaches of those early days. We have more powerful iterative paradigms likeannealing; we have vastly improved partitioning technologies; we have large-scaleanalytical solutions that formulate and solve enormous numerical optimization prob-lems; we have clustering and multi-scale methods; and we have a hierarchy ofgeometric models, from coarse initial placement to final legalization. In this vastlymore complex landscape of challenges and solutions, where does the enterprisingstudent of placement look to figure out what’s what in the placement business today?

This book, I hope.Based on a set of placers that competed in recent contests sponsored by the ACM

International Symposium on Physical Design (ISPD), and using the tremendouslyimportant sets of common placer benchmarks associated with ISPD, this volumeoffers an excellent overview of what we know about placement today. We owe agreat debt to its editors, Gi-Joon Nam of IBM and Jason Cong of UCLA, for orga-nizing all this material into one accessible and coherent volume. As our problemscontinue to grow in size, and we layer ever more constraints like timing, power andreliability on these tools, it’s clear that people are no less excited about placementproblems today than when I first read about the topic as a student.

Rob A. RutenbarCarnegie Mellon UniversityApril 2007

Preface

Research in placement algorithms for VLSI circuits has enjoyed a renaissance inrecent years. Today, there are a number of high quality academic placers that havebeen developed in universities. The amount of research on this topic clearly reflectsthe importance of the placement as the single most critical component for achiev-ing timing/design closure in a modern physical synthesis tool. Placement algorithmitself has been researched for more than three decades. Yet, the problem is still verychallenging for multiple reasons. First, the exponential increase of the circuit den-sity according to Moore’s Law has led to designs with tens of millions of placeableobjects today. Although such complex designs are composed hierarchically basedon the logic or function hierarchy, multiple studies (e.g. [3]) show that placementbased on the logic hierarchy may lead to considerably inferior results. The preferredmethodology is to place the entire design flat (with millions or tens of millions ofplaceable objects) to derive a good physical hierarchy and then use it to guide thesubsequent physical synthesis process. Therefore, the modern placers have to handleextremely large problem sizes. Second, today’s System-on-Chip (SoC) designs intro-duce complex constraints, such as routability and timing constraints, as well as thesupport of mixed size macros, area I/Os, multi-Vt and multi-Vdd islands for poweroptimization. Moreover, recent work on placement optimality studies ([1,2]) suggestthat there exists significant room for improvement even for wire length optimizationalone (details will be discussed in Chap. 2). All these reasons stimulated renewedinterests in research in circuit placement problems, both in academia and industry, inthe past a few years.

To help further stimulate advances in placement research, ISPD (InternationalSymposium on Physical Design [7]) hosted two placement contests using new, large-scale benchmark suites based on real industrial designs ( [5, 6], see Chap.1 for moredetailed discussion). The common goals of the two ISPD placement contests were:

• To provide new modern placement benchmarks to stimulate new development inplacement research

xviii Preface

• To provide a common basis for quantitative measurements of contemporaryplacement algorithms, and help the academic community to publicize their place-ment tools and results

• To provide an educational forum on a variety of state-of-art placement algorithmsfor future placement researchers

These two placement contests were huge success with participation from anumber of academic placers and provided a common platform to evaluate variousplacement algorithms on the same set of realistic benchmarks. This book is the prod-uct of these academic efforts on placement contests and it can be considered as theyear 2006 snapshot of state-of-the-art modern placement techniques employed in thefield. The book provides in-depth description of the best practices of placement algo-rithms used in the research community today. Each book chapter provides detaileddescription of the underlying algorithm and implementation features of a place-ment tool that participated in the two contests, including the experimental resultson ISPD placement benchmark circuits and the optimality analysis on PEKO-MSbenchmarks.

This book is organized in four parts:

• Part I introduces placement benchmark suites. In Chap. 1, new industry design-driven ISPD 2005/2006 benchmark circuits are presented with contest results.Chapter 2 describes the details of PEKO-MS benchmarks that can be used forplacement optimality analysis.

• Part II describes flat placement techniques, which formulate and solve the entireplacement problem directly (although the numerical solvers used in these placersmay use multilevel methods). Chapter 3 describes the most recent analyticalplacer DPlace that is an anchor cell-based quadratic placement engine. TheKraftwerk placement algorithm, the winner of ISPD 2006 placement contest,is presented in Chap. 4.

• Part III presents top-down partitioning-based placement techniques. It includesCapo, a congestion driven placer (Chap. 5) and the Dragon placer that combinessimulated annealing optimization with a partitioning algorithm (Chap. 6).

• Part IV is about multilevel placement methods that have attracted significantattentions recently. It covers APlace (Chap. 7), which was the winner of the2005 placement contest, the runtime efficient force-directed placer, FastPlace(Chap. 8), the mFAR fixed-point addition based placer (Chap.9), and the multi-level non-linear optimization placer mPL (Chap. 10) that produced the highestquality solutions in the 2006 placement contest. Also, NTUplace3 (Chap. 11), anew analytical placer for large scale mixed-size designs, is presented here.

The idea of this book emerged in April 2006, right after the ISPD 2006 place-ment contest, as a way of capturing a technology snapshot of dominant placementalgorithms. We sent out invitations to all placement contest participants, and everyteam agreed to contribute to this book. By February 2007, all chapter manuscriptswere submitted. In fact, some of them included the latest progress they made afterthe 2006 placement contest. Therefore, the results reported in some of the chapters

Preface xix

are different (better) from the original placement contest results, which we providedat the end of Chap. 1 for reference.

The editors are well aware of the limitations of placement objectives used in thetwo contests. The 2005 contest uses wire length minimization as its sole objectivefunction, while the 2006 contest uses a combination of wire length minimization, celldensity control and runtime as its objective function (see Chap. 1 for more details).Real placement problems need to consider a number of other objectives, such as tim-ing, power, and thermal optimization, as well as interaction with various physicalsynthesis operations, such as buffer insertion and gate sizing. A direct comparisonof different placers under all these objectives and constraints may not be possible ormeaningful, as each design has its own emphasis, and the final result is not deter-mined by the placement algorithm alone. Many other steps, such as timing analysis,global and detailed routing, and various physical optimization operations can affectthe final result. Therefore, we think that it is appropriate to use rather simple metricsin the two placement contests to measure the capability of the core wire length opti-mization engines employed in the different placers. As pointed in [4], a placer withgood wire length minimization engine can be extended to handle other design objec-tives through weighted wire length minimization using various weighting functions.

This book is intended for graduate students, researchers, and CAD tool develop-ers in the physical synthesis and physical design area. Each chapter is mostly self-contained and can be read independently. We hope that the readers can benefit fromthis collection of modern placement algorithms and potentially contribute to the fieldwith new perspective. Please note this book is not intended to provide a comprehen-sive review of all available placement techniques, but to highlight the most successfultechniques and practices used in modern placers. We refer the reader to [4] for a morecomprehensive survey for the existing placement techniques.

We would like to thank the ISPD organizing committee for sponsoring the twoplacement contests, and IBM Corporation for providing the benchmark examples.We are indebted to the time and efforts of all the chapter authors who made this bookpossible. Finally, we would like to thank David Papa at the University of Michiganfor thorough reviews of all chapters.

Gi-Joon NamIBM ResearchAustin, Texas

Jason CongUniversity of CaliforniaLos Angeles, California

March 2007

xx Preface

References

1. C.-C. Chang, J. Cong and M. Xie, “Optimality and Scalability Study of Existing Place-ment Algorithms,” Asia South Pacific Design Automation Conference, 2003, pp. 621–627

2. C.-C. Chang, J. Cong, M. Romesis and M. Xie, “Optimality and Scalability Study ofExisting Placement Algorithms,” IEEE Transactions on Computer-Aided Design of Inte-grated Circuits, pp. 537–549, April 2004

3. J. Cong, “An Interconnect-Centric Design Flow for Nanometer Technologies”, Proceed-ings of the IEEE, vol. 89, No. 4, pp. 505–528, April 2001

4. J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan, “Large Scale Circuit Placement,”ACM Transaction on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 389–430, April 2005

5. Gi-Joon Nam, “ISPD 2006 placement contest: Benchmark suite and results,” Proceedingsof the International Symposium on Physical Design, pages 167–167, 2006

6. G.-J. Nam, C.J. Alpert, P. Villarubbia, B. Winter, and M. Yildiz, “The ISPD2005 place-ment contest and benchmark suite,” Proceedings of the International Symposium on Phys-ical Design, pages 216–219, 2005

7. http://www.ispd.cc

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