belle upgrade r&d: recent developments @ uhidlab/presentations/bgm_mar03.pdf · belle upgrade...

Belle Upgrade R&D: Recent Developments @ UH

Gary S. VarnerUniversity of Hawai

,i

Belle General MeetingMarch 2003

1Gary S. Varner, Belle General Meeting: March 25, 2003

What’s New?

• MTS1 Fabrication – Arrived beginning of year– TOP/precision timing readout candidate

• STRAW2 Fabrication– Another precision timing option– Built in TWC/Pile-up handling

• COPPER Eval board– High speed FE electronics emulator

• What next


Time-to-Time – Clocked and MTDC

2ns

e- e-

Sample edges with 500ps resolution


TS + MTDC Performance

• ~20ps jitter

σ = 22.5ps+50ps

-50ps


Works Well, Why Change?

• LRS Demise– Unobtainium– Use new generation of

precision, low deadtime multi-hit TDCs

– Form-factor• Lower card costs, many channels• FINESSE/COPPER (PMC)

– For TOP want multi-hit truly deadtimeless

• Min. δT >= 10ns (HPTDC) [5ns typ.]

– Reference to RF bunch and self-calibration

32 LVDS inFINESSE

COPPER interface


Electronics – scenarios

Bar TOP

~5mm pos. resolution: 40 Ch/counter

Butterfly TOP

*200 counters = 1440 channelsMulti-hit (hidden cost) >1440 channels

Focusing DIRC

~few mm x few mm: few kCh/counter

*~100 counters: few 100k channels

~1mm pos. resolution: 200 Ch/counter

*180 counters = 36,000 channels


Time Stretcher Module

• Designed

with LRS

– R&D 100 Award

VIPA StandardModule

16 Channels/1 per DC

Stretch factor20x

RF clockReference


MTS1 Layout

•Presented at 3rd Belle Upgrades Meeting

• Sent for Fab. Sept 16, back mid-Dec.

•Agilent 0.5µm process


MTS1 Silicon (1)

LVDS Rx

LVDS Tx


MTS1 Silicon (2)

Completely differential

signal routing


Evaluation Board

CPLD (programmable

logic)MTS1 chip

Bottom view

Top view TTL-LVDS translator

• Quick and simple test board – avoid complexity unless MTS1 shown to work – found bias changes!


Test Station

Bottom view

GPIB -Ethernet

• Software readout works – but very slow (1/4 Hz)


TS SPICE Output

Ramp

Output to TDC

Ref

Input:4:1 Stretch

Ratio

25ps 100ps lsb


Output Signal

• Measured with a 5GSa/s scope (500MHz ABW) ……200ps/sample


TS SPICE Simulation

• Simple fit:

Time Stretcher SPICE Simulation

y = 3.7503x + 4.9388R2 = 1

0

20

40

60

80

100

120

140

17 19 21 23 25 27 29 31 33

Input Time difference [ns]

Str

etch

ed T

ime

[ns]


MTS1 Timing Residuals

SF~15 for this test

(scope optimization)

40MHz RF clock

• After trying many things, still getting clock feedthrough – however can be simply calibrated


MTS1 Timing Residuals

σ ~ 49ps

RMS ~ 51ps

• However, this value includes the (large) system jitter


System Jitter

σ ~ 49.5ps

22meas JitterMTS1

σσσ −=

22 )5.49()3.51( −=

Use RMS value

σ ~ 13.5ps

• Don’t believe it, but promising and impetus to put together a better test system


Direct Residuals Comparison

• Comparable: MTS1 Time Stretcher residuals2002/07/26 14.06

σ = 22.5ps

Residual Timing (ns)

0

1

2

3

4

5

6

7

-0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2

IDEntriesMeanRMS

101 16

0.4500E-02 0.2199E-01

0.3788 / 1Constant 6.085Mean 0.6607E-02Sigma 0.2633E-01

tsref3.ntp

σ = 26.3ps

RMS = 22.0ps

LRS module test

MTS1 Simulation


Time Walk Correction

• Reasonable functional form– But as background increases…

tFixed threshold

V

T0

Twc

ADCGate

Q

Sensitive to “3 Effects”

• Many ideas: e.g. direct digitization at high speed?


STRAW2 Chip Self-Triggered Recorder Analog Waveform (STRAW)

16 Channels of256 deep SCA buckets

Optimized for RF inputMicrostrip 50Ω

Follow-on to the ATWDChip (LBL)

Target input Bandwidth:>700MHz

-LL and HL (adj.) for each channel

Sampling Rate:1-2GSa/s (adj.)

-Multiplicity triggerfor LL hits

On-chip ADC:12-bit, >2MSPS

Primary application:Askaryan-effect RFUHE cosmic detectors External option:

MUXed Analog out

Sampling Rates>~8GSa/s possiblew/ 0.25µm process

8192 analog storage cells

Die:~2.5mm2 Possible to get rid of TDC: muegamma

Self-Triggering:


Antarctic Impulsive Transient Antenna (ANITA)

M. R

osen, Univ. of H

awaii

ANITAGondola &

Payload

Antenna array

Cover (partially cut away)

Solar Panels

• ANITA Goal: Pathfinding mission for GZK neutrinos

• NASA SR&T funded Nov. 2002, launch in 2006


STRAW2 Evaluation

• RF signal input

• Adjustable: 0.6 –3.4 GSa/s

• 256 samples (70 –300ns)


RF Response

• Sub-ns transient ping: <= 100ps leading edge

Scope ET sampling:100 Gsa/s equiv.


πβ Domino Chip (thanks to S. Ritt)

C. Brönnimann et al., NIM A420 (1999) 264

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout

Pile up handling


TOF Counter Test

STRAW2 (uncal.) vs. TDS scope

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0 10 20 30 40 50 60

Time [ns]

STR

AW

[V],

scop

e[sc

aled

V]

scope (4GSa/s)STRAW2

TOF Counter, FM-PMT

STRAW2 chip sampling @ 3.3 Gsa/s

@ 3.3 Gsa/s, 15 samples on 5ns

risetime leading edge


Precision Timing Estimate

• Time base stability– Jitter tiny (<= 10ps?)– Can phase lock to KEK-B RF clock

• Leading edge fitting– A la g-2 (NIM …)– Completely immune to backsplash– Significant robustness for pile-up– True multi-hit extraction– New way to get at systematics limitation

• Crude estimate:– For 300ps steps, 100mV min sensitivity in threshold region:

– 5mV quantization extrapolation 15ps resolution– Needs real evaluation – can test with good DSO


FIFOFIFO

FIFOFIFO

FIFOFIFO

FIFOFIFO

MemoryMemory

CPUCPU

Bridge

Local Bus PCI Bus

VME-9U Module

Det

ecto

r Si

gnal

s

User I/OUser I/O

User I/OUser I/O

User I/OUser I/O

User I/OUser I/O

Trigger inputTrigger interrupt

BridgeBridge

Mezzanine Cards

PCI Mezzanine Cards

ControlControl BridgeBridge

USB 2.0

Rear B

oard

FINESSE

SPIGOT

COPPER

Performance Evaluation

•Develop “evaluation” FINESSE (to exercise COPPER), as well as “test data” FINESSE for Sub-detector software tests


CuEval FINESSE

• Front-end INstrumentation Entity for Sub-detector Specific Electronics

Dual 128kB RAM480 Mbps USB2.0

COPPER Interface

Hardware “ready” – Yangheng working on USB drivers


Summary

• MTS1 Future– Some work on linearity needed, multi-hit functioning– Proper test board, CAMAC readout (<<50ps intrinsic noise)– Unfortunately Agilent 0.5µm no longer supported by MOSIS– Enough for prototyping (~20 chips), but may want to migrate to

TSMC 0.35µm process [MTS2]– CFD ASIC upstream [BCFD1]

• STRAW2 Future– STRAW3 (fix known bugs)– COW (Completely Oversampled Waveform) chip– Experiment with achievable time resolution for TOF counter (&

TOP prototype eventually…)

• CuEval prototype– TOP readout, APV25 readout, …

And…


Thoughts on the Future (1)

• Monolithic Pixel Detector– STAR prototype under test at UH:

8 cm

l 20 µm square pixels

λ5 chips per slat

λ90 million pixels

λ40 µm thick chips

Fang working on, Plan pixel proto(TSMC process)This fiscal year

(if get Nichi-bei funds) 20µm2 pixel proto

Many thanks to S. Kleinfelder (UC Irvine),& F. Bieser, H. Matis & H. Wieman (LBNL)


Thoughts on the Future (2)

• Composite Pixel Detector– XTEST2 architecture a winner for high-speed readout

50µm

• Essentially XTEST2 architecture – 8-bits, 37 transistors ~10µm2

– 1G pixels/s P=50mW

Fab. Detector on top


Back-up Slides

• Stuff for further rumination, if queried


TOP Counter

• Looks good, though Time-of-Propagation depends on photon wavelength


Single Point Measurement

• Maximize R for better pointing… trigger latency

+

= δυυυ

υε)/(4.01

11 00

0

TeVW

RKAE T

r

Empirically determined

Material, aperture DecoherenceFreq.

R

• Squeeze all possible info.


COPPER Hardware

COPPER Board

FINESSE

FINESSE

FINESSE

FINESSE

VME-9U size board

PMC

PMC

PMC for CPU

Front

Rear

SPIGOT

• VME and PCI interfaces


FINESSE Hardware• Dimensions

- Depth × Width = 168.0(d) × 71.0(w) mm2.

• Layout example

COPPER side

component side

• “PMC” form factor -- compact


Test Control (w/o Trig/DAQ)

Control to FIFOs

(Max. 480 Mbit/s)

USER IO card for COPPER testing

DATA to FIFOs

Trigger

Interrupt to CPU

USB 2.0

Rear Board

registers

RAM

registers

FINESSE

SPIGOT

• Use memory mapping for control + CPLD/FPGA


Trex Enterprises HDTV

Located in Maui

HNEI doing prototypeDeposition work

Designing a 500M pixel array

• micro/nano crystalline Si deposit on HDTV


Interesting Possibility

Top electrode

Combine both!

Would allow redundancy at higher noise rates

Some compatibility issues in choice of

circuits


Current thoughts

• Parallel efforts

Exploration/DesignEvaluation

• High Speed readout

• Pipelined readout

• Better SNR:

•improve detector

•lower noise

• TSMC submission possible (Nichi-bei request)

• Gain experience

• Understand practical limits on performance

• Feedback to design process

• Give grad students/ post-Docs some experience with pixels


template

• Simple fit:

belle upgrade r&d: recent developments @ uhidlab/presentations/bgm_mar03.pdf · belle upgrade...

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