Behavioral Modelling - 1

Verilog Behavioral Modelling

Behavioral Models represent functionality of the digital hardware.

It describes how the circuit will operate without specifying hardware.

There are two important keywords for behavioral description.

initial Specifies a single-pass behavior.always Specifies cyclic behavior.

Behavioral Modelling

initial keyword is followed by a single statement or a begin…end block

The statement following initial is executed once at t=0 and it expires.

always keyword is followed by a single statement or a begin…end block

The statement following always is executed repeatedly until simulation is stopped.

Chapter 5 3

Use of initial and always Chapter 5 4

Use of initial and always.

Defines a clock with 20 unit clock period.

Chapter 5 5

always and event control @

always @(event control expression) begin ....... end@ is called event control operator.always @(event) waits until the event occurs.When event takes place begin.. end block will be executed.Example: wait for positive edge of clock always @(posedge clock) always @(posedge clock or negedge reset)

Chapter 5 6

always @ (A or B or C or OUT2)

/* Note: OUT2 is output of one statement but input of another statement */

begin

OUT1 = (A&B) | (B&C) | (C&A) ;

OUT2 = {A,B,C};

OUT3 = OUT2 >>> 2;

OUT4 = OUT2 << 1;

/* inside the always block all instructions are executed sequentially, like in programming languages (exceptions will be mentioned later) */

end

Multiple statements in always block

always @ (A or B or C)

OUT1 = (A&B) | (B&C) | (C&A);

always @ (A, B, C)

OUT2 = {A, B, C};

always @ (*)

OUT3 = OUT2 >> 1;

/* All the three always blocks will run concurrently i.e. all the LHS of each of the always blocks will be calculated at the same instant of time */

Multiple always blocks

Procedural Blocks

module MultiplexerD (input a, b, s, output w);reg w;always @(a, b, s) begin

if (s) w = b;else w = a;

endendmodule

always statement

if-else statement

Can be used when the operation of a

unit is too complex to be described by

Boolean or conditional expressions

Sensitivity list

There are two types of assignments in verilog.

In blocking assignment the instuctions are executed sequentially one after the other.

In non blocking the left hand side is assigned the value of the right hand side simultaneously at the end of the simulation timestep. These statements are executed in parallel.

Blocking and non blocking assignments

Blocking and Nonblocking assignment examples

Blocking assignment: Evaluation and assignment are immediatealways @ ( a or b or c)begin

x = a | b; //Evaluate a|b and assign value to xy = a ^ b ^ c; // Evaluate a^b^c and assign value to yz = b & ~c; //Evaluate b & ~c and assign value to z

end Non Blocking assignment: Assignments deferred until right

hand side has been evaluated (assigned at the end of timestep)always @ (a or b or c)begin

x <= a | b; //Evaluate a|b but defer assignment of xy <= a ^ b ^ c; // Evaluate a^b^c but defer assignment of yz <= b & ~c; // Evaluate b & ~c but defer assignment of z

end

Blocking vs. Nonblocking

If A=3 and B=5B=A ;

C=B+2 ....... will set B=3 and C=5B<=A ;

C<=B+2 …… will result B=3 and C=7

Chapter 5 12

Swap Operation Blocking

always @ (*)begin

temp = b;b=a;a=temp;

end Non blocking

always @ (*)begin

a<=b;b<=a;

end

Blocking and non blocking assignments

module blocking (in, clk, out);input in, clk;output out;reg out, q1, q2;

always @ (posedge clk)begin

q1 = in;q2 = q1;out = q2;

endendmodule

Blocking and non blocking assignment examples

module nonblocking(in, clk, out);input in, clk, out;output out;reg q1, q2, out;

always @ (posedge clk)begin

q1 <= in;q2 <= q1;out <= q2;

endendmodule

Circuits which the above code is synthesized to

Blocking Assignment Non Blocking Assignment

You represent all your combinational logic by blocking assignment.

You represent all your sequential logic by non-blocking assignment

Rule of thumb

Flip-Flop

`timescale 1ns/100ps

module Flop (reset, din, clk, qout);input reset, din, clk;output qout;reg qout;always @(negedge clk) begin

if (reset) qout <= 1'b0;else qout <= din;

endendmodule

Synchronous reset input

A Signal declared as a reg to be

capable of holding its values between

clock edges

Flip-Flops are used in data part for flags

and data storage

A Non-blocking Assignment

A Software-Like

Procedural Coding Style

Flip-Floptriggers on the falling edge of clk

Input

The Body of always

statement is executed at the negative edge of

the clk signal

D flip-flop with active-low asynchronous reset

D

clk

Q

Q_n

reset_n

Behaviour of the circuit

reset_n is active low signal which clears output when low

Q and Q_n are complimentary outputs of the flip flop

On the positive edge of the clock the input D is passed on to the output Q.

D flip-flop with active-low asynchronous reset

always @ (posedge clk or negedge reset_n)begin

end

if(reset_n == 0)begin

Q <= 0;Q_n<=1;

endelsebegin

Q <= D;Q_n <= !D;

end