Beam Secondary Shower Acquisition System: 2014_11_24_GBT_On_Igloo2 Release BE-BI-BL Jose Luis Sirvent Blasco 2 Jose Luis Sirvent Blasco PhD. Student STUDENT MEETING 01/12/2014 1.Introduction 1.1 Why a new releaseagain? There were many issues to solve Interfaces SERDES / GBT code synchronization not guaranteed Readability of the code now more clear Update of GBT_FPGA Release (Now there is a new one!) Libero 11.4 was upgraded with a SP1 Clock constraints were defined on GUI interfaces, not on SDC files. Debugging only possible with Console Application Needed Console application for Start-up the link New functionalities were needed: Possibility of selecting SERDES Lane Possibility of selecting REFCLK for SERDES This code aims to be the firmware for the CMS Igloo2 Umd mezzanine board. Other people will use this code and customize for their needs CMS, LHCb BE-BI-BL Jose Luis Sirvent Blasco 3 By the way! This board is now being tested on the US. Well receive ours soon 3. Providing Synchronization 3.1 SERDES / User-logic interface So far synchronization was reached using delay lines on de data bus This was Microsemis advice but not really flexible After each place-route the components are on different locations Maybe needed to put/remove delay lines Or apply physical constraints to fix location of individual flip-flops This was unacceptable! Not flexible design for other applications Other option advice to place a memory-based FIFO after RX part If used, the code would not be latency deterministic, and the frame clock recovery would not work well Many time invested on trying different approaches for synchronization: Playing with logic Using clock buffers Placing registers triggered with buffered/unbuffered clock Playing with synthesis and compilation constraints and checking timming report: Multy-cycle paths False paths Max delay analysis Min delay analysis BE-BI-BL Jose Luis Sirvent Blasco 4 3. Providing Synchronization 3.1 SERDES / User-logic interface A lot of time spent reading SERDES documentation General rule for clock domain crossing: This is a thumb rule Use pipelined registers Official Advice according Microsemi documentation: Sample RX data on the rising edge of EPCS_RX_CLK Allways adopted this as a rule for my design Consider first interface with SERDES with Unbuffered clock Trigger all the GBT code with the Buffered Clock on the global clocking network. Never reaching constraints after modifications. BE-BI-BL Jose Luis Sirvent Blasco 5 3. Providing Synchronization 3.1 SERDES / User-logic interface A lot of time spent reading SERDES documentation General rule for clock domain crossing: This is a thumb rule Use pipelined registers Official Advice according Microsemi documentation: Sample RX data on the rising edge of EPCS_RX_CLK Allways adopted this as a rule for my design Consider first interface with SERDES with Unbuffered clock Trigger all the GBT code with the Buffered Clock on the global clocking network. Never reaching constraints after modifications. Suddenly I decided to sample on the falling edge on RX part and voila! BE-BI-BL Jose Luis Sirvent Blasco 6 7 3. Providing Synchronization 3.1 SERDES / User-logic interface 3. Providing Synchronization 3.2 Timing constraints Distributed on two SDC files (we do not use the GUI anymore): GBT_On_Igloo2_M2GL_EVAL_KIT_Synthesis.sdc Word_Clocks 250MHz Frame_Clocks 40MHz Fabric_Clock 50MHz Attribute syn_noclockbuff in some Rx_Word_CLKs Each clock assigned to an independent group. ADVICE: Perform always synthesis with retiming!! GBT_On_Igloo2_M2GL_EVAL_KIT_Compile.sdc Word_Clocks 250MHz Reset signals considered asynchronous (false path) Frame_Clocks 40MHz Fabric_Clock 50MHz False paths between clock domains to consider clocks independent. CAUTION: On the world_clks section only the selected lane must be uncommented!! ADVICE: Perform place and route with Timing driven and High effort layout BE-BI-BL Jose Luis Sirvent Blasco 8 4. New Functionalities SERDES LANE and REFCLK selection: 3 Lanes and 3 possible REFCLKs Selectionable through the file: gbt_banks_user_setup.vhd Synthesis tool will directly implement the needed logic to use the selected lane and refclk BE-BI-BL Jose Luis Sirvent Blasco 9 4. New Functionalities Debugging: Link active at start-up Possible trough SmartDebug (through JTAG) No exclusive need of Console Application Need to select the suitable signals to read/write Indications on Release Notes Essential signals for link diagnostics promoted to top level Code prepared for Igloo2UMd_Mezzanine board BE-BI-BL Jose Luis Sirvent Blasco 10 5. Where to find the firmware? Dropbox: https://www.dropbox.com/sh/hs4xzi3sn0cv2ww/AACYpkFhM3hfYAuc9kOqDRWsa?dl=0 SVN: https://svn.cern.ch/reps/be-bi-bl/electronics/bwsdev/studies/BWS_pCVD Diamond detector Readout Electronics/GBT_On_Igloo2/Firmware/GBT_FPGA_Igloo2/LATOP TWIKI: Ill try to maintain a bit this site with news and updates Nicer interface to present the firmware and offer some information https://twiki.cern.ch/twiki/bin/view/Sandbox/JoseLuisSirventBlascoGBT_On_Igloo2 BE-BI-BL Jose Luis Sirvent Blasco 11