batch 12 wafer 7 summary comparison to baseline. n+ sheet resistance ( / ) wide structure method,...
TRANSCRIPT
batch 12 wafer 7 summary comparison to baseline
N+ Sheet Resistance (/ ) Wide structure method, Target = 30 /
WID
E: N
+ sh
eet r
ho (
Ohm
s/sq
)
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
WID
E: N
+ sh
eet r
ho (
Ohm
s/sq
)
0
20
40
60
80
100
120
140
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
N+ Sheet Resistance wafer map
waf
er f
lat
N+ sheet resistance statistics
P+ Sheet Resistance (/)Wide structure method, Target = 39 /
WID
E: P
+ sh
eet r
ho (
Ohm
s/sq
)
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
WID
E: P
+ sh
eet r
ho (
Ohm
s/sq
)
0102030405060708090
100110120
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
P+ sheet resistance statistics
Poly Sheet Resistance (/)Wide structure method, Target = 49 /
WID
E: P
L sh
eet r
ho (
Ohm
s/sq
)
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
WID
E: P
L sh
eet r
ho (
Ohm
s/sq
)
0
20
40
60
80
100
120
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Poly Sheet Resistance wafer map
waf
er f
lat
Poly wide sheet resistance statistics
Poly CD Narrow #1 & #2 (m)Target = 2m
CD
PLN
AR
R1
(um
)
0
1
2
3
4
5
6
7
8
9
10
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
CD
PLN
AR
R2
(um
)
0
1
2
3
4
5
6
7
8
9
10
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Poly CD statistics
Poly COMB leakage (A)Target = 1E-12 A
IPLC
OM
B1L
1e-14
1e-12
1e-10
1e-8
1e-6
1e-4
1e-2
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Poly COMB leakage statistics
Poly Serpentine Resistance ()Target = 166 k
RP
LSE
RP
1
1e+21e+31e+41e+51e+61e+71e+81e+9
1e+101e+111e+121e+131e+14
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Poly serpentine resistance statistics
NMOS & PMOS Threshold Voltage (V)W=5 m, L=varying*
PM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Threshold Voltage (V)W=10 m, L=varying*
NM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
VT w=10, l=5um statistics
NMOS & PMOS Threshold Voltage (V)W=50 m, L=varying*
NM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Vt
-3
-2
-1
0
1
2
3
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Saturation Current (A)W=5 m, L=varying*, Log10 scale
NM
OS
Log
(ab
s(ID
sat)
-12-11-10-9-8-7-6-5-4-3-2-10
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g(a
bs(
IDsa
t)
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Saturation Current (A) W=10 m, L=varying*, Log10 scale
NM
OS
Log
(ab
s(ID
sat)
-14
-12
-10
-8
-6
-4
-2
0
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g(ab
s(ID
sat)
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Saturation Current (A) W=50 m, L=varying*, Log10 scale
NM
OS
Lo
g(a
bs(
IDsa
t)
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g(a
bs(
IDsa
t)
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Off Current (A)W=5 m, L=varying*, Log10 scale
NM
OS
Lo
g1
0(a
bs(
LD
))
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g1
0(a
bs(
LD
))
-14
-12
-10
-8
-6
-4
-2
0
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Off Current (A)W=10 m, L=varying*, Log10 scale
NM
OS
Lo
g1
0(a
bs(
LD
))
-12-11-10-9-8-7-6-5-4-3-2-10
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g1
0(a
bs(
LD
))
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
NMOS & PMOS Off Current (A)W=50 m, L=varying*, Log10 scale
NM
OS
Log
10(a
bs(
LD))
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
PM
OS
Lo
g1
0(a
bs(
LD
))
-13
-11
-9
-7
-5
-3
-1
11
.31
.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25 1
1.3
1.5 2 3 5 10
25
L
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 7 wafer
3 4 5 6 8 12 batch
N+ Contact Resistance ()Target = 0.1
RN
+CO
N1
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
N+ contact resistance statistics
N+ Contact Chain Resistance ()Target = 5k R
N+C
C1
1e+01e+11e+21e+31e+41e+51e+61e+71e+81e+9
1e+101e+111e+12
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
N+ contact chain resistance statistics
P+ Contact Resistance ()Target = 1
RP
+CO
N1
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
P+ contact resistance statistics
P+ Contact Chain Resistance ()Target = 4 kR
P+C
C1
1e+11e+21e+31e+41e+51e+61e+71e+81e+9
1e+101e+111e+121e+13
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
P+ contact chain resistance statistics
Poly Contact Resistance ()Target = 0.1
RP
LCO
N1
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
poly contact resistance statistics
Poly Contact Chain Resistance ()Target = 4.9 k
RP
LCC
1
1e+11e+21e+31e+41e+51e+61e+71e+81e+9
1e+101e+111e+121e+13
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
poly contact chain resistance statistics
M1 COMB leakage (A) Target = 1E-12A
IM1C
OM
B1L
1e-14
1e-12
1e-10
1e-8
1e-6
1e-4
1e-2
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
M1 COMB leakage statistics
M1 Serpentine Resistance ()Target = 85
RM
1SE
RP
1
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
1e+14
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
M1 Serpentine Resistance wafer map
M1 serpentine resistance statistics
M1 Van der Pauw Sheet Resistance (m/ �)target = 56.7 m/ �
VD
P: M
1 sh
eet r
ho (
mO
hms/
sq)
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
1e+14
1e+16
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batchvery high resistance
M1 sheet resistance statistics
M2 to M1 Via Resistance ()Target = 0.1
RM
1CO
N1
1e-4
1e-2
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
1e+14
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Batch 4 & 5 did not receive M2 processing
Via1 resistance statistics
M2 to M1 Via Chain Resistance ()Target = 19
RM
1CC
1
1e+0
1e+2
1e+4
1e+6
1e+8
1e+10
1e+12
11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batch
Via1 contact chain resistance statistics
M2 Van der Pauw Sheet Resistance (m/ �)target = 42.5 m/ �
VD
P: M
2 sh
eet r
ho (
mO
hms/
sq)
1e-6
1e-41e-2
1e+0
1e+21e+4
1e+6
1e+81e+10
1e+12
1e+141e+16
11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7 7
3 4 5 6 8 12
wafer within batch
3
4
5
6
8
12
batchvery high resistance
batches 4 & 5 didn’t receive M2 processing
M2 sheet resistance statistics