basics 0 review muxdec

7/31/2019 Basics 0 Review MuxDec

1/47

Digital LogicLecture 10

Combinational Logic: Decoders,Encoders, and Multiplexers

By

Ghada Al-MashaqbehThe Hashemite University

Computer Engineering Department


2/47

The Hashemite University 2

Outline Introduction.

Decoders.

Encoders.

Multiplexers.


3/47


Introduction In this lecture we will complete viewing

the standard combinational circuits.

Specifically, we will study:

Decoders.

Encoders.

Multiplexers.


4/47


Decoders I Decoder is a combinational circuit that

converts a binary value to a specific binarycode one to one mapping.

Remember that an n-bit binary code canrepresents up to a 2n binary codes. So, a decoder has the binary code as an input

and the original binary value as the output.

For an n-bit binary code, the decoder has ninputs and a maximum 2n outputs (may havefewer outputs if you have unused codes as inBCD).


5/47


Decoders II We will study the n-to-m-line decoders where m


6/47


Decoders III Truth table of 3-to-8 line decoder

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1


7/47


Decoders II


8/47


Decoders IV A particular application of 3-to-8 line decoder

is binary-to-octal conversion.

That is based on the 3-bit binary value youget which octal digit represented by thisvalue.

For example if the input is 111 convert it tooctal you get digit 7, the output of thedecoder will have a 1 (active) at D7 whichrepresent digit 7 in octal.


9/47


Active Low Decoders Constructed with NAND gates.

The selected minterm based on the input (i.e.

the active one) will have a 0 on its output lineand other unselected minterms will have 1(the inactive state for active low output line).

How to differentiate between active low and

active high decoders from its block diagram? Bubbles on the output lines active low decoder.

No bubbles on the output lines active highdecoder.


10/47


Decoders with Enable Line I The following is a general design

or block diagram of binarydecoder.

The Enable lines enables the

decoder to perform mapping. The Enable depends on

whether it is active low (have abubble in front of the line) oractive high (have no bubble infront of the line or pin).

Active low enable must have aninput of 0 to activate thedecoder.

Active high enable must beasserted (has value of 1) toactivate the decoder.


11/47


Decoders with Enable Line II Some decoders may have more than 1 enable

line where each line can be different from the

other (i.e. whether it is active high or activelow).

The state of the decoder it self (whether it isactive low or active high) is independent of

the enable line state.

So, you may have an active low decoder withactive high enable line.


12/47


Decoders with Enable Line III If a decoder is not enabled (not activated)

this means that the minterm selected by theinputs is not activated and no specific output

is selected. The inactive state depends on the type of the

decoder: Active low decoder all outputs will be high (at

level 1) when disabled (the enable line is notactivated). Active high decoder all outputs will be low (at

level 0) when disabled (the enable line is notactivated).


13/47


Active Low 2-to-4 Line

Decoder With Enable Line


14/47


Building Bigger Decoders from

Small Ones We can combine two 3-to-8 decoders to build a 4-to-16 decoder(in this figure w is the MSB and z is the LSB).

Generates from

0000 to 0111

Generates from

1000 to 1111


15/47


Combinational Logic Implementation

Using Line Decoders I Decoders can be used to implement logic

functions with the condition that these functionsmust be represented as a sum of minterms.

The minterms in the function are combinedusing an OR gate or NAND gate based on thedecoder type.

Two cases: Active high decoders: combine these minterms with

OR gate. Active low decoders: combine these minterms with

NAND gate.

Note that NAND-NAND is equivalent to AND-OR

circuit.


16/47


Combinational Logic ImplementationUsing Line Decoders II

What to do with functions that have a longlist of minterms (larger than 2n/2)?

Active high decoder: Simply get the minterms in F and combine them with a

NOR gate.

The output of the NOR gate is F.

Active low decoder:

Simply get the minterms in F and combine them with aAND gate.

The output of the AND gate is F.


17/47


Example

Design a full adder using OR gates and3x8 active high decoder.

Sol: From the truth table of full adder, the

sum-of-minterms representation of S

and C are:S(x,y,z) = (1,2,4,7)

C(x,y,z) = (3,5,6,7)


18/47


Example -- Solution


19/47


Notes

If you are given F(x, y, z) = xy + z, how youcan implement it using an active high decoder

and an OR gate? First you must define the minterms in F. the

simplest way is obtain the truth table of F and seeat which minterms it has value of 1.

The previous note is applied for anyrepresentation of F other than sum ofminterms.


20/47


Encoders

Encoders perform the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output

lines.

The output lines generate the binary codecorresponding to the input value. Two types of encoders:

Encoders with mutually exclusive inputs: only one input isactive at a time.

Priority encoders: multiple inputs can be active at the sametime.

Example of encoders with mutually exclusive inputs isoctal to binary encoders (8-to-3 line encoder).


21/47


Octal-to-Binary EncoderDesign I

Truth TableD0 D1 D2 D3 D4 D5 D6 D7 X Y Z1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Note that we need not to complete the whole table where wehave listed only 8 entries equal to the number of inputs (not 2^8entries) since only 1 input is allowed to be active at a time.


22/47


Octal-to-Binary EncoderDesign II

From the truth table we can see that theoutputs of the encoders are based on ORing

the minterms found in the inputs: z=D1+D3+D5+D7

y=D2+D3+D6+D7

x=D4+D5+D6+D7

So, the internal implementation of octal-to-binary encoder is composed of 3 OR gates.


23/47


2n-to-n Encoder DesignLimitations

This encoder has many limitations: Only one input can be active at a time, otherwise

it will produce undefined combination which do

not correspond to either of the activated inputs(based on the OR expressions). Solution: give higher priority to inputs with higher

subscripts, e.g. D5 has higher priority than D2 and so on.So, when both D5 and D1 for example are active theoutputs will be 101 since D5 has higher priority.

Note that when all inputs are 0 the output will be000 which is the same output when only D0 isactive. Solution: provide an additional output to indicate

whether at least there is one input is 1.


24/47


Priority Encoder

Priority encoder is an encoder thatsolves the limitations of 2n-to-n encoder

discussed previously (include priorityand an additional output which is calledthe valid bit (V) to indicate that at least

one input is 1). We will design a 4-to-2 priority encoder.


25/47


Priority Encoder Design I

Truth table:Inputs Outputs

D0 D1 D2 D3 x y v

0 0 0 0 X X 01 0 0 0 0 0 1X 1 0 0 0 1 1X X 1 0 1 0 1

X X X 1 1 1 1

Note that we have inserted the dont care conditions inthe input side just to avoid the need to list all 16 entries inthe truth table (not to be used in simplification as thedont care found in the output).


26/47


Priority Encoder Design II


27/47


Priority Encoder Design III


28/47


Applications of Priority Encoders

Inputs indicates a request for service. e.g., Interruptrequests.

if multiple requests are made simultaneously, the encoder

gives undesirable results. The solution is to assign priority to the input lines, priority

encoder.


29/47


Multiplexers I

Multiplexer is a combinational circuit that selects one ofthe inputs and directs it to a single output line.

It is abbreviated as a MUX.

It is also called data selector and a digital switch. The operation performed by a MUX is called election.

The selection of the inputs is controlled by a selectionlines or inputs.

In general a MUX has 2n inputs, n selection lines (impliedfrom the inputs so they are not counted with the inputs),and exactly 1 output.


30/47


Multiplexers II

Each input of the multiplexer is 1-bit only. The internal implementation of the MUX is an

AND-OR circuit. Each input is fed into one AND gate in

addition to one input from each selection line. The selection lines are very similar to the

enable line in the decoder. If their values are

1 then the AND gate is enabled, otherwisethe AND gate is disabled so the input has noeffect on the output.


31/47


Multiplexers III

A multiplexer is named as follows:(number of inputs)-to-(number of

outputs) MUX or simply (number ofinputs)X(number of outputs) MUX.

For example: you may have a 2X1 MUX,

4X1 MUX, 8X1 MUX and so on.


32/47


2X1 MUX Design I


33/47


2X1 MUX Design I

Boolean expression of the MUX outputis:

Y = I0S + I1S

Note that which input that will bepassed to the output (selected)

depends on the value of S which is theselection line here.


34/47


4X1 MUX Design I


35/47


4X1 MUX Design II

Boolean expression of the MUX outputis:

Y = I0S1S0 + I0S1S0 + I0S1S0 + I0S1S0

Note that which input that will bepassed to the output (selected)

depends on the product value of S0 andS1 which are the selection lines here.


36/47


Note

MUXs can have also enable line(s).

Similar to the decoder the enable line

will be fed into all AND gates in theMUX.

The enable line can be active high or

active low.


37/47


m-bit MUX I

Multiplexers can be combined with common selectioninputs to support multi-bit selection logic.

Remember that a MUX selects between 2n 1-bit

inputs. But what about if you want to select between2n m-bit numbers (where m is the number of bits ineach input)? As we done before, if you want to build for example a 2X1

MUX with 4-bit inputs, you have m MUXs (equal to thenumber of bits in the numbers) and you work on the bit

level. In this example if you have two inputs A, and B you want to

select either A or B and see it on the output which isY3Y2Y1Y0.

It is called quadruple MUX.


38/47


m-bit MUX II


39/47


m-bit MUX II

E is the enable line, and here it is active low,that is if E = 0 then the quadruple MUX

works, if E =1 the MUX is disabled and nooutput is available.

Remember that the basic block is a 2X1 MUX,that it selects between two inputs so it has

one selection line. Is S = 0 then the output = A, and if S = 1

then the output of the MUX = B.


40/47


Boolean Functions ImplementationUsing Multiplexers I

We have used a decoder with OR gate to implementBoolean functions.

Active high decoder contains all the minterms

represented by AND gates inside it. Have a deep look at the internal design of a MUX you

will find that a 2nX1 MUX is simply a nX2n decoderwith OR gate.

So, you can use a MUX to implement any Boolean

function since all the needed minterms are availablewithout the need to OR gate since it is already found. The only difference that now you apply the inputs of

the Boolean function to the selection lines of the MUXin the proper way.


41/47


Boolean Functions ImplementationUsing Multiplexers II

To implement a Boolean function with ninputs you have two options:

Either to use a 2nX1 MUX where you haven selection lines.

Or to use a 2n-1X1 MUX where you have n-

1 selection lines.


42/47


Boolean Functions ImplementationUsing Multiplexers III

General rules for implementing any Booleanfunction with n variables using 2nX1 MUX: Use a multiplexer with n selection lines and 2n

data inputs.

List the truth table of F.

Apply the n variables to the selection inputs ofmultiplexer with the same significance order.

For each data input (which is a minterm) place a 1if F has an output of 1 for this minterm and 0 if Fhas an output of 0 for this minterm.


43/47


Example

On board


44/47


Boolean Functions ImplementationUsing Multiplexers IV

General rules for implementing any Booleanfunction with n variables using 2n-1X1 MUX: Use a multiplexer with n-1 selection inputs and 2n-

1

data inputs List the truth table of F. Apply the first n-1 variables to the selection inputs

of multiplexer with the same significance order. For each combination of the selection variables

evaluate the output as a function of the lastvariable.

The function can be 0, 1 the variable or thecomplement of the variable.


45/47


Example I


46/47


Example II


47/47

Additional Notes

This lecture covers the followingmaterial from the textbook:

Chapter 4: Sections 4.9, 4.10 and 4.11

basics 0 review muxdec

Documents