basic processing unit
DESCRIPTION
TRANSCRIPT
Basic Processing Unit
V.SaranyaAP/CSE
Sri Vidya College of Engineering and Technology,
Virudhunagar
Objective
Execution of Instructions.Single Bus Organization of the Processor.Multiple Bus Organization of the Processors.
Some Fundamental Concepts
Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision-making).
Datapath: portion of the processor which contains hardware necessary to perform all operations required by the computer (the brawn).
Control: portion of the processor (also in hardware) which tells the data path what needs to be done (the brain).
InstructionFetch
InstructionDecode
OperandFetch
Execute
ResultStore
NextInstruction
Instruction execution cycle: fetch, decode, execute. Fetch: fetch next
instruction (using PC) from memory into IR.
Decode: decode the instruction.
Execute: execute instruction.
Fetch
Fetch: Fetch next instruction into IR (Instruction Register).Assume each word is 4 bytes and each
instruction is stored in a word, and that the memory is byte addressable.
PC (Program Counter) contains address of next instruction.
IR [[PC]]PC [PC] + 4
Single Bus Organization
Data line
Address line
PC
MAR
MDR
Y
Internal processor bus
Memory bus
Z
MUX
A
ALU
B
Constant 4
Select
AddSub
XOR
:ALU control lines
Carry-in
IR
RO
R(n–1)
::
TEMP
Instruction decoder and control logic
. . .
Control signals
Instruction Execution An instruction can be executed by performing one
or more of the following operations in some specified sequence: Transfer a word of data from one register to
another or to the ALU (Arithmetic Logic Unit). Perform an arithmetic or a logic operation and
store the result in a register. Fetch the contents of a given memory location
and load them into a register. Store a word of data from a register into a given
memory location.
Register Transfer Register to register transfer:
For each register Ri, two control signals:Riin used to load the data on the bus into the
register.Riout to place the register’s contents on the
bus. Example: To transfer contents of R1 to R4:
Set R1out to 1. This places contents of R1 on the bus.
Set R4in to 1. This loads data from the processor bus into R4.
Register Transfer (2)
Y
Internal processor bus
Z
MUX
A
ALU
B
Constant 4
Select
Ri
X
Ri in
X
Ri out
Y in
X
X
Z in
Z out
X
Arithmetic/Logic Operation
ALU: Performs arithmetic and logic operations on its A and B inputs.
To perform R3 [R1] + [R2]:1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
Y
Internal processor bus
Z
MUX
A
ALU
B
Constant 4
Select
Ri
X
Ri in
X
Ri out
Y in
X
X
Z in
Z out
X
Arithmetic/Logic Operation (2) If there are n operations, do we need n ALU
control lines? We could use encoding, which requires log2 n
control lines for n operations. However, this will increase complexity and hardware (additional decoder needed).
A
ALU
BAdd
Sub
XOR
:ALU control lines
Carry-in
Reading a Word from Memory Move R3, (R2) /* R2 [[R1]]
1. MAR [R2]2. Start a Read operation on the memory bus3. Wait for the MFC response from the memory4. Load MDR from the memory bus5. R3 [MDR]
MDR has four control signals: MDRin, MDRout, MDRinE and MDRoutE
Memory-bus data lines
MDR
X
MDR inE
X
MDR outE
Internal processor bus
X
MDR in
X
MDR out
Control Signals…R2out, MARin, Read.WMFCMDRout, R3in
MOVE R3, (R2)
Reading a Word from Memory (2) Move (R1), R2 /* R2 [[R1]] Sequence of control steps:
1. R1out, MARin, Read
2. R2out, MDRinE, WMFC
3. MDRout, R2in
WMFC: Wait for arrival of MFC (Memory-Function-Completed) signal.
MFC: To accommodate variability in response time, the processor waits until it receives an indication that the Read/Write operation has been completed. The addressed device sets MFC to 1 to indicate this.
Storing a Word in Memory
Move R2, (R1) /* [R1] [R2]Sequence of control steps:
1.R1out, MARin
2.R2out, MDRin, Write
3.MDRoutE, WMFC
4.R1in.
• MOVE (R2), R1.
• MAR [R2]• MDR [R1]
R2out, MARin,R1out, MDRin, WriteWMFCMDRout, R2in
Example 2
Executing a Complete Instruction Add (R3), R1 /* R1 [R1] + [[R3]] Adds the contents of a memory location pointed
to by R3 to register R1. Sequence of control steps:
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
Steps 1 – 3: Instruction fetch
Multiple-Bus Organization Single-bus structure: Control sequences are long as
only one data item can be transferred over the bus in a clock cycle.
Figure on next slide shows a three-bus structure. All registers are combined into a single block called
register file with three ports: 2 outputs allowing 2 registers to be accessed simultaneously and have their contents put on buses A and B, and 1 input allowing data on bus C to be loaded into a third register.
Buses A and B are used to transfer source operands to the A and B inputs of ALU, and result transferred to destination over bus C.
Multiple-Bus Organization (2)Bus C
Constant 4
Bus A Bus B
PC
Register file
MU
X
Incrementer
AALU
B
R
Address line
Memory bus data lines
Bus CBus A Bus B
MAR
MDR
IR
Instruction decoder
Processor: Datapath and Control
Multiple-Bus Organization (3)
For the ALU, R=A (or R=B) means that its A (or B) input is passed unmodified to bus C.
Add R4, R5, R6 /* R6 [R4] + [R5] Adds the contents of R4 and R5 to R6.
Sequence of control steps:1. PCout, R=B, MARin, Read, IncPC
2. WMFC3. MDRoutB, R=B, IRin
4. R4outA, R5outB, SelectA, Add, R6in, End