basic process diffusion

Diffusion Diffusion Process Process -- Basic Basic

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Front-End Technology & Manufacturing

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Diffusion Process - Basic

AMK Site Training

Purpose

Equips new Diffusion engineers (< 1 year in STM) with basic process knowledge in diffusion.

Equips non-diffusion dept experienced engineers with cross-functional knowledge.

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Objective

At the end of the course, participants should be able to:

Explain the concepts of diffusion, oxidation and RTP processes

Differentiate the differences among diffusion, oxidation and RTP processes.

Explain some common defects in Diffusion

List down some of the common metrology equipment used in Diffusion

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Table of ContentsTopic 1: Basic Thermal processes

Describe the thermal process overview

Topic 2: Thermal oxidationExplain thermal oxidation of silicon & oxide thickness range

Describe the growth mechanism of oxide

Describe the function & application of oxideExplain the factors affect oxidation growth rate

Describe furnace equipment and oxidation system

Topic 3: Thermal Diffusion Explain diffusion concepts

Understand thermal diffusion cycle

Explain two major steps of diffusion Describe the Laws of diffusion

Analyze the data curve on Solid solubility of impurity in silicon

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Table of Contents (Cont.)

Topic 4: POCL3 DepositionExplain N type doping & N type dopants

Describe the liquid source doping systemDescribe the solid source doping system

Topic 5: Boron DepositionExplain P type doping & P type dopantsDescribe the type of solid source boron process

Describe the solid source doping system

Topic 6: Rapid Thermal Processing (RTP)Understand the overview of RTP

Understand the RTP thermal cycle

Explain the RTP SystemDescribe the RTP application

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Topic 7: Common Diffusion DefectsOxidation Defects

POCL3 DefectsBoron Defects

Topic 8: Metrology Tool in DiffusionExplain the thermal process & quality parameters

Familiarize the film thickness measurement tool and concept

Understand the Surface Photo Voltage (SPV) tool and concept

Understand the capacitance voltage (C-V) measurement and conceptUnderstand sheet resistance and concept

Describe Spreading Resistance Probe

Analyze the SRP Profile

Table of Contents (Cont.)

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Course Agenda Outline

5BREAK

10Common Diffusion Defects7

15Rapid Thermal Processing 6

20- BREAK

20Metrology Tool in Diffusion8

10Pre-Quiz/ Ice Breaker

240 mins= 4 hrs

Total Time:

9

5

4

3

2

1

Topic

20Wrap-Up: Q&A, Evaluation, Post-Quiz

20Boron Deposition

20POCL3 Deposition

20Thermal Diffusion

60Thermal oxidation

20Basic Thermal Processes

Duration (mins)

Content

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Topic 1: Basic Thermal Processes

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Thermal Process Overview

Silicon wafer is subjected to heat treatment at elevated temperatures (350°C ~ 1260°C) under various types o f ambient and conditions.

This treatment is called Thermal process.

It is usually carried out in either the furnace (horizontal or vertical) with atmospheric or low pressure, or the Rapid Thermal Processor (RTP).

The ambient typically is Nitrogen, Oxygen, Hydrogen. Sometimes, it may add chlorine for specific purpose of metallic gettering process.

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Thermal Process Overview (Cont.)

Furnace / RTP

600 ~ 1200To repair lattice damage after the implant damage

Post Implant Anneal

RTP400 ~ 850A high temperature operation to allow silicon or polysilicon reacts with a metal to form a silicide compound (TiSi2). To reduce contact resistance@metal-Si interface.

Silicide

Furnace850 ~ 1100Doped oxide (PSG) is subjected to medium-high temperature process causes the glass to soften and flow to have a better conformal step coverage

Reflow / Glass Flow

Furnace400 ~ 1000Deposit a dielectric film (SiO2,Si3N4), PolySi film through low pressure

CVD – Poly, LTO, Nitride, TEOS, O-N-O

Furnace750 ~ 1100Convert liquid phase chemicals and deposit doped glass (P2O5) on silicon surface

Impurity Dopant Deposition

Furnace800 ~ 1250Drive in the dopants into silicon to form conductive diffused zone (N or P)

Diffusion

Furnace / RTP

750 ~ 1200Grow a layer of oxide film to protect underneath layers

Oxidation

ToolsOp. Temp °CObjectivesProcess

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Thermal Process Overview (Cont.)

Furnace900 ~ 1100Densify the dielectric oxide without changing its amorphous phase structures but increases the density of the film

Densification

Furnace600 ~ 1200A controlled modification of the silicon crystal to draw impurities to the bulk, or to the back surface of the wafer, so that immobilize impurities at locations away from the region of the active zone.

Gettering

ToolsOp. Temp °CObjectivesProcess

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Topic 2: Thermal Oxidation

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Thermal OxidationDefinition: Thermal Oxidation is defined as the formation of oxide on Silicon (SiO2) on a silicon surface.2 Main Type of Oxidation Process :

Dry OxidationSi (Solid) + O2(vapor) → SiO2 (Solid) Slow growth rate & controllable Very dense & clean Use for gate oxide in MOS device

Wet OxidationSi (Solid) + 2H2O(vapor) → SiO2 (Solid) + 2H2

faster growth rate less dense than dry oxide Use for field oxide or mask oxide

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Oxide Thickness Range (20 Åto 10,000Å)

MOS gate oxide 20-500Å

EPROM tunnel oxide 60-100Å

Sacrificial (screen) Oxide 100-400Å

Pad oxide 100-500Å

Masking oxide 2,000-5,000Å

Field oxide 3,000-10,000Å

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Growth MechanismOxygen (or steam) must come into direct contact with siliconAs oxide grows, the silicon is consumed (45%) of the final oxide thickness (Toxide).After initial oxide layer is formed, oxygen must diffuse throughthe layer to reach the silicon (reaction is slowed)

Silicon consumed

oxideTxSi consumed 45.0=

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Growth Mechanism (Cont.)

“Native Oxide”: First 0 - 20 Å

Nearly instantaneous growth from ambient

Inhibit oxidation of silicon

Linear Growth: 20 - 1000 Å ->Initial growth stage

Growth rate is relatively fast

Thickness, x = C1 x time(t)

C1 is a constant that is dependent

on temperature (Angstroms/min).

x (Å)

x α t

Time

Linear

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Growth Mechanism (Cont.)

Parabolic Growth: >1000 Å

Growth rate becomes slow

Thickness, x = C2 X √ time(t)

C2 is a constant that is dependent on temperature

Example: An wet oxidation process at 1000OC, has C2 =180 Angstroms/minute where C2 obtain from oxide data curve (Pg 27)

Growth for 90 minutes:

Thickness = (180 Å/min) X SQRT (90min) = 1707Å

Time

x (Å)

x α √t

Parabolic

Linear

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Function of Oxide

Device scratch protection

Device isolation e.g. Field oxide in MOS

Dielectric material (Electrical insulator) in the gate oxide (MOS) or memory cell structures

Impurity-mask barrier during doping or implant

Dielectric layer between metal conductor layers i.e.Capacitor

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Application of Oxide

Field oxide and Shallow Trench Isolation (STI) barrier oxide services as an isolation barrier between individual transistors to isolate them from each other.

Field Oxide in MOS

Substrate

Substrate

Shallow Trench Isolation (STI) in DRAM

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Application of Oxide (Cont.)

Gate oxide serves as a dielectric between the gate and source-drain parts of MOS transistor

Source Drain

Gate Gate Oxide

Substrate

Substrate

P-wellN-well

MOS Device

Twin well MOS Device

Gate OxideGate Oxide

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Oxide serves as masking material for depositing or implanting dopants into silicon.

Selective diffusion by dopants only happens on opening or unprotected areas.

Dopants have a slow rate of movement through oxide when compared to silicon.

Dopant

Substrate

BaseEmitter

Dopant Barrier Oxide

Dopant barrier spacer oxide

Implantation

SubstrateSource Drain

Spacer oxide protects narrow channel from high energy implant

Bipolar Junction Transistor

Screen oxide

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Pad oxide provides stress reduction (cushion) for nitride and silicon. In short, stress relief oxide.

Barrier oxide protects active devices and silicon from follow-on processing

SubstratePad Oxide

Nitride

MetalBarrier Oxide

Pad oxide

Passivation NitrideBonding Pad Metal

Barrier oxide

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A thin thermally grown implant screen oxide serves to reduce damage to the silicon surface and obtain better control over the depth that the dopant is implanted into silicon by reducing channeling effect.

Substrate

Thin Screen oxide

Ion implantation

(Without screen oxide) High damage to upper Si surface plus more channeling (Ion B)

(With screen oxide) Low damage to upper Si surface plus less channeling (Ion A)

Si atom

Channeling

Ion A

Ion B

Lattice imperfection

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Factors Affect Oxidation Growth Rate

Silicon Crystal Lattice Orientation i.e. <111> or <100>

Dopant Effects

Chlorine Dependence

Pressure Effects

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Oxidation Growth Rates: Crystal Orientation Effects

Silicon with crystal orientation of <111> will tend to oxidize faster than <100>The <111> silicon permits a greater number of atoms to be exposed to the diffusing oxygen molecules. Thus, an increase in oxidation rate is seen.Density surface atoms of Silicon:

<111> - 7.83 X 1014 cm-2

<100> - 6.78 X 1014 cm-2

Silicon surface

<111> Silicon

Oxygen

Silicon surface

<100> Silicon

Oxygen

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Oxide Growth Rate Data Curve

Oxide growth rate in silicon for DRY oxidation

<111> Si0.021um

<100> Si0.015um

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Oxide Growth Rate Data Curve (Cont.)

Oxide growth rate in silicon for wet oxidation

0.15um

0.021um

<111> Si0.03um

<100> Si0.018um

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Oxidation Growth Rates: Dopants Effect

Common dopants like Boron & phosphorous enhanced oxidation rate in silicon as shown below:

SiO2 in Phosphorous Doped Silicon SiO2 in Boron Doped Silicon

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Oxidation Growth Rates: Chlorine Effects

Oxidation rate of <100> silicon in chlorine ambient

Presence of chlorine in oxidation ambient increase oxidation growth on silicon. Note: C2H2Cl2 [DCE] + 2O2 → 2HCl + 2CO2

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Oxidation Growth Rates: Pressure Effects

Increase in pressure increase oxide growth (1atm=760 Torr)

Oxidationrate of <111> & <100> silicon in wet ambient

Thickness increase with

pressure

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Furnace Equipment Systems

Furnace system (horizontal or vertical) consists of a number of subsystems

Tube Quartz or silicon carbide

Wafer boats – quartz, silicon carbide

Heating elements – capable to heat up to 1300 °C

Thermocouples

Temperature controller for the dopants

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Furnace Equipment Horizontal System

Coil Heater

Si Wafers & Dopant sourceQuartz Tube

Zone 3Source

Zone 2Center

Zone 1Handle

Heating Element

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Furnace Equipment Horizontal System (Cont.)

Horizontal Furnace Loading Station

Tube Computer

Computer Console Station(MUX)

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Furnace Equipment System

Inlet process gases

Thermocouple

WafersQuartz Tube

Cantilever or paddle

Nitrogen gas inlet

Inner Atmoscan tube

Atmoscan Furnace

Horizontal Furnace

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Pyrogenic Oxidation Source Furnace

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Source Cabinet Horizontal Furnace

Gas Jungle & Bubb ler Controller

VAVLE

MFC

BUBBLER

Gas Filte

r

POCL3 25oC

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To Exhaust

Process gases

Thermocouples

Heating elements

Quartz wares

Vertical furnace system

Furnace Equipment (Vertical) System

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Pyrogenic Oxidation System

Carrier gas N2

O2

N2

H2

To vent

SF Heater

Heating ElementPyrogenic flameH2 + O2

FurnaceInlet gases,

H2, O2, N2, Cl2

Temperature control bath(20oC)

DCE (Chlorinated

agent, liquid)

Si + O2→ SiO2 Dry oxidation

Si + 2O2 + 4HCl → SiO2 + 2H2O + 2Cl2 Dry + Gettering

Si + 2H2O → SiO2 + 2H2 Wet oxidation

Si + 2H2O +2HCl → SiO2 + 3H2 + Cl2 Wet + Gettering

C2H2Cl2 [DCE] + 2O2→ 2HCl + 2CO2 DCE oxidation

Safety Ratio H2 : O2 <1.88

Chemical reaction for Oxidation System

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Topic 3: Thermal Diffusion

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Diffusion ConceptsMigration of a substance from a higher concentration to a lower concentration.Examples: perfume in air (gas state), ink in water (liquid

state)Diffusion is accelerated by putting energy (heat) into the system.

Ink in water (Liquid Diffusion) Perfume in Air (Gas Diffusion)

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Diffusion Concepts (Cont.)

A high temperature process whereby selected chemical dopants (N or P Type) which entered the silicon to change its electrical characteristics at desired location.

xj = 0

xj = Final Depth

N Dope Region

Silicon

xj

Diffusion Model

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Predeposition Thermal CyclePredeposition Time-temperature dependent chart

Boat in of wafersTemperature ramp up from standby@700oC to process temperature@900oCProcess timeRampdown of process temperature to standby temperatureBoat out of wafers

30min with O2

Process time

40 min

5oC/min

700oCBoat in

700oCBoat out

10oC/min

900oC

20 min

Ramp rate

lower temperature

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Drive in Thermal CycleDrive-in Time-temperature dependent chart@

Boat in of wafersTemperature ramp up from standby@700oC to process temperature@1000oC (High temperature)Process timeRamp down of process temperature to standby temperatureBoat out of wafers

Dry O2 30min +Wet 40min

Process time

60 min

5oC/min

700oCBoat in

700oCBoat out

1000oC

30 min

10oC/min

Higher temperature

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Two Step Diffusion

Two Major Steps in Diffusion:

Pre-Deposition : Dopants are deposited on the surface of the wafer

Drive-In : redistribution of dopants atoms introduced from the predeposition step to the desired depth in wafer.

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Laws of DiffusionFick’s 1st Law

When an impurity is dissolved in silicon and the impurity has a non-uniform concentration, the first law of diffusion describes that the impurity will tend to spread out until the concentration is reached its equilibrium state.

x

NDJ

∂∂−=

WhereJ is the flux density;D is diffusion coefficient;N is the impurity concentration.

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Laws of Diffusion (Cont.)

Fick’s 1st Law

x

NDJ

∂∂−= Impurity concentration

gradient

Diffusion Coefficient of impurity (N or P Type)

Negative Sign Decreasing concentration gradient

X1 X2J X2X1

It States that particle flow is proportional to the concentration gradient

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Laws of Diffusion (Cont.)

Diffusion Coefficient

Solid-state diffusion occurs as a result of the random motion of impurities in silicon and these are always thermally activated. The diffusion coefficient is therefore a very strong function of temperature, T and a relation of the form:

−=

Tk

QDD

B

exp0

WhereD0 is frequency factor;Q is the activation energy;kB is the Boltzmann

constant;8.62X10-5eV/KT is in degrees Kelvin.

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Solid Solubilities of Impurity Elements in Silicon

Solid solubility defines the maximum concentration of a dopant that can be absorb in a substrate at any specific temperature.

Example Common dopant:

Phosphorous = 1.3X1021

atoms/cc@1200 oC

Solid Solubility of impurities in Silicon data Cure

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Topic 4: POCL3 Deposition

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N Type Doping

POCL3(Phosphorous oxychloride) is N type impurity

N Type Doping is to introduce impurity(electrons) on the silicon to form collector and emitter in bipolar NPN transistor, and source/drain in NMOS.

Electrons are the primary current carrier.

NPN Transistor

Emitter (N type)

Collector (N type)

Base

Source (N type)

Drain (N type)

NMOS

Gate

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N Type Dopants

Furnace / Implanter

SolidDi-Antimony Tri-oxide, Sb2O3nAntimony, Sb

ImplanterLiquidTri-Methylantimony, Sb(CH3)3

ImplanterGasArsine, AsH3nArsenic, As

FurnacePlanarSolid Wafer SiP2O7

Furnace / Implanter

GasPhosphine, PH3

FurnaceLiquidPhosphorus Oxychloride, POCℓ3nPhosphorus, P

SystemSource Phase

SourceDopant type

Dopants

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POCL3 Doping

SiO2

Phosphorus diffused zone in Silicon

Diffusion

Masking oxideSilicon Wafer

Heat + Dopant

Phosphorus doped zone in Silicon

Predeposition

Phosphorus doped glass

Masking oxide

Phosphorus dope SiO2

Masking oxide

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Liquid Source Doping System

4POCl3 + 3O2→ 2P2O5 +6Cl2 Reaction

2P2O5 + 5Si → 5SiO2 + 4P Deposition

O2

N2

To vent

Heating Element

Furnace (Atm or LP)Inlet doping

gases

Temperature control bath(25oC)

Liquid source POCl3

Gaseous phase POCl3

Collaborated with Pyrogenic system

2H2O + 2Cl2→ 4HCl + O2 Recomposition

Si + 2H2O + 2HCl → SiO2 + 3H2 + Cl2

Oxidation + Gettering

Chemical reaction for POCL3

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Liquid Source Doping SystemAtmospheric Furnace

Cantilever – Low Rs range 1 to 4 Ω/sq Paddle – High Rs range 5 to 20 Ω/sq

Cantilever /Twin Rod Paddle

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Liquid Source Doping System LYDOP

LYDOP denotes Low Pressure Phosphorus Oxychloride Dop ing

Reduce low pressure give better doping uniformity with reduced maintenance compared to atmospheric doping process.

High Throughput 200 wafers per run

LYDOP System

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LYDOP Concept (Cont.)

Air molecules Gasmolecules

Longer mean free path of gas species

Low PressureAtmospheric Pressure

Gasmolecules

Note : Mean Free Path Distance Particle travel before collision

Start

End

Start

End

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Solid Source System

P2O5

Front Patterned wafer side

Wafer Back side

Solid sources, PH1000

Quartz Rack

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Solid Source Doping System

SiP2O7 + (Heat & N2) → P2O5 + SiO2 Activation

2P2O5 + 5Si → 5SiO2 + 4P Deposition

O2

N2

Furnace

Heater

Inlet doping gases

N2

H2

Chemical reaction for PH1000, SiP2O7

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Topic 5: Boron Deposition

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P-Type Doping

Boron Nitride(BN) is P type impurity

P Type Doping is to introduce impurity(holes) on the on the silicon to form isolation and base structure in bipolar NPN transistor, and source/drain in PMOS.

Holes are the primary current carrier.

Gate

Source (P type)

Drain (P type)

PMOS

Collector

Emitter

Base (P type)

NPN Transistor

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P Type Dopants

ImplanterSolidIndium Tri-chloride, InCℓ3pIndium, In

ImplanterSolidAluminum Oxide, Aℓ2O3pAluminum, Al

ImplanterGasBoron Tri-fluride, BF3

ImplanterGasDiborane, B2H6

FurnaceLiquidBoron Tribromide, BBr3

FurnacePlanarBoron Nitride, BNpBoron, B

SystemSource Phase

SourceDopant

typeDopants

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Planar Doping

SiO2

Silicon Wafer

Boron Glass

Boron doped zone in Silicon

Predeposition

SiO2

Boron diffused zone in SiliconDiffusion or Drive in

Heat + Dopant

Masking oxide

Masking oxide

Masking oxide

Boron dope SiO2

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Solid Source Boron Process

There are 2 type of Boron deposition process:

Dry process with O2

Wet process with H2O known as Hydrogen injectionprocess

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Solid Source System

B2O3

Front Patterned wafer side

Wafer Back side

Solid sources, BN975

Quartz Rack

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Solid Source Doping System

Dry Process

4BN + 3O2→ 2B2O3 + 2N2 Activation

3Si + 2B2O3→ 3SiO2 + 4B Deposition

Wet Process

B2O3 + H2O → 2HBO2 (Metaboric acid) H2 injection

2Si + 2HBO2→ 2SiO2 + 2B + H2 Deposition

O2

N2

Furnace

Heater

Inlet doping gases

N2

H2

Chemical reaction Boron Nitride

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Topic 6: Rapid Thermal Processing (RTP)

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Rapid Thermal Processing Overview

The RTP is a method of heating a single wafer to a temperature range of 400 to 1300 °C in a very short time.(eg. F ast ramprate@50oC/s)

The main advantages over a conventional furnace:

Reduced thermal budget

Minimized dopant movement in the silicon

Cleaner ambient because of the smaller chamber volume

Reduced contamination due to cold wall heating (wafer is heated chamber wall, ambient not heated)

Useful for ion implantation damage annealing (RTA).

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Rapid Thermal Processing Overview (Cont.)

The Disadvantages of RTP are :

Single-wafer processing

Rapid heating of wafer can result is warpage, slip defects & thermal stress

Relatively poor process uniformity

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RTP Thermal CycleRTP Time-temperature dependent chart

Wafer at standby room temperature@25oCLoad wafer to heating chamber with idle temperature@100oCFast ramp up rate from 25oC/sec to 75oC/secProcess time < 60secFast ramp down rate from 25oC/sec to 75oC/secUnload wafer to cooling station

1000oC

18 sec 18 sec

30 sec

50oC/sec

Fast Ramp rate

Idle temp=100oC 100oC

50oC/sec

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RTP System

The hardware used for RTP is typically a single wafer chamber equipped with a radiant heat source.

The heat source is an IR radiator at wavelengths that are efficiently absorbed by the silicon wafer. This allows very rapid and uniform heating.

Temperature is controlled using an optical pyrometer in a closed loop control system.

Tungsten Halogen Lamps (Crosswise)

Tungsten Halogen Lamps (Lengthwise)

Pyrometers

Slip-Free Ring

Ceramic Shield

Wafer

Thermocouple

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Chamber of RTP System

Wafer chuck

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RTP ApplicationTemperature, °C

1200

1000

800

600

400

200

Process Time

NiSi formation / anneal

CoSi formation

Cu anneal

High-k annealCoSi annealTiSi formation

Barrier metal annealTiSi anneal

BPSG / PSG densification

Implant anneal

Ultrashallow Junction (USJ) formation

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RTP Application (Cont.)

Titanium Silicide (TiSi2) Formation :

Silicides are used to reduce contact resistance at metal-silicon interface.

TiSi2 becoming an issue for ultrashallow junctions.

Current technology is Cobalt Silicide forms at lower temperatures with comparable resistance.

Future technologies (sub-100nm) with even shallower

junctions are considering Nickel Silicide.

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Topic 7: Common Diffusion Defects

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Type of DefectsOxidation Defects

OISF Oxide Induced Stacking Faults

ESF Epitaxial Stacking faults

Oxide Induced charges

POCL3 Defects

POCL3 stain

Boron Defects

Boron skin

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Oxide Defects in Diffusion

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Oxide Induced Stacking Faults

Stacking faults are frequently generated in the surface region of silicon wafer during thermal oxidation process at a typical temperature range between 900 and 1200 °C. These fa ults are commonly called oxidation-induced stacking faults (OSF or OISF).

Degrade the performance and affect the reliability of semiconductor devices.

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OSFs are predominantly nucleated at certain mechanical damages on the wafer surface; they include contamination with Na or metallic impurities, and surface pitted by HF acid. Moreover, oxygen precipitates can also be nucleated sites for OSF.

OSFs are caused by Fe metallic contaminations on p-type dopant diffusion zone

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Stacking faults are also observed in silicon epitaxialfilms grown on silicon substrates. They differ from OSFs both in structure and in the mechanisms of formation. These faults nucleate dominantly at the interface ions on the surface or in the substrate region, and grow into the epitaxial film.

Epitaxy Stacking Fault grown on <111> surface

Epitaxial Layer

Stacking fault

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Oxidation Induced Defects

trapoxidemobilefixedtraperfaceTotal QQQQQ +++= int

Impurities & broken bonds(Si-O)

Oxide layerOxide Trapped

Qot

Wafer handling

Photoresist, developer

Furnace cleanliness

Origin at the gate /SiO2 interface and enter oxide layer

Mobile

Qm

Oxidising ambient (H2O or O2)

Furnace Rampdown rate

30Å to 50Å of the silicon interface

Fixed

Qf

Silicon orientation <111> or <100>

Oxidation temperature

Silicon-silicon oxide interfaceInterface Trapped Qit

CauseOrigin in siliconOxide Charge

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MOS Structure

Semiconductor

Oxide

Metal

Oxide trapped charge(Qot)Mobile chargeQm

Na+

Interface trapped charge (Qit)

Fixed charge (Qf)

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POCL3 Defects in Diffusion

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POCLPOCLPOCLPOCL3333 DefectDefectDefectDefectName of Defect : POCL3 STAIN

Good wafer Bad wafer

Cause

Reaction of the POCL3 and moisture will result in phosphoric acid and small amount of Hydrochloric acid which attack the silicon.

If the tube and boat is highly dopedAutodoping (atoms that outgas from tube or boat and then redope into process ambient and wafer)

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AMK Site Training

Boron Defects in Diffusion

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AMK Site Training

Boron DefectName of Defect: Boron Stacking Fault

CauseWhen B2O3 reacts with silicon, it forms a glassy structure with silicon. During diffusion, the rate of expansion on the doped Sisurface is different with that of pure Si structure, hence causing dislocations on the wafer. The dislocation propagates with temperature and forms stacking faults.

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AMK Site Training

Boron Defect (Cont.)

Name of Defect : Boron Skin

Cause:

Water vapour on the B2O3 layer of the wafer surface.

The water vapour will react with hot boron glass (B2O3) to form metaboric acid.

H2O + B2O3 2 HBO2

The metaboric acid will etch into the wafer on temperature above 400 oC.

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AMK Site Training

Topic 8: Metrology Tool in Diffusion

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AMK Site Training

Metrology Tools

Common Diffusion Process Parameters

Films thickness – Ellipsometer, Optiprobe, UV1280

Doped sheet resistivity – Four-point probe, Rs machine

Doping concentration profileSpreading Resistance Probe

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AMK Site Training

Metrology Tools (Cont.)

Quality parameters for contamination control

Defectivity Inspection ScopesWafer Defects control

Surface Photo-Voltage (SPV) MeasurementIroncontamination control

Capacitance – Voltage (C-V) techniquesMobile ion contamination control

TXRF(Total X Ray Fluorescence) Determine concentration of heavier element eg. Nickel on SPV wafer substrate

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AMK Site Training

Film Thickness Measurement Tool

Opti probe and UV machine are capable to measure oxide, silicon nitride, Poly on oxide, oxide on Poly and oxide-nitride-oxide (ONO)

Optiprobe

UV machine

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AMK Site Training

Film Thickness PrincipleA non-destructive, non-contact to measure thin and transparent film (e.g. silicon oxide)Wafer is optically scanned by a laser

Ellipsometer Principle Oxide Thickness

1

46.1sin

sin

,Re

)(2

==

=

air

idealSiO

Indexfractive

ηη

θιθη

η

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AMK Site Training

Surface Photo Voltage(SPV) Measurement Tool

Function: To detect heavy metals (e.g. Fe, Copper, Cobalt, Nickel) found in wafers.SPV machine and the concentration of Fe dissolved in the silicon

SPV wafer

SPV Machine SPV wafer Map

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AMK Site Training

SPV Measurement PrincipleSPV is the change of the electrostatic potential at the wafer surface caused by illumination.Diffusion Length, (L) average distance an excess minority carrier travels before recombination. It is a measure of imperfection insilicon (e.g. metal contamination, oxygen induce defects)

Ec

EF

Ev

e- e- e- e-

Band to BandRecombination

Ec

EF

Ev

e- e- e- e-

Cr Ox PptFeDefect State

Recombination

Very Pure Silicon:Band to Band Recombination

- Long Lifetime

Silicon with Impurity/Defects:Recombination through Defect States

- Kills Lifetime

Photon flux

Chopper

SPV electrode

dV

Chuck

Silicon wafer

Lock- in amp

P type substrate

P type substrate

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AMK Site Training

SPV Measurement Principle (cont.)

[

L2

L1

Diffusion Length Measurement

Optical Activation(FeB Pair Dissociation)

Calculation

Diffusion Length Measurement

Fe ] cm-3 =1.05××××1016 L2-2 - L1

-2

Universal constant

Calculation

Fe-B pairing occurs at room temperature (Iron mobile at room temp)Measure L1

The Fe-B Pair is a weak recombination center - little effect on lifetime

Fe-B Pairs can be dissociated by exposure to bright light

Fe is an efficient recombination center -significantly reduces lifetimeMeasure L2

Determine Iron calculation, Fe

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AMK Site Training

Capacitance Voltage(C-V) Measurement

Conventional method of C-V Metal-Oxide-Semiconductor structure

Bias voltage from -5V to 5V and record capacitance

CV Test Setup

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AMK Site Training

Capacitance Voltage(C-V) Measurement (cont.)

Bias Voltage

CV Plot for n-type silicon

Ca

paci

tanc

e

C max

C min

-5 +50

Ideal curve

Q = C V

Qm = C.∆V

where Q = Qm mobile charge

∆V=Voltage shiftReal

curve∆V

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AMK Site Training

Capacitance Voltage(C-V) Measurement (Cont.)

Non-contact C-V measurement techniqueCOCOS Metrology (Corona-Oxide-Characterization-Of-Semiconductor)

Corona pulsing gun controls charge deposition (positive or negative)Fast and precise vibrating probe provides non-contact voltage transient measurement

Q = C V

C = ∆Q/∆V

Corona charge

Measured with non-contact probe

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AMK Site Training

Sheet ResistanceThe four-point probe technique is one of the most common methods for measuring semiconductor resistivity.

A known value of current (I) is passed between the two outer probes, and the potential difference (V) developed across the inner probes is measured.

4 point probe Automatic 4 point

probe system

53.4..

....

tanRe

'

=

==

=

FactorCorrectionisFCwhereI

VxFCRxFCRs

cesisSheetI

VR

LawsOhm

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AMK Site Training

Spreading Resistance Probe

The spreading resistance probe (SRP) is used to measure both dopant concentration depth profiles and resistivity. It is capable of profiling very shallow p-n junction depths.The SRP probe has two carefully aligned probes that are moved in steps along a beveled wafer surface, with the resistance betweenthe probes measured at each step.As the probes pass through the junction, the probes sense the change in conductivity type (n or p).The sample must be carefully prepared with a bevel angle, usually 0.5°~ 5°, which makes the SRP a destructive test.

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AMK Site Training

Spreading Resistance Probe (Cont.)

The SRP measurement method is characterized as:

specially prepared probes and the apparatus to raise, lower and step the probes;

low applied voltages during the measurement;

δZ (depth) = δl Sinθ

θ

Substrate

II

V ~ 5 mV = fixed voltage

δl

Silicon sample with doped profile

Beveled surface

xj

xj

NP

P substrate Concentration

P-N Junction

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AMK Site Training

SRP Profile

Epitaxy n-doped concentration

Boron doped

Arsenic doped

Si – SiO2interface

Diffusion Junction

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AMK Site Training

1

2 43

5

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AMK Site Training

~~~~THANKYOU~~~~

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AMK Site Training

ReferencesSilicon Wafer Manufacturing (Gilles Thomas, ST)AMK5 Cross-Functional Training Material, Diffusion (AMK5 Diffusion)Silicon Processing for the VLSI Era Volume 1 (S.Wolf & R.N. Tauber)Basic Process Technology (STMicroelectronics)Advance Semiconductor Handbook (Integrated circuit engineering cooperation)Technical article on Role of chlorine in silicon oxidation (J. Monkowski)

basic process diffusion

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