basic concepts and architectures

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CMOS SigmaCMOS Sigma--Delta Converters Delta Converters ––From Basics to StateFrom Basics to State--ofof--thethe--ArtArt

Basic Concepts and ArchitecturesBasic Concepts and ArchitecturesAngelAngel RodríguezRodríguez--VázquezVázquez

Basic Concepts and ArchitecturesBasic Concepts and ArchitecturesAngel Angel RodríguezRodríguez--VázquezVázquez

l@[email protected]

Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and Angel Rodríguez-Vázquez

Barcelona, 29-30 / Septiembre / 2010

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OUTLINEOUTLINE1. Introduction1. Introduction

2. Fundamentals of 2. Fundamentals of ADCsADCs OversamplingOversampling

Quantization noise shapingQuantization noise shaping

Basic architectureBasic architecture

Cl ifi ti fCl ifi ti f ADCADC

3. Discrete3. Discrete--Time Time ModulatorsModulators Classification of Classification of ADCsADCs

Si lSi l bit i lbit i l titi hit thit t SingleSingle--bit singlebit single--quantizerquantizer architecturesarchitectures

Dual quantizationDual quantization

MultiMulti--bit quantizationbit quantization MultiMulti bit quantizationbit quantization

BandpassBandpass modulatorsmodulators

4. Continuous4. Continuous--Time Time ModulatorsModulators

Basic concepts and topologiesBasic concepts and topologies

Synthesis methodsSynthesis methods

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Introduction: Introduction: Basic ADC ProcessBasic ADC Process

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Introduction: Introduction: QuantizationQuantization

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OversamplingIntroduction: Introduction: SamplingSampling

p g

Classification of ADCs

Nyquist-rate ADCs (M~1)

Oversampling ADCs (M>>1)

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Introduction: Introduction: Taxonomy of ADCsTaxonomy of ADCs

Sampling process

Limits the input signalLimits the input signal frequency

Speed of the ADC Speed of the ADC

Quantization process

Limits the input signal accuracy

Resolution of the ADC

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Introduction: Introduction: Taxonomy of ADCsTaxonomy of ADCs

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Introduction: Introduction: About ADC taxonomyAbout ADC taxonomy

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Introduction: Introduction: Resolution vs. conversion rateResolution vs. conversion rateCMOS ADCsCMOS ADCs

ADCsADCs

NyquistNyquist ADCsADCs

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Introduction: Introduction: Quantization errorQuantization error Quantization output-input characteristicQ p p

Quantization error White noise model

- If x varies randomly from sample to sampley p p

- If the # of quantizer levels is high

[Enge99]

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Introduction: Introduction: Quantization error noise modelQuantization error noise model

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PSD of oversampled quantization noise

Fundamentals of Fundamentals of ADCs: ADCs: OversamplingOversampling

PSD of oversampled quantization noise

In-Band Noise power (IBN or PQ)

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Fundamentals of Fundamentals of ADCs: ADCs: OversamplingOversampling

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Fundamentals of Fundamentals of ADCs: ADCs: Performance metricsPerformance metrics

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Fundamentals of SD ADCs: Fundamentals of SD ADCs: Quantization noise shapingQuantization noise shaping Processing of the quantization error

I b d i d ff ti l ti In-band noise power and effective resolution

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Fundamentals of Fundamentals of ADCs: ADCs: Basic Basic ADC architectureADC architecture

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Fundamentals of Fundamentals of ADCs: ADCs: NyquistNyquist--rate vs. rate vs. ADCsADCs

NyquistNyquistADCADC

SiSi D ltD ltSigmaSigma--DeltaDeltaADCADC

HIGHHIGH--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasingaliasing

LOWLOW--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasing (1st/2nd order)aliasing (1st/2nd order)for antifor anti--aliasingaliasing

Overall resolution obtained using Overall resolution obtained using HIGHHIGH--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

for antifor anti--aliasing (1st/2nd order)aliasing (1st/2nd order)

High overall resolution obtained using High overall resolution obtained using LOW/MODERATELOW/MODERATE--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

HIGHHIGH--SELECTIVITY DIGITAL FILTERSELECTIVITY DIGITAL FILTER

EASIER AND MORE ROBUST IN MODERN CMOSEASIER AND MORE ROBUST IN MODERN CMOS

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H(z) with large gain

Fundamentals of Fundamentals of ADCs: ADCs: Basic Basic M architectureM architecture

within the signal band

1st1st--order order MML L thth--order order MM

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H(z) with large gain

Fundamentals of Fundamentals of ADCs: ADCs: Basic Basic M architectureM architecture

within the signal band

1st1st--order order MML L thth--order order MM

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Fundamentals of Fundamentals of ADCs: ADCs: Classification of Classification of MsMs Nature of the signals being handled: Low-pass vs. Band-pass

Low-Pass M Band-Pass M

Dynamics of the loop filter: Discrete-Time vs. Continuous-Time

DT M CT M

Number of bits of the embedded quantizer: single bit vs multi bit Number of bits of the embedded quantizer: single-bit vs. multi-bit Number of quantizers employed: single-loop, cascade, etc.. Type of primitives available in the fabrication technology…

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H(z) with large gainL BFundamentals of Fundamentals of ADCs: ADCs: Basic control parametersBasic control parameters

within the signal bandL

L L thth--order order MM

Oversampling, Oversampling, OSROSR

Order of the shaping, Order of the shaping, LL

Speed of analog circuitry Speed of analog circuitry

Resolution of the Resolution of the internal quantizer, internal quantizer, BB

Stability of the Stability of the M M

Linearity of the DACLinearity of the DACLinearity of the DAC Linearity of the DAC

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H(z) with large gainL BFundamentals of Fundamentals of ADCs: ADCs: Basic control parametersBasic control parameters

within the signal bandL


Oversampling, Oversampling, OSROSR

Order of the shaping, Order of the shaping, LL

Speed of analog circuitry Speed of analog circuitry

Resolution of the Resolution of the internal quantizer, internal quantizer, BB

Stability of the Stability of the M M

Linearity of the DACLinearity of the DACLinearity of the DAC Linearity of the DAC

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DTDT-- Ms: Ms: 1st1st--order LP order LP modulatormodulator

Using a linear model for the quantizer

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DTDT-- Ms: Ms: 1st1st--order LP order LP ModulatorModulator

Ramp input & 1-bit quantizer

Sinewave input & 3 bit quantizerSinewave input & 3-bit quantizer

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Noise pattern

DTDT-- Ms: Ms: 1st1st--order LP order LP modulatormodulator

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DTDT-- Ms: Ms: 2nd2nd--order LP order LP modulatormodulator

1st-order Modulator

2nd-order Modulator

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DTDT-- Ms: Ms: 2nd2nd--order LP order LP modulatormodulator

Linear analysis

Output spectrum and noise pattern

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2nd2nd--order order MM

DTDT-- Ms: Ms: HighHigh--order singleorder single--loop loop modulatorsmodulators

Stable for inputs inif

[Candy85]


purepure--differentiator FIRdifferentiator FIR NTFNTFProne to instabilityProne to instability

High-order loops areonly conditionally stable [OptE90]only conditionally stable [ p ]

IIRIIR NTFNTFss [Lee87]

Zeros at Zeros at zz = 1= 1 Butterworth/Chebyshev polesButterworth/Chebyshev poles

(1)(1)(1)(1)

Gain adjusted to satisfy

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OPTIMIZED IIROPTIMIZED IIR NTFNTFss [Schr93]

(2)(2)

5th5th--order NTForder NTF((OSR OSR = 64)= 64)

Complex zeros at |Complex zeros at |z z | = 1 with optimal | = 1 with optimal positions within the signal bandpositions within the signal band

Butterworth/Chebyshev polesButterworth/Chebyshev poles

IIRIIR NTFNTFss [Lee87]

(2)(2)(1)(1)

Zeros at Zeros at zz = 1= 1 Butterworth/Chebyshev polesButterworth/Chebyshev poles

(1)(1)

Gain adjusted to satisfy

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Di t ib t d f db k dDi t ib t d f db k d


Distributed feedback andDistributed feedback anddistributed feedforward inputdistributed feedforward input

(1)(1)

(2)(2) Feedforward summationFeedforward summation+ local resonators+ local resonators Complexity (many feedback/feedforward coeffs)Complexity (many feedback/feedforward coeffs)

Large spread of coeffs (area power)Large spread of coeffs (area power) Large spread of coeffs (area, power)Large spread of coeffs (area, power) Not suited at low oversampling (standNot suited at low oversampling (stand--alone)alone)

(2)(2)

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Error Cancellation Logic (ECL)Error Cancellation Logic (ECL)

DTDT-- Ms: Ms: HighHigh--order cascade order cascade modulatorsmodulators

HIGHHIGH--ORDER STABLE OPERATIONORDER STABLE OPERATION is ensured by cascading low-order stages (Li = 1, 2).

d > 1, interstagecoupling

by cascading low order stages (Li 1, 2).

Relationships among ECL and M to be fulfilled for perfect cancellation (NOISE LEAKAGENOISE LEAKAGE).

coupling

Systematic loss of resolution, but:

MASH MASH MsMs

Smaller than for single loops Independent of OSR

Each stage re-modulates a signal containing the quantization error in the previous one.

Digital processing is used to cancel out all quantization errors but that in the last stage

Performance close to idealPerformance close to ideal

Small spread of analog coeffsSmall spread of analog coeffs ECL can be easily implementedECL can be easily implemented

quantization errors, but that in the last stage. Suited at low oversamplingSuited at low oversampling

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DTDT-- Ms: Ms: HighHigh--order cascade order cascade modulatorsmodulators

11--11--1 1 MM [Mats87]

22--2 2 MM [Kare90]

22--1 1 MM [Longo88] 22--22--1 1 MM [Vleu01]

Noise leakage precludes the cascading of4th4th--order 2order 2--stage cascadestage cascade 22--11--11--1 1 MM [Rio00]

22--22--2 2 MM [Dedic94]

Noise leakage precludes the cascading ofa large number of stages to be practical

4th4th--order 3order 3--stage cascadestage cascade22--11--1 1 MM [Yin94]

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DTDT-- Ms: Ms: MultiMulti--bit bit modulatorsmodulators

Increased dynamic rangeIncreased dynamic rangeB can trade for OSR (wideband)

Better stability propertiesBetter stability properties

DAC nonDAC non--linearities are directly linearities are directly added to the inputadded to the input

More aggressive high-order NTFs

FULLFULL--PARALLEL ADC/DACPARALLEL ADC/DAC(Typically B < 6)

DAC linearity limited byDAC linearity limited bycomponent mismatchcomponent mismatchadded to the inputadded to the input

The linearity of the M will beno better than that

( yp y ) pp

POSSIBLE APPROACHESPOSSIBLE APPROACHES

Element TrimmingElement Trimming Analog CalibrationAnalog Calibration

Correcting DAC errorsCorrecting DAC errors

DEM techniquesDEM techniques

Decorrelating DAC errorsDecorrelating DAC errorsfrom the inputfrom the input

Dual quantizationDual quantization

Introducing DAC errorsIntroducing DAC errorsat a nonat a non--critical positioncritical position

Digital CorrectionDigital Correction

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ELEMENT SELECTIONELEMENT SELECTION

DTDT-- Ms: Ms: MultiMulti--bit bit modulatorsmodulators

ELEMENT SELECTIONELEMENT SELECTIONLOGICLOGIC

Increased dynamic rangeIncreased dynamic rangeB can trade for OSR (wideband)

Better stability propertiesBetter stability properties

DAC nonDAC non--linearities are directly linearities are directly

( )

More aggressive high-order NTFs

FULLFULL--PARALLEL ADC/DACPARALLEL ADC/DAC(T pi ll B < 6)

DAC linearity limited byDAC linearity limited byomponent mi m t homponent mi m t hadded to the inputadded to the input

The linearity of the M will beno better than that

(Typically B < 6) component mismatchcomponent mismatch

Elements selected to make DAC errors independent of the input signal

Dynamic Element Matching (DEM)Dynamic Element Matching (DEM)

Elements selected to make DAC errors independent of the input signal

Algorithms that try to average the error in each DAC level to zero (to push DAC errors to high freq.)

Randomization: Distortion transforms into white noise Rotation: Distortion moves out of band (CLA) Mismatch-shaping: 1st/2nd order (ILA, DWA, DDS)

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DTDT-- Ms: Ms: DualDual--quantization quantization modulatorsmodulators

Combines 1-bit and multi-bit quantizers (linearity/reduced error)

Dual QuantizationDual Quantization

LeslieLeslie--SinghSinghLeslieLeslie SinghSingharchitecturearchitecture

[Lesl90]Concept applied to singleConcept applied to single--loop loop MsMs [Hair91]

L-0 cascade M

Improved stability Noise leakage L 0 cascade M

Suffers from noise leakage Multi-bit quantization does

not improve stability

Concept applied to cascadeConcept applied to cascade MsMs [Bran91]Concept applied to cascade Concept applied to cascade MsMs [Bran91]

Multi-bit quantization usually applied only in the last stage

DAC errors shaped by L-LNRelaxes DAC requirements

Noise leakage (inherent to cascades)

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DTDT-- Ms: Ms: BandpassBandpass modulators modulators –– IF digitizationIF digitization

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DTDT-- Ms: Ms: BandpassBandpass modulators modulators

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DTDT-- Ms: Ms: BandpassBandpass modulators modulators

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DTDT-- Ms: Ms: BandpassBandpass Ms Ms –– Signal band location Signal band location

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DTDT-- Ms: Ms: LPLP--toto--BP transformation method BP transformation method

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DTDT-- Ms: Ms: BandpassBandpass SD Modulators SD Modulators

Other BP M architectures Other BP-M architectures

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DTDT-- Ms: Ms: ADCs ADCs -- DecimationDecimation

Bandpass decimation Bandpass decimation

Effi i t d i ti Efficient decimation

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CTCT-- Ms: Ms: Basic conceptsBasic concepts

Discrete-Time Ms

DT loop filter All internal signals are DT Sampling at the input

Continuous-Time Ms

CT f t (l filt ) t CT front (loop filter) part DT back (quantizer) part Sampling inside the loop

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AA Filter

Pros of CT-Ms

Implicit anti-aliasing filterImplicit anti aliasing filter Less impact of sampling errors No input switches – potentially better for low-voltage supply No “settling” error at the loop filter circuitry P t ti ll l ti d ith l ti Potentially larger operation speed with less power consumption No sampling of the noise at the input capacitors Reduced digital noise coupling

Counters of CT-Ms Counters of CT Ms

Very involved dynamic due to the combination of non-linearity, CT and DT

larger impact of circuit non linearities larger impact of circuit non-linearities Time constant tuning is needed for correct loop filtering Large sensitive to time uncertainty (“jitter”)

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Linear analysis of CT-Ms assuming [Bree01]:


Linear analysis of CT Ms, assuming [Bree01]:

Linear model for the quantizer DAC gain is unity in the signal bandwidth

Example: Lth-order, B-bit single-loop architecture

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C h i h d l i i f i (f d i )

CTCT-- Ms: Ms: Synthesis methodsSynthesis methods

DT-to-CT synthesis method: pulse invariant transformation (freq. domain)

Find an equivalent DT M that fulfils the required specifications Based on a DT-to-CT equivalence [Cher00]

Open-loop configuration

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DT-to-CT synthesis method: State-Space Representation (time domain)


DT-to-CT synthesis method: State-Space Representation (time domain) Operation of the loop filter is described by state-space equations Can be applied to an arbitrary feedback DAC waveform [Olia03b]

Equivalent DT system

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Application of DT-to-CT method to cascade CT Ms

Every state variable and DAC output must be connected to the integrator input of theulterior stages in the cascade [Ortm01]

Increases the number of analog components (transconductors and amplifiers) Increases the number of analog components (transconductors and amplifiers)

DT-to-CT

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Direct synthesis method [Bree01]


ec sy es s e od [ ee0 ] Uses the desired NTF as a starting point, (as for the DT case) An Inverse Chevychev distribution of the NTF zeros has advantages in terms of SNR

and stability A li ti t d hit t [T t06] Application to cascade architectures [Tort06]

Optimum placement of poles/zeroes of the NTF Synthesis of both analog and digital part of the cascade CT Modulator Reduced number number of analog components Reduced number number of analog components

DT-to-CT

MethodDirect

Method

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Direct synthesis of cascade architectures (I) [Tort06]


Direct synthesis of cascade architectures (I) [Tort06]

Sensitivity to mismatch (gm,C) A 2-1-1 example

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A 2-1-1 example

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16

18

oss

(dB

)

10

12

14

10

12

SN

R L

o

6

8

1 1.5

2 2.5

0 0.20.40.60.81

8

c(%)gm(%)1

1.5

2

2.5

0 0.20.40.60.81

4

c(%)gm(%)

c

DT-to-CT synthesis method Direct synthesis method

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Direct synthesis of cascade architectures (II) [Tort06]


Direct synthesis of cascade architectures (II) [Tort06]

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A case study: A 12 bit@20MHz 4 b 2 1 1 CT M for VDSL [Tort06]


A case study: A 12-bit@20MHz, 4-b, 2-1-1 CT M for VDSL [Tort06]ho

dth

esis

met

Dire

ct s

ynt

D

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[B 01] L B d J H H ij i C ti Ti Si D lt M d l ti f A/D C i i R di

General ReferencesGeneral References

[Bree01] L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in RadioReceivers. Kluwer Academic Publishers, 2001.

[Cherr00] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/DConversion. Kluwer Academic Publishers, 2000.

[Enge99] J V Engelen and R van de Plassche BandPass Sigma-Delta Modulators: Stability Analysis[Enge99] J.V. Engelen and R. van de Plassche, BandPass Sigma-Delta Modulators: Stability Analysis,Performance and Design Aspects. Kluwer Academic Publishers, 1999.

[Geer02] Y. Geerts, M. Steyaert and W. Sansen: “Design of Multi-bit Delta-Sigma A/D Converters”. Kluwer, 2002.

[Mede99] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Kluwer Academic Publishers, 1999.

[Nors97] S.R. Norsworthy, R. Schreier, and G.C. Temes (Editors), Delta-Sigma Data Converters: Theory, Design andSimulation. IEEE Press, New York 1997.

[Pelu99] V. Peluso, M. Steyaert, and W. Sansen, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/DConverters. Kluwer Academic Publishers, 1999.

[Rabi99] S. Rabii and B.A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. KluwerAcademic Publishers, 1999.

[Rio06] R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez, CMOS CascadeSigma- Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer,20062006.

[Rodr03] A. Rodríguez-Vázquez, F. Medeiro and E. Janssens, CMOS Telecom Data Converters. KluwerAcademic Publishers, 2003.

[Rosa02] J.M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips. Kluwer AcademicPublishers, 2002.

[Shoa95] O. Shoaei, Continuous-Time Delta-Sigma A/D Converters for High Speed Applications. Ph.D.Dissertation, Carleton University, 1995.

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