basic adders and counters implementation of adders in fpgas ece 645: lecture 3

Basic Adders and Counters

Implementation of Adders in FPGAs

ECE 645: Lecture 3

Required Reading

Chapter 5, Basic Addition and Counting, Sections 5.1-5.5, pp. 75-85.

Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

Required Reading

Chapter 9, Using Carry and Arithmetic Logic

Spartan-3 Generation FPGA User Guide http://www.xilinx.com/support/documentation/spartan-3_user_guides.htm

Half-adder

x

y

c

sHA

x + y = ( c s )2

2 1

x y c s0011

0101

0001

0110

Half-adderAlternative implementations (1)

s = xy + xy

b)

a)

s = x y

c = xy

c = x + y

c)c = xy

s = xc + yc = xc yc

Half-adderAlternative implementations (2)

Full-adder

xy

cout

sFA

x + y + cin = ( cout s )2

2 1

x y cout s

00001111

00110011

00010111

01101001

cin

01010101

cin

Full-adderAlternative implementations (1)

a) s = (x y) cin

cout = xy + cin (x y)

s

c

c


s = x y cin = xycin + xycin + xycin + xycin

cout = xy + xcin + ycinb)


c)

x y cout s0011

0101

0

1

cin

cin

cin

cin

cin

cin

x

yA2

A1

XORD

0 1

Cin

Cout

S

p

g


Implementation used to generate fast carry logic in Xilinx FPGAs

x y cout

0011

0101

y

y

cin

cin

p = x yg = ys= p cin = x y cin

Latency of a k-bit ripple-carry adder

Tripple-add = TFA(x,ycout) + + (k-2) TFA(cincout) + + TFA(cin s)

Latency k TFA

Latency k

Overflow for signed numbers (1)

Indication of overflow

Positive+ Positive= Negative

Negative+ Negative= Positive

Formulas

Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1 =

= ck ck-1

Overflow for signed numbers (2)

xk-1 yk-1 ck-1 ck sk-1 overflow ckck-1

00001111

00110011

01010101

00010111

01101001

01000010

01000010

Implementation of Adders in FPGAs

Technology Low-cost High-performance

120/150 nm Virtex 2, 2 Pro

90 nm Spartan 3 Virtex 4

65 nm Virtex 5

45 nm Spartan 6

40 nm Virtex 6

Xilinx FPGA Devices

Altera FPGA Devices

Technology Low-cost Mid-range High-performanc

e130 nm Cyclone Stratix

90 nm Cyclone II Stratix II

65 nm Cyclone III Arria I Stratix III

40 nm Cyclone IV Arria II Stratix IV

23ECE 448 – FPGA and ASIC Design with VHDL

Programmableinterconnect

Programmablelogic blocks

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

General structure of an FPGA


CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Xilinx Spartan 3 FPGAs


CLB Structure


CLB Slice Structure

• Each slice contains two sets of the following:• Four-input LUT

• Any 4-input logic function,• or 16-bit x 1 sync RAM (SLICEM only)• or 16-bit shift register (SLICEM only)

• Carry & Control• Fast arithmetic logic• Multiplier logic• Multiplexer logic

• Storage element• Latch or flip-flop• Set and reset• True or inverted inputs• Sync. or async. control


LUT (Look-Up Table) Functionality

• Look-Up tables are primary elements for logic implementation

• Each LUT can implement any function of 4 inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000


COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-UpTable

Carry&

ControlLogic

O

YB

Y

F4F3F2F1

XB

X

Look-UpTable

F5IN

BYSR

S

Carry&

ControlLogic

CINCLKCE SLICE

Carry & Control Logic

x yCOUT

0011

0101

y

y

CIN

CIN

Propagate = x yGenerate = ySum= Propagate CIN = x y CIN

xy

Carry & Control Logic in Xilinx FPGAs

Carry & Control Logic in Spartan 3 FPGAs

LUT

Hardwired (fast) logic

Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One

Logic Cell

Simplified View of Carry Logic in One Spartan 3 Slice

Critical Path for anAdder Implemented UsingXilinx Spartan 3 FPGAs

Number and Length of Carry Chainsfor Spartan 3 FPGAs

Bottom Operand Input to Carry Out DelayTOPCYF

0.9 ns for Spartan 3


Carry Propagation DelaytBYP

Carry Input to Top Sum Combinational Output DelayTCINY


Critical Path Delays and Maximum Clock Frequencies(into account surrounding registers)

Major Differences between Xilinx Families

Number of CLB slicesper CLB

Number of LUTsper CLB slice

Look-Up Tables

Number of adderstages per CLB slice

Spartan 3Virtex 4

Virtex 5, Virtex 6,Spartan 6

4-input 6-input

4

2

2

2

4

4

Altera Cyclone IIILogic Element (LE) – Normal Mode

Altera Cyclone IIILogic Element (LE) – Arithmetic Mode

Altera Stratix III, Stratix IVAdaptive Logic Modules (ALM) – Normal Mode

Altera Stratix III, Stratix IVAdaptive Logic Modules (ALM) – Arithmetic Mode

Bit-Serial & Digit-Serial Adders

Bit-serialadder

xi yi

si

c0

startci+1

clk

Digit-serialadder

d d

d

xi yi

si

c0

startci+1

clk

Addition of a Constant

Addition of a constant (1)

xk-1 xk-2 . . . x1 x0

yk-1 yk-2 . . . y1 y0

variableconstant+

xk-1 xk-2 . . . xh+1 xh xh-1 . . . x0

yk-1 yk-2 . . . yh+1 1 0 . . . 0

variableconstant+

xh xh-1 . . . x0

sk-1 sk-2 . . . s1 s0

sk-1 sk-2 . . . sh+1

Addition of a constant (2)

. . .HA/MHA

HA/MHA

HA/MHA

HA/MHA

x0xh-1xhxh+1xh+2xk-1 xk-2 . . . . . .

. .

x0xh-1xhsh+1sh+2

sk-1 sk-2 . . . . . .

If yi = 0 Half-adder (HA) yi = 1 Modified half-adder (MHA)

ck

Modified half-adder

x

y

c

sMHA

x + y + 1 = ( c s )2

2 1

x y c s0011

0101

0111

1001

HA HAHAHA

x1x2xk-1 xk-2 . . .

. .

s1s2sk-1 sk-2 . . .

x0

x0

ck

Incrementer

MHA MHAMHAMHA

x1x2xk-1 xk-2 . . .

. .

s1s2sk-1 sk-2 . . .

x0

x0

ck

Decrementer

Asynchronous Adders

Possible solutions to the carry propagate problem

1. Detect the end of propagation rather than wait for the worst-case time

2. Speed-up propagation via • look-ahead• carry skip• carry select, etc

3. Limit carry propagation to within a small number of bits

4. Eliminate carry propagation through the redundant number representation

Analysis of carry propagation

Probability of carry generation = (xiyi = 11)4

1

Probability of carry propagation = (xiyi = 01 or 10)2

1

Probability of carry anihilation = (xiyi = 00 or 11)21

j j-1 . . . . . . . i+1 i

1 0 … 1 …0 … 1 11 1 … 0 …1 … 0 1

Probability of carry propagatingfrom position i to position j

=

11 or 00 01 or 10

1

21 ij

21

probability of propagation

probability of anihilation

=ij

21

Expected length of the carry chain that starts at position i (1)

Expected length(i, k) =

ikik

ijk

ij

ij

1

2

1)(

2

11

1

)(

Lengthof the carry chain

Probabilityof the given length

Probabilityof propagationtill the end ofadder

Distancetill the end of adder

Expected length of the carry chain that starts at position i (2)

Expected length(i, k) =

)1(22 ik

For i << k

Expected length of the carry propagation is 2

basic adders and counters implementation of adders in fpgas ece 645: lecture 3

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