bambang a. b. sarif coe-kfupm logic synthesis using sis

Bambang A. B. Sarif

COE-KFUPM

Logic Synthesis Using SIS

2 /35Bambang A. B. Sarif, COE-KFUPM

Agenda

• Introduction

• Logic Synthesis Using SIS– Combinational Logic Synthesis– Sequential Logic Synthesis– Technology Mapping– Input File Format

• Example


Introduction

• Early effort on Logic synthesis is dated back in the early 50’s and 60’s– Quine and McCluskey algorithms

• Two level logic synthesis (1984)– ESPRESSO

• Multi level logic synthesis– Combinational Logic (1987): MIS– Sequential Logic (1990): SIS


Introduction: ESPRESSO

• Running time of Quine McCluskey algorithm is O(3n/n)– Finding minimum cover is an NP-complete problem

• ESPRESSO:– Trades speed with exact solution– Using heuristic

• Procedures of ESPRESSO:– Expand: expand prime implicants to its highest cover– Irredundant Cover: remove redundant implicants– Reduce: reduce prime implicants


Introduction: SIS

• It was developed by CAD research group of UC Berkeley (http://www-cad.eecs.berkeley.edu/)

• It is a software package consisting of tools for logic synthesis:– ESPRESSO, MIS, NOVA, JEDI, etc.

• Synthesis process is roughly divided into two phases:– Technology independent phase– Technology dependent phase (technology mapping)


Introduction: SIS(2)

• SIS can be executed using batch files

• It is available in ccse network in /tools/sis/

• Documentations are available in /tools/sis/doc/ and in http://www.ccse.kfupm.edu.sa/~sarif/logic_synthesis.htm


Logic Synthesis using SIS:SIS Environment (1)

• To invoke SIS, type SIS in your shell

• To exit from SIS environment, type quit

• To execute a unix command in SIS environment, use ‘!’ before the command– Example: sis>!type adder.eqn

• SIS can be executed in batch mode (either command line or file script). Example: – sarif>sis -t type1 –T type2 -o outname -f scriptname < inputname >

result.txtWill invoke SIS using type1 input file whose name is inputname, using script file scriptname, write the output in type2 format with filename outname and dump all result in result.txt file


Logic Synthesis using SIS:SIS Environment (2)

• To print all SIS commands: print_help

• SIS commands is categorized into several classes:– Input/output commands– Network manipulation commands– Network status command– Etc


Logic Synthesis using SIS:Input and Output Commands

• Input commands: read the circuits (network) or set some constraints– Usually begin with “read_”. Example: read_eqn,

read_pla, read_blif– Sets some parameters using “set_” commands:

set_delay, set_state

• Output commands: write the networks– Usually begin with “write_”. Example: write_pla,

write_eqn, write_bdnet


Logic Synthesis using SIS:Network Status Commands

• To print the required information. Usually begin with “print_”. – Example: print, print_stats, print_delay,

print_kernel, print_gates, print_map_stats– Other: power_estimate, power_print


Logic Synthesis using SIS:Network Manipulation Commands

• This type of commands are used to ‘manipulate’ our network to get the most optimize representations.

• There is no stick rule on which commands to use nor the order to invoke those commands

• Everybody are welcomed to ‘experiments’ with their own approach to get the best results

• The commands can be divided roughly into commands for combinational and sequential logic circuits.


Logic Synthesis using SIS: Combinational Logic Synthesis

• Combinational logic synthesis in SIS is targeting multi level logic form through these steps:– Decomposition– Extraction– Factoring– Substitution– Collapsing

• The input file can be in the form of pla, blif, eqn or slif command

• The commonly used commands are: simplify, full_simplify, resub, eliminate, fx, gx, gcx, sweep


Logic Synthesis using SIS: Combinational Logic Synthesis (2)

• There is a famous script used for combinational circuits targeting area minimization, i.e., rugged.script. The script contains the following commands:– sweep; eliminate – simplify -m nocomp– eliminate – sweep; eliminate – simplify -m nocomp– resub -a– fx– resub –a; sweep– eliminate; sweep– full_simplify -m nocomp


Logic Synthesis using SIS: Combinational Logic Synthesis (3)

• Script used for combinational circuits targeting delay minimization, i.e., delay.script contains the following:– sweep; decomp -q– tech_decomp -o 2– resub -a –d; sweep– reduce_depth -b -r– red_removal – eliminate -l 100 -1– simplify -l– full_simplify -l– sweep; decomp -q– fx -l – tech_decomp -o 2


Logic Synthesis using SIS: Sequential Logic Synthesis

• Divided roughly into two parts: the minimization of sequential parts and minimization of combinational parts of the circuits.

• The input file can be in the form of blif, slif, kiss or stg file.

• The minimization of sequential part consists of:– State minimization using STAMINA– State assignment using NOVA or JEDI– Retiming (retiming and resynthesis)


Logic Synthesis using SIS: Technology Mapping (1)

• Technology library is given in genlib format and should be read before technology mapping.

• The technology mapping is based on tree-covering algorithm: decompose the functions into 2-input NAND gates and inverters, then covered by patterns that represents the possible choices of gate in the library.– Effective for area minimization

• The mapping is performed by using map command.– There is option for area (delay) optimization with delay

(area) consideration


Logic Synthesis using SIS: Technology Mapping (2)

• Example of how different technology mapping for a 4-bit ripple carry adder

• Command Area Delay

map -m 0.5 –AFW 45 gates, 64960.00 12.33

map -n 1 –AFGW 43 gates, 63104.00 11.89

map -m 0 27 gates, 47328.00 16.45

map -m 0.5 35 gates, 54752.00 14.00

map -m 1 39 gates, 66352.00 14.97


Logic Synthesis using SIS: Input File Format (1)

Equation file (eqn)

• The logic equations are of the form signal = expression ;

• The following operators may be used to construct the expression

• ( ) grouping• & or * or space AND• | or + OR• ! (prefix) or ‘ (postfix) NOT• != or ^ XOR• == XNOR

• Hence, F = a*!b + c*!d ; and F = a b' + c d' ; represent the same equation



• The commands INORDER and OUTORDER can be used to specify the primary inputs and primary outputs for the network.

• For example

INORDER = a b c d;

OUTORDER = p;

t = c + !b;

p = !d*a + !t*!a;



PLA (truth table) format

• The following keywords are recognised, where [d] denotes a decimal number and [s] denotes a text string.

.i [d] Specifies the number of input variables.

.o [d] Specifies the number of output functions.

.ilb [s1] [s2] . . . [sn] Gives the names of the input variables.

.ob [s1] [s2] . . . [sn] Gives the names of the output functions.

.p [d] Specifies the number of product terms. (optional)

The product terms (one per line) are now specified -

inputs outputs (See below)

.e or .end Marks the end of the description.

• Comments are allowed within the input file, following a # character.



.i 4

.o 1

.ilb a b c d

.ob f

.p 100100 10101 10110 11000 11001 11010 11101 10000 -0111 -1111 -.e

-- # inputs-- # outputs-- input names-- output name-- number of product terms-- A'BC'D'-- A'BC'D-- A'BCD'-- AB'C'D'-- AB'C'D-- AB'CD'-- ABC'D-- A'B'C'D' don't care-- A'BCD don't care-- ABCD don't care-- end of list

ƒ(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)



KISS2 (state table) format

• In order to represent sequential designs, the previous truth-table format is extended to include ‘present state’ and ‘next state’ entries, so allowing state tables to be described.

• The following commands are used

.s [d] Specifies the number of states. (optional)

.r [s] Specifies the reset state. (optional)

The entries in the state table are now given -

inputs current_state next_state outputs

where current_state and next_state are symbolic names representing the circuit states.



Example

.i 1

.o 1

0 st0 st0 0

1 st0 st1 0

0 st1 st2 0

1 st1 st1 0

0 st2 st0 0

1 st2 st1 1

.e



BLIF Format

• Describe the hierarchical logic level of a given circuit in a textual form.

• A circuit is viewed as directed graph of combinational and sequential logic nodes.

• The format consists of the following information:– Model : flattened hierarchical circuit (input, output, clock)– Logic gates– External don’t cares– Flip-flop and latches– Library gates– Model (subcircuit) references– Subfile references– FSM description (KISS format)– Clock constraints– Delay constraints



Genlib Format

• It is used to specify the gates in SIS

• A cell is specified in the following format:GATE <cell-name> <cell-area> <cell-logic function>

<pin-info>

…….

<pin-info>

• A pin is specified in the following format:PIN <pin-name> <phase> <input-load> <max-load> <rise-block delay> <rise-fanout-delay><fall-block-delay><fall-fanout-delay>



• A latch is specified in the following format:LATCH <cell-name> <cell-area> <cell-logic-function>

<pin-info>

……

<pin-info>

<latch-spec>

[<clock-delay-info>] [<constraints-info>]

• Latch-spec is defined asSEQ <latch-input> <latch-output> <latch-type>


Example: Combinational Logic (1)

FULL Adder

• PLA file (fa.pla):

# Full Adder

.i 3

.o 2

.ilb a b cin

.ob sum co

.p 8000 0 0001 1 0010 1 0011 0 1100 1 0101 0 1110 0 1111 1 1.e

• Invoke SIS and read the pla file

$ sis

UC Berkeley, SIS 1.3

sis>read_pla fa.pla

sis>p

{sum} = a b cin + a b' cin' + a' b cin' + a' b' cin{co} = a b cin + a b cin' + a b' cin + a' b cin

• sis> simplify *

• sis> print

{co} = a b + a ci + b ci{sum} = a b ci + a b' ci' + a' b ci' + a' b' ci

• sis > print_factor

{co} = ci (b + a) + a b{sum} = ci (a' b' + a b) + ci' (a b' + a' b)



• sis> tech_decomp -o 4 -a 4

• sis> print{co} = [848] + [849] + [850]

{sum} = [844] + [845] + [846] + [847]

[844] = a b' ci'

[845] = a' b ci'

[846] = a' b' ci

[847] = a b ci

[848] = b ci

[849] = a ci

[850] = a b

• sis> read_library msu.genlib

• sis> map

• sis> print{co} = a b + a ci + b ci[1207] = a'[1205] = b'[1214] = [1205] [1207] ci + a b ci[844] = [1207]' b' ci'[845] = [1205]' a' ci'{sum} = [1214] + [844] + [845]



• sis> print_map_stats

Total Area = 352.00

Gate Count = 12

Buffer Count = 0

Most Negative Slack = -5.00

Sum of Negative Slack = - 10.00

Number of Critical PO = 2

• sis> read_eqn full.adder

• sis> source script

• sis> print

{co} = a b + a ci + b ci

{sum} = {co}' a + {co}' b + {co}' ci + a b ci


Example: Sequential Logic (1)

• sis> read_kiss mark1.kiss2

mark1.kiss2 pi= 5 po=16 nodes= 0 latches= 0

lits(sop)= 0 lits(fac)= 0 #states(STG)= 16

• sis> state_minimize stamina

Running stamina, written by June Rho, University of Colorado at Boulder

Number of states in original machine : 16

Number of states in minimized machine : 12





• sis> state_assign jedi



• sis> source script



• sis> full_simplify





• sis> extract_seq_dc

number of latches = 4 depth = 6 states visited = 12

• sis> full_simplify



• sis> extract_seq_dc

• sis> source script.rugged





• sis> retime -n

Lower bound on the cycle time = 3.40

Retiming will minimize the cycle time

RETIME: Initial clk = 13.60, Desired clk = 3.40

initial cycle delay = 13.60

initial number of registers = 4

initial logic cost = 78.00

initial register cost = 4.00

Failed at 3.40 : Now attempting 8.50






Success at 13.44, Delay is 13.40

Success: Now attempting 13.34

Quitting binary search at 13.34

final cycle delay = 13.40

final number of registers = 8

final logic cost = 78.00

final register cost = 8.00

RETIME: Final cycle time achieved = 13.40

mark1.kiss2 pi= 5 po= 16 nodes= 17 latches= 8

lits(sop)= 70 lits(fac)= 66



• sis> rlib lib2.genlib

• sis> map -s

total gate area: 104864.00

maximum arrival time: (19.75,20.35)


lits(sop)= 120 lits(fac)= 105


Questions ??

bambang a. b. sarif coe-kfupm logic synthesis using sis

Documents

sis slide

sis environment

type sis

sis2 sis

print slide

help sis commands

file slide

synthesis process