bai tap ve diode 1

Part I Lectures 1-7

Diode Circuit Applications

University of Technology The PN Junction Diode Electrical and Electronic Engineering Department Lecture One - Page 1 of 7

Second Year, Electronics I, 2009 - 2010 Dr. Ahmed Saadoon Ezzulddin

The PN Junction Diode Basic Construction: When acceptor impurities are introduced into one side and donors into the other side of a single crystal of a semiconductor, a p-n junction is formed. In general, the acceptor ion is indicated by a minus sign because, after this atom "accepts" an electron, it becomes a negative ion. The donor ion is represented by a plus sign because, after this impurity atom "donates" an electron, it becomes a positive ion. Now, if a junction is formed between a sample of p-type and one of an n-type semiconductor, this combination possesses the properties of a rectifier (permits the flow of charge in one direction). Such a two-terminal device is called a p-n junction diode.

The two single crystal semiconductors (having four valence electrons) used most frequently in the construction of p-n junction diodes are silicon (Si) and germanium (Ge).

The p-type is created by introducing those impurity elements (acceptors) that have three valence electrons (trivalent), such as boron, gallium, and indium.

The n-type is created by introducing those impurity elements (donors) that have five valence electrons (pentavalent), such as antimony, arsenic, and phosphorus.

In a p-type material the hole is the majority carrier and the electron is the minority carrier.

In an n-type material the electron is called the majority carrier and the hole the minority carrier.

The electrons and holes in the region of the junction will combine, resulting in a lack of carriers in the region near the junction. This region of uncovered positive and negative ions is called the "depletion region" due to the depletion of carriers in this region.

Essential Characteristics: The essential electrical characteristic of a p-n junction is that it constitutes a rectifier which permits the easy flow of charge in one direction but restrains the flow in the opposite direction. We consider now how this diode rectifier action comes above. No Applied Bias (VD = 0 V): In the absence of an applied bias voltage, the net flow of charge in any one direction for a semiconductor diode is zero (see Fig. 1-1).

Fig. 1-1



N P

ode

ode

Cat

h

An

Reverse Bias (VD < 0 V): The current that exists under reverse-bias conditions is called the reverse saturation current and is represented by Is (see Fig. 1-2).

Fig. 1-2 Forward Bias (VD > 0 V): A semiconductor diode is forward-biased when the association p-type and positive and n-type and negative has been established (see Fig. 1-3).

Fig. 1-3 I-V Characteristic Carve and Current Equation: Forward-bias region

Reverse-bias region Reverse-breakdown region

Fig. 1-4

)1( / −= KD TkVSD eII [1.1]

Where k = 11600/η with η = 1 for Ge and η = 2 for Si for relatively low levels of diode

current and η =1 for Ge and Si for higher levels of diode current. TK = TC + 273o.



Resistance Levels: 1. DC or Static Resistance: The application of a dc voltage to a circuit containing a p-n junction diode will result in an operating point on the characteristic carve that will not change with time. The resistance of the diode at the operating point can found simply by finding the corresponding levels of VD and ID as shown in Fig. 1-5 and applying the following equation:

D

DD I

VR = [1.2]

Fig. 1-5

2. Ac or Dynamic Resistance: If a sinusoidal rather than dc input is applied, the varying input will move the instantaneous operating point up and down a region of the characteristics and thus defines a specific change in current and voltage as shown in Fig. 1-6. With no applied varying signal, the point of operation would be the Q-point determined by the applied dc levels. A straight line drawn tangent to the curve through the Q-point will define a particular change in voltage and current that can be used to determine the ac or dynamic resistance for this region of the diode characteristics. In equation form,

d

dd I

VrΔΔ

= [1.3]

Fig. 1-6



In differential calculus, the derivative of a function at a point is equal to the slope of the tangent line drawn at that point. Eq. [1.3], as defined by Fig. 1-6, is, therefore, essentially finding the derivative of the function at the Q-point of operation. If we find the derivative of the general Eq. [1.1] for the p-n junction diode with respect to the applied forward bias and then invert the result, we will have an equation for the dynamic or ac resistance in that region. That is;

)]1([)( / −= KD TkVSD

DeI

dVdI

dVd

)( SDKD

D IITk

dVdI

+=

DkD

D ITk

dVdI

≅ ( Generally, ) SD II >>

DD

D IdVdI 93.38= ( η = 1 & TK = 298o => 93.38

29811600

≅=KT

K )

DD

D

IdIdVivr 026.0/ ≅==

Dd I

mVr 26= [1.4]

All the resistance levels determined thus far have been defined by the p-n

junction and do not include the resistance of the semiconductor material itself (called body resistance) and the resistance introduce by the connection between the semiconductor material and the external metallic conductor (called contact resistance). These additional resistance levels can be included in Eq. [1.4] by adding resistance denoted by rB appearing in Eq. [1.5].

BD

d rImVr +=′

26 [1.5]

3. Average AC Resistance: If the input signal is sufficiently large to produce a board swing such as indicated in Fig. 1-7, the resistance associated with the device for this region is called the average ac resistance. The average ac resistance is, by definition, the resistance determined by a straight line drawn between the two intersection establish by the maximum and minimum value of input voltage. In equation form,

.. pttoptd

dav I

VrΔΔ

= [1.6]



DI

DV0

−+ DV

TD VV >

−+ TV

DI

+− DV

TD VV <

DI

DV0 TV

−+ DV

TD VV >

−+ TV )(Favr

DI

+− DV

TD VV <

)(Ravr

DI

DI

DV0 TV

)(Favr

)(Ravr

−+ DV

0>DV DI

+− DV

0<DV

Fig. 1-7 Equivalent Circuits (Models): 1. Piecewise-Linear Model: (see Fig.1-8); Forward-bias; Reverse-bias; Fig. 1-8 2. Simplified Model: (see Fig. 1-9); Forward-bias & Rnetwork >> rav(F); Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-9 3. Ideal Model: (see Fig. 1-9); Forward-bias, Enetwork >> VT, Rnetwork >> rav(F) & VD = 0 V; Reverse-bias, rav(R) = ∞ Ω & ID = 0 A; Fig. 1-10



+

−E

−+ DV

DI

R+

−RV

Si

Ωk3.3

V20

Ωk6.5

2DESi

1D

2R

1R

Load-Line Analysis: From Fig. 1-11:

0=−− RD VVE RIVE DD +=

RE

RVI D

D +−= [1.7]

Eq. [1.7] is a linear equation; cmxy += ,

where Rm /1−= & REc /= .

REIV

EVI

DD

DD

=⇒=

=⇒=

0

0 [1.8] Fig. 1-11

Example 1-1: Determine the currents , , and for the network of Fig. 1-12.

1DI2DI

1RI

Fig. 1-12

Solution:

.212.03.37.0

1

21

mAkR

VI D

R ===

Appling KVL yields: 0

212=−−+− DDR VVEV

and VVVEV DDR 6.187.07.020212

=−−=−−= ,

with .32.36.56.18

2

21

mAkR

VI R

D ===

Finally, mAmmIII RDD 108.3212.032.3112

=−=−= .



Exercises: Find the values of ID and Vo in the circuits shown in Fig. 1-13.

V10−

Ge

Si

1oV

2oV

Ωk2.1

Ωk3.3

DI

Ge Si

Si

Ωk3

V16+

V12+

oV

DI Si1DI

Ωk2

Si

Ωk2

Ge

oV

2DI

Ωk2

V10+

Si Ge

1oV

2oVΩk47.0

V20

Ωk1

1DI2DI

SitSinω10 )(tId

)(tVo

Ωk2

Ω= kr Fav 1.0)(Ω= Mr Rav 1)(

(a) (b) (c)

(d) (e)

Fig. 1-13

University of Technology Diode Switching Circuits Electrical and Electronic Engineering Department Lecture Two - Page 1 of 3


V5+ V5− V2−

V3+ V8+

V3+ V7−

V2−

Ωk1 Ωk1 Ωk1 Ωk1 Ωk1

I I I I I

AV

BV

1D

2DoV

R

AV

BV

V+

oV1D

2D

R

Diode Switching Circuits Basic Concepts: Diode switching circuits typically contain two or more diodes, each of which is connected to an independent voltage source. Understanding the operation of a diode switching circuit depends on determining which diodes, if any, are forward biased and which, if any, are reverse biased. The key to this determination is remembering that a diode is forward biased only if its anode is positive with respect to its cathode (see Fig. 2-1). One of the very import applications of diode switching circuits is logic gates. Fig. 2-1 Logic Gates: Diodes can be used to form logic gates, which perform some of the logic operations required in digital computers. OR Gate: It has output when there a signal in any input channels (see Fig. 2-2).

Input voltages State of diodes Output voltageVA VB D1 D2 Vo 0 0 off off 0 0 1 off on 1 1 0 on off 1 1 1 on on 1

Fig. 2-2

AND Gate: It has output only when all inputs are present (see Fig. 2-3).

Input voltages State of diodes Output voltageVA VB D1 D2 Vo 0 0 on on 0 0 1 on off 0 1 0 off on 0 1 1 off off 1

Fig. 2-3



oV

R

V5+

V5−

V5+1D

2D

3D

4DV5−

V5+

oV

R

V15+

V0

V5+1D

2D

3DV10−

oV

R

V10−

V5+

V5−1D

2D

(a) (b) (c)

Example 2-1: Determine which diodes are forward biased and which are reverse biased in the circuits shown in Fig. 2-4. Assuming a 0.7-V drop across each forward-biased diode, determine the output voltage Vo.

Fig. 2-4 Solution: In (a) the net forward-biasing voltage between supply and input for each diode is

D1 & D3: +5 - (+5) = 0V, D2 & D4: +5 - (-5) = 10V.

Therefore, D2 and D4 are forward biased and D1 and D3 are reverse biased. Vo = -5 + 0.7 = -4.3V.

While in (b) the net forward-biasing voltage between supply and input for each diode is

D1: +15 - (+5) = +10V, D2: +15 - 0 = +15V, D3: +15 - (-10) = +25V.

Therefore, D3 is forward biased and D1 and D2 are reverse biased. Vo = -10 + 0.7 = -9.3V.

Finally, in (c) the net forward-biasing voltage between supply and input for each diode is

D1: -5 - (-10) = +5V, D2: +5 - (-10) = +15V.

Therefore, D2 is forward biased and D1 is reverse biased. Vo = +5 - 0.7 = +4.3V.



Exercises: Determine Vo and I for each circuit in Fig. 2-5. Assume that each of the diodes in these circuits has a forward voltage drop of 0.7 V.

(a) (b) (c)

(d) (e)

oVIΩk2

V10+

V6+

V2−

V4−1D

2D

3D

4D

I

3D

4DoV

1D

2D

Ωk2

V5+

V2+

V1−

V4−

IoV

1D

2D

Ωk1.5

AV

BV

Ωk1

Ωk1

1.2.3.

,0VVV BA ==

.5&0 VVVV BA ==and,V5VV BA ==

1D

2D

3D

Ωk2

V20+

V15−

V15−

Ωk1

Ωk1

I

Ωk12oV

1oV

C

C

A

B

1. No pulses at either A or B,2. A 30 V positive pulse at A or B, and3. Positive pulses (30 V) at both A and B.

oVI

Ωk2

V3+

V5−

V8−1D

2D

3D

4D

V15−

Fig. 2-5

University of Technology Diode Clipping Circuits Electrical and Electronic Engineering Department Lecture Three - Page 1 of 8


RSiV2.5

ovivDE

0 tTT/2

iv

- 9

9

D

R+

−ov

+

−iv

V−0 t

ov

T/2 T

V

V−0

iv

tT/2T

D

R

+

−ov

+

−iv

V

0 t

ov

T/2 T

V

V−0

iv

tT/2T

Diode Clipping Circuits Basic Definition: There are a variety of diode circuits called clippers (limiters or selectors) that have the ability to "clip" off a portion of the input signal above (positive) or below (negative) certain level without distorting the remaining part of the alternating waveform. Depending on the orientation of the diode, the positive or negative region of the input signal is "clipped" off. There are two general categories of clippers: series and parallel. The series configuration is dined as one where the diode is in series with the load. While the parallel variety has the diode in a branch parallel to the load (see Fig. 3-1).

Simple Series (Positive) Clipper

Simple Parallel (Negative) Clipper

Fig. 3-1 Example 3-1: Biased Series (Negative) Clipper, see Fig. 3-2.

Fig. 3-2



0 tTT/2

iv

- 10

10

R

Sioviv

D

E V7.5

13.5

4.5

ov

- 4.5- 9 iv90

iV

13.5

4.5

0TT/2 t1 t2

t

13.5

4.5

0 t

ov

- 4.5

RV5.4

oviviV

Ideal

DTVE −

For t = 0 → t1 and t2 → T; D ON, and vo = vi + 4.5 V. For t = t1 → t2; D OFF, and vo = 0 V.

Fig. 3-2 (cont.) Example 3-2: Biased Parallel (Positive) Clipper, see Fig. 3-3.

Fig. 3-3



R

Si

ov

DE V7.5

transitionV+

−

0id =

- 10

ov

iv10

- 10

- 5

- 50

iv

10

-5

0 TT/2t1 t2

t

ov

- 10

-5

0 t

- 10

transitionV

Vtransition – id R – Vd + E = 0; Vtransition = 0.7 – 5.7 = – 5 V. For t = 0 → t1 and t2 → T; D ON, and vo = – 5 V. For t = t1 → t2; D OFF, and vo = vi.

Fig. 3-3 (cont.) Summary: A variety of series and parallel clippers with the resulting output for the sinusoidal input are provided in Fig. 3-4.

Fig. 3-4



0 tTT/2

iv

-12

12

R

SiV3.3oviv

1D1E

GeV7.7

2D2E

R

V4oviv

1D11 TVE +

V8

2D22 TVE +

1iV

2iV

Ideal

Ideal

Fig. 3-4 (cont.) Example 3-3: Double Diode Series Clipper, see Fig. 3-5.

Fig. 3-5



0 t

TT/2

iv

- 4

20

8

- 16

ov

- 4

8

0 t

t1 t2 t3 t4

2iV

1iV

01=di

R

Siov

1E V3.21D

1trV+

−

Rov

2E V3.52D Si

2trV+

−

02=di

Roviv

Si

1E V3.2 2E 3.5

1D 2D Si

V0 t

T

T/2

iv

- 9

9

ov

iv

8

- 4

- 8- 12

1240

For t = 0 → t1, t2 → t3, and t4 → T; both D1 and D2 will be OFF, and vo = 0 V. For t = t1 → t2; D1 ON while D2 OFF, and vo = V = vi – 4 V.

1i

For t = t3 → t4; D1 OFF while D2 ON, and vo = V = vi + 8 V.

2i

Fig. 3-5 (cont.) Example 3-4: Double Diode Parallel Clipper, see Fig. 3-6. V – i R – Vd – E1 = 0; + i R + Vd + E2 = 0;

1tr 1d 2trV2d

V = 0.7 + 2.3 = 3 V. = – 0.7 – 5.3 = – 6 V. 1tr 2trV

Fig. 3-6



0 tTT/2

iv

- 10

10

RIdialoviv

D

E V5

0 tT

T/2

iv

- 9

9

3

- 6

0 t

3

- 6

1trV

2trV

ov

t1 t2 t3 t4

- 6

ov

iv9

- 6

0 3

3- 9

For t = 0 → t1, t2 → t3, and t4 → T; both D1 and D2 will be OFF, and vo = vi. For t = t1 → t2; D1 ON while D2 OFF, and vo = 3 V. For t = t3 → t4; D1 OFF while D2 ON, and vo = – 6 V.

Fig. 3-6 (cont.) Example 3-5: Special Type Clipper: A Comparator, see Fig. 3-7.

Fig. 3-7



12

6

- 12

ov

iv120 6

12

- 6- 12

ov

iv120

- 6

(a) (b)

0 tTT/2

iv

- 10

10

0 t

iv

10

5

5

t1 t2

E

10

5

- 10

ov

iv100 5

For t = 0 → t1 and t2 → T; D OFF, and vo = E = 5 V. For t = t1 → t2; D ON, and vo = vi.

Fig. 3-7 (cont.) Exercises: 1. Design biased parallel clippers (with silicon diodes) to perform the functions

indicated in the transfer characteristics of Fig. 3-8.

Fig. 3.8



2. Sketch the output voltage (vo) and the transfer characteristics (vo against vi) for each circuit of Fig. 3-9 for the input (vi) shown.

0 tT

iv

10R

2E V3.2

D Si

1E

V4iv ov

0 tTT/2

iv

- 8

8

0 tT

iv

150

(a)

(b)

(c)

(d)

iv ov

1D

R

2DGe Si

V3.3 V3.51E 2E0 t

TT/2

iv

- 9

9

1D 2D

Ideal Idealiv ov

1R 2RΩk100 Ωk200

1E 2EV25 V100

RIdealoviv

D

E V4

Fig. 3-9

University of Technology Diode Clamping Circuits Electrical and Electronic Engineering Department Lecture Four - Page 1 of 4


ovV5

Ωk50

CV

V20V7.0

_

+

_ +_

+

+

_

C

Fμ1.0iv ov

D

E V5

SiR Ωk500 tTT/2

iv

- 20

10 kHzf 1=

-53T/2 2T

Diode Clamping Circuits Basic Definition: The clamping circuit (clamper) is one will "clamp" a signal to a different dc level. The circuit must have a capacitor, a diode, and a resistive element, but it can also employ an independent dc supply to introduce an additional shift. The magnitude of R and C must be chosen such that the time constant τ = RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval (T/2) the diode is nonconducting. Throughout the analysis we will assume that for all practical purposes the capacitor will fully charge or discharge in five time constants. Therefore, the condition required for the capacitor to hold its voltage during the discharge period between pulses of the input signal is

fTRC

21

255 =>>=τ [4.1]

Example 4-1: Determine the output (vo) for the circuit of Fig. 4-1 for the input (vi) shown.

Fig. 4-1 Solution: The analysis of clamping circuits are started by considering that the part of the input signal that will forward bias the diode. For the circuit of Fig. 4-1, the diode is forward bias ("on" state) during the negative half period of the input signal (vi) and the capacitor will charge up instantaneously to a voltage level determined by the circuit of Fig. 4-2.

Fig. 4-2



ovV5

Ωk50V10_

+

_ ++

_

V3.24

0 tTT/2

ov

4.3

34.3

19.3

3T/2 2T 5T/2

For the input section KVL will result in – 20 + VC + 0.7 – 5 = 0 => VC = 24.3 V. The output voltage (vo) can be determined by KVL in the output section + 5 – 0.7 – vo = 0 => vo = 4.3 V.

Now check that the capacitor will hold on or not its establish voltage level during

the period (positive half period in case of Example 4-1) when the diode is in the "off" state (reverse bias). The total time constant 5τ of the discharging circuit of Fig. 4-3 is determined by the product 5RC and has the magnitude

5τ = 5RC = 5 (50×103) (0.1×10-6) = 25 ms. The frequency ( f ) is 1 kHz, resulting in a period of 1 ms and an interval of 0.5 ms between levels, that is T/2 = 1/( 2f ) = 1/(2 × 1×103) = 0.5 ms. We find that 5 τ >> T/2 ( 25ms / 0.5ms = 50 times). So that, it is certainly a good approximation that the capacitor will hold its voltage (24.3 V) during the discharge period between pulses of the input signal.

Fig. 4-3 The open-circuit equivalent for the diode will remove the 5-V battery from having any effect on vo, and applying KVL around the outside loop of circuit will result in + 10 + 24.3 – vo = 0 => vo = 34.3 V.

The resulting output appears in Fig. 4-4, where the input and the output swing are the same.

Fig. 4-4



CV

Vvi 15= V7.0

_

+

_+

_+ +

_R Vvo 5=

E

0 tTT/2

iv

-5

15

5

3T/2 2T

Civ ov

D

E V3.4

SiR

0 tTT/2

ov

-15

5

3T/2 2T

-5

Example 4-2: Using silicon diode, design a clamper circuit that will produce output vo = 10Sinωt–5 V when the input is vi = 10Sinωt+5 V. Draw the circuit diagram and the input and output signals. Solution: From the input (vi) and output (vo) signals, we have a negative biased clamper. Therefore, the diode is forward bias ("on" state) during the positive half period of the input signal (vi). The output voltage (vo) at this positive period can be determined by KVL in the output section of the circuit shown in Fig. 4-5.

E + 0.7 – vo = 0 => E = 5 – 0.7 = 4.3 V. For the input section KVL will result in 15 – VC – 5 = 0 => VC = 10 V.

Fig. 4-5 The circuit diagram and the input and output signals are shown in Fig. 4-6.

Fig. 4-6



Summary: A number of clamping circuits and their effect on the square-wave input signal are shown in Fig. 4-7.

Negative Clampers Positive Clampers

Clampers with ideal diodes and 5τ = 5RC >> T/2

Fig. 4-7 Exercise: Sketch the output (vo) for the circuit of Fig. 4-8 for the input (vi) shown. Assume ideal diodes.

0 tT

T/2

iv

-15

15C

iv ov2E V10

1D 2D

1E

0E

V3

V7

1R

2R+

−

+

−

Fig. 4-8

University of Technology Diode Rectifier Circuits Electrical and Electronic Engineering Department Lecture Five - Page 1 of 10


0π2

π tω

1Vvi =VP/n

1

2

1

2

VV

NNn ==

0π2

π tωVP

2V

iv+

_ov

+

_

1N 2N

1V 2VPV LR

D

TV+

_

+ _ i

0 π2π tω

ov

T

Tff io /1==

PRV

Diode Rectifier Circuits Basic Definition: A diode circuit that converts an ac voltage to a pulsating dc voltage and permits current to flow in one direction only is called "rectifier" and the ac-to-dc conversion process is termed "rectification". Half-Wave Rectifier (HWR):

Fig. 5-1 For the half-wave rectifier circuit of Fig. 5-1:

The average (dc) value of a half-wave rectified sine-wave voltage (Vdc) is

πωω

πωω

πPR

PR

T

odcVtdtSinVtdtv

TV =⋅=⋅= ∫∫

00 21)(1

For VP close to VT, )(318.0 TPdc VVV −= [5.1a]

For VP >> VT, Pdc VV 318.0= [5.1b]

The root mean square (rms) value of the load voltage (Vrms) is

221)(1

0

22

0

2 PRPR

T

ormsVtdtSinVtdtv

TV =⋅=⋅= ∫∫

π

ωωπ

ωω

For VP close to VT, )(5.0 TPrms VVV −= [5.2a]

For VP >> VT, Prms VV 5.0= [5.2b]



0π2

π tω

1Vvi =VP/n

1

2

1

2

VV

NNn ==

0π2

π tωVP

2V

iv+

_ ov+_

1N 2N

1V 2V PV

LR

D1

D2 D3

D4 i

+ (-)

(+)-

+ (-)

(+)-

i1(i2)

ov

0 π2π tωT

io ff 2=

21 iii +=

PRV

The rms value of the ac component (or the ripple voltage) of the rectified signal [Vr(rms)] is PRPRPRdcrmsr VVVVVrmsV 385.0)318.0()5.0()( 2222 =−=−= For VP close to VT,

)(385.0)( TPr VVrmsV −= [5.3a] For VP >> VT,

Pr VrmsV 385.0)( = [5.3b]

The percent ripple (r) in the rectified waveform (also called the ripple factor) is

%121%100318.0385.0%100)(

=×=×=PR

PR

dc

r

VV

VrmsVr

Efficiency (η) = [ Pdc(load) / Ptotal(circuit) ] × 100%

%/15.40%100

)()5.0()318.0(%100

)( 2

2

2

2

LdLdP

LP

Ldrms

Ldc

RrRrIRI

RrIRI

+=×

+=×

+=η

For ideal diode (rd = 0 Ω), η = ηmax = 40.5 %

The peak inverse voltage (PIV) of the diode is PVPIV = [5.4]

The frequency of the output rectified signal (fo) is

io ff = [5.5] Full-Wave Rectifiers (FWRs): 1. A Bridge Full-Wave Rectifier:

Fig. 5-2



For the bridge full-wave rectifier circuit of Fig. 5-2:

π

ωωπ

πPR

PRdcVtdtSinVV 21

0

=⋅= ∫

For VP close to 2VT, )2(636.0 TPdc VVV −= [5.6a]

For VP >> 2VT, Pdc VV 636.0= [5.6b]

2

1

0

22 PRPRrms

VtdtSinVV =⋅= ∫π

ωωπ

For VP close to 2VT, )2(707.0 TPrms VVV −= [5.7a]

For VP >> 2VT, Prms VV 707.0= [5.7b]

PRPRPRdcrmsr VVVVVrmsV 308.0)636.0()707.0()( 2222 =−=−= For VP close to 2VT,

)2(308.0)( TPr VVrmsV −= [5.8a] For VP >> 2VT,

Pr VrmsV 308.0)( = [5.8b]

%4.48%100636.0308.0%100)(

=×=×=PR

PR

dc

r

VV

VrmsVr

%/21

81%100)2()707.0(

)636.0(%100)2( 2

2

2

2

LdLdP

LP

Ldrms

Ldc

RrRrIRI

RrIRI

+=×

+=×

+=η

For ideal diode (rd = 0 Ω), η = ηmax = 81 %

TP VVPIV 2−= [5.9]

io ff 2= [5.10]



0π2

π tωVP

2V

0π2

π tω

1Vvi =VP/n

1

2

1

2

VV

NNn ==

iv+

_ ov+_

1N 2N

1V2V PV

LR

i+ (-)

(+)-

2V

2N

+ (-)

(+)- PV

2D

1D

(i2)

i1

0 π2π tω

ov

Tio ff 2=

21 iii +=

PRV

2. A Center-Tapped (CT) Full-Wave Rectifier:

Fig. 5-3 For the center-tapped full-wave rectifier circuit of Fig. 5-3:

π

ωωπ

πPR

PRdcVtdtSinVV 21

0

=⋅= ∫

For VP close to VT, )(636.0 TPdc VVV −= [5.11a]

For VP >> VT, Pdc VV 636.0= [5.11b]

2

1

0

22 PRPRrms

VtdtSinVV =⋅= ∫π

ωωπ

For VP close to VT, )(707.0 TPrms VVV −= [5.12a]

For VP >> VT, Prms VV 707.0= [5.12b]

PRPRPRdcrmsr VVVVVrmsV 308.0)636.0()707.0()( 2222 =−=−= For VP close to VT,

)(308.0)( TPr VVrmsV −= [5.13a] For VP >> VT,

Pr VrmsV 308.0)( = [5.13b]



%4.48%100636.0308.0%100)(

=×=×=PR

PR

dc

r

VV

VrmsVr

%/1

81%100)()707.0(

)636.0(%100)( 2

2

2

2

LdLdP

LP

Ldrms

Ldc

RrRrIRI

RrIRI

+=×

+=×

+=η

For ideal diode (rd = 0 Ω), η = ηmax = 81 %

TP VVPIV −= 2 [5.14]

io ff 2= [5.15] Summary: Different parameters for the HWR and FWR circuits are listed in Table 5-1.

Table 5-1

FWR Parameter HWR

Bridge CT

VPR VP – VT VP – 2VT VP – VT

Vdc 0.318VPR 0.636VPR

Vrms 0.5VPR 0.707VPR

Vr 0.385VPR 0.308VPR

r 121% 48.4%

ηmax 40.5% 81%

PIV VP VP – 2VT 2VP – VT

fo fi 2fi



Vv 220=i

+

_LR2D

1D

Ω100

125.0=n

Si

Si

+_PV

_PV+

Example 5-1: The input voltage to a full-wave rectifier employing a center-tapped step-down transformer and two silicon diodes is 220 V rms, and the transformer has turns ratio n = 0.125. Draw the rectifier circuit diagram when it is connected to a 100 Ω load, and find

1. the average value of the voltage across the load. 2. the average power dissipated by the load, and 3. the minimum PIV rating required for each diode.

Solution: The rectifier circuit diagram is shown in Fig. 5-4. 1. .9.38125.022022 VnvV iP =∗∗== ( ) ( ) .3.247.09.38636.0636.0 VVVV TPdc =−=−= 2. ( ) ( ) .0.277.09.38707.0707.0 VVVV TPrms =−=−=

( ) .3.7100

0.27 22

WR

VPL

rmsav ===

3. ( ) ( ) .1.777.09.3822 VVVPIV TP =−∗=−≥

Fig. 5-4



TD OFF

PRV

Co VV =

t

)( ppVr

D ON

Charging Discharging

iv+

_LR

D

C oV+

_

T

PRV

t

)( ppVrCo VV =

iv+

_LR

2D

1D

C oV+

_

Capacitor Filters: A low-pass filter is connected across the output of a rectifier to suppress the ac components and to pass the dc component. A rudimentary low-pass filter used in power supplies consists simply of a capacitor (C) connected across the rectifier output, that is, in parallel with the load (RL), as illustrated in Fig. 5-5.

Half-wave rectifier with capacitor filter

Full-wave rectifier with capacitor filter

Fig. 5-5 Operation:

During the positive first quarter-cycle of the input, the diode is forward-biased (when Vi > VC), allowing the capacitor to charge quickly to within a diode drop of the input peak (VPR).

When the input begins to decrease below its peak, the capacitor retain its charge and the diode becomes reverse-biased (when VC > Vi).

During the remaining part of the cycle, capacitor C can discharge slowly only through load resistance RL at a rate determine by RLC time constant (τ).

The voltage fluctuation in the filtered waveforms is called the peak-to-peak ripple voltage [Vr(pp)]. In general, Vr(pp) in FWR is smaller than it is in HWR for same RL and C values (see Fig. 5-5).



T

PRV

Co VV =

t

dcV

2)( ppVr

)( ppVr

Ripple of a Capacitor Filter: We will now derive an expression for the ripple in the output of a rectifier having a capacitor filter (C) and load resistance (RL). The derivation that follows is applicable to both HWR and FWR. We can assume that the ripple voltage in a lightly loaded filter (RLC time constant (τ) is large) is a sawtooth wave as illustrated in Fig. 5-6.

Fig. 5-6 This approximation is equivalent to assuming that the capacitor charges instantaneously and that its voltage decays linearly, instead of exponentially. Assuming that the voltage decays linearly is equivalent to assuming that the discharge current (I) is constant and equal to where Vdc is the dc value of the filtered waveform. The total charge in capacitor voltage is Vr(pp) volts, and this charge occurs over the period of time T. Therefore, since

Ldc RVI /=

tIQ Δ=Δ . ,

C

TRVCQppV Ldc

r)/()( =

Δ=

Since T=1/fr, where fr is the frequency of the fundamental component of the ripple, that is, for HWR and ior fff == ior fff 2== for FWR. So that

CRf

VppVLr

dcr =)( [5.16]

or CRfppVV Lrrdc ⋅= )( [5.17] From Fig. 5-6, it is apparent that

2

)( ppVVV rPRdc −=

Subsuming from Eq. [5.16], we obtain

CRf

VVVLr

dcPRdc 2−=



Solving for Vdc, we obtain an expression for the dc voltage (Vdc) in terms of the peak rectifier voltage (VPR):

CRf

VV

Lr

PRdc

211+

= [5.18]

The rms value of a sawtooth waveform having peak-to-peak value Vr(pp) is known to be

32

)()( ppVrmsV rr = [5.19]

Therefore, from Eqs. [5.17] and [5.19], the percent ripple is

%100)(

)32/()(%100)(×=×=

CRfppVppV

VrmsVr

Lrr

r

dc

r

%10032

1×=

CRfr

Lr [5.20]

Equation [5.20] confirms our analysis of the capacitor filter: a large RLC time

constant (τ) results in a small ripple voltage, and vice versa. The light-load assumption on which our derivation is based is generally valid for percent ripple (r) less than 6.5%. From a design standpoint, the values of fr and RL, are usually fixed, and the designer's task is to select a value of C that keeps the ripple below a prescribed value. Example 5-2: A full-wave rectifier is operated from a 50 Hz line and has a filter capacitor connected across its output. What minimum value of capacitance is required if the load is 1.2 kΩ and the ripple must be no greater than 2.4%? Solution:

%10032

1×=

CRfr

Lr

C∗∗∗∗∗= 3102.150232

1024.0 =>

.100 FC μ≥



Exercises: 1. A full-wave bridge rectifier isolated from the 220 V rms power line by a transformer.

Assuming the diode voltage drops are 0.7 V. i. What turns ratio should the transformer have in order to produce an average

current of 1 A in a 10 Ω load? ii. What is the average current in each diode under the conditions of (i)? iii. What minimum PIV rating should each diode have? iv. How much power is dissipated by each diode?

2. A full-wave bridge rectifier is operated from a 50 Hz, 220 V rms line. It has a 100 μF

filter capacitor and a 2 k Ω load. Neglect diode voltage drops. i. What is the percent ripple? ii. What is the average current in the load?

University of Technology Voltage-Multiplier Circuits Electrical and Electronic Engineering Department Lecture Six - Page 1 of 3


PV+ _

+

_PV21C

2C1D2D+

_PViv Po VV 2=

+

_+

_

Voltage-Multiplier Circuits Basic Concepts: Diodes and capacitors can be connected in various configurations to produce filtered, rectified voltages that are integer multiples of the peak value of an input sine wave. The principle of operation of these circuits is similar to that of the clamping circuits discussed previously. By using a transformer to change the amplitude of an ac voltage before it is applied to a voltage multiplier, a wide range of dc levels can be produced using this technique. One advantage of a voltage multiplier is that high voltages can be obtained without using a high-voltage transformer. Voltage Doubler: 1. Half-Wave Voltage Doubler: Figure 6-1 shows a half-wave voltage doubler circuit.

Fig. 6-1

Operation:

During the positive half-cycle, D1 ON and D2 OFF => Charging C1 up to VP.

During the negative half-cycle, D2 ON and D1 OFF => Charging C2 to 2VP.

The output (Vo) of the half-wave voltage doubler is PCo VVV 2

2== [6.1]

If a load is connected to the output of the half-wave voltage doubler, the voltage across capacitor C2 drops during the positive half-cycle (at the input) and the capacitor is recharged up to 2VP during the negative half-cycle. The output waveform across capacitor C2 is that of a half-wave signal filtered by a capacitor filter. The peak inverse voltage (PIV) rating of each diode in the half-wave voltage doubler circuit must be at least 2VP.



+_PV

2C

1D

PViv

Po VV 2=

+

_

+

_

+_PV

2D

1C+

_

2. Full-Wave Voltage Doubler: Figure 6-2 shows a full-wave voltage doubler circuit.

Fig. 6-2 Operation:

During the positive half-cycle, D1 ON and D2 OFF => Charging C1 up to VP.

During the negative half-cycle, D2 ON and D1 OFF => Charging C2 up to VP.

The output (Vo) of the full-wave voltage doubler is PCCo VVVV 2

21=+= [6.2]

If load current is drawn from the full-wave voltage doubler circuit, the voltage across the capacitors C1 and C2 is the across a capacitor fed by a full-wave rectifier. One difference is that of C1 and C2 in series, which is less than capacitance of either C1 and C2 alone. The lower capacitor value will provide poorer filtering action than the single-capacitor filter circuit. The peak inverse voltage across each diode is 2VP, as it is for filter capacitor circuit. Voltage Tripler and Quadrupler: Figure 6-3 shows an extension of the half-wave voltage doubler, which develops three and four times the peak input voltage. It should be obvious from the pattern of the circuit connection how additional diodes and capacitors may be connected so that the output voltage may also be five, six, seven, and so on, times the basic peak voltage (VP).



PV+ _

+ _

+ _

+ _

PV2

PV2 PV2

1C

2C3C

4C1D 2D 3D 4D+

_PV

)3( PVTripler

)2( PVDoubler)4( PVQuadrupler

iv+

_

Fig. 6-3 Operation:

During the positive half-cycle, D1 ON and D2, D3, D4 OFF => Charging C1 up to VP.

During the negative half-cycle, D2 ON and D1, D3, D4 OFF => Charging C2 to 2VP.

During the next positive half-cycle, D1, D3 ON and D2, D4 OFF => C2 charges C3 to 2VP.

During the next negative half-cycle, D2, D4 ON and D1, D3 OFF => C3 charges C4 to 2VP.

The voltage across the combination of C1 and C3 is 3VP and that across C2 and C4 is 4VP.

The PIV rating of each diode in the circuit must be at least 2VP. Exercises: 1. A certain voltage doubler has 35 V rms on its input. What is the output voltage?

Sketch the circuit, indicating the output terminals and PIV for the diode. 2. Repeat Exercise 1 for a voltage tripler and quadrupler. 3. The output voltage of a quadrupler is 620 V. What minimum PIV rating must each

diode have?

University of Technology Zener Diodes and Applications Electrical and Electronic Engineering Department Lecture Seven - Page 1 of 7


)(mAID

)(VVDZV

ZKI

ZMI

ZIZr

Anode

Cathode

Zener Diodes and Applications Zener Diodes: Diodes which are designed with plate power-dissipation capabilities to operate in the breakdown region may be employed as voltage-reference or constant-voltage devices. Such are known as avalanche, breakdown, or zener diodes. The zener diode is made for operation in the breakdown region. By varying the doping level, a manufacturer can produce zener diodes with breakdown voltages from about 2 to 250 V. When the applied reverse voltage reaches the breakdown value, minority carries in the depletion layer are accelerated and reach high enough velocities to dislodge valence electrons from outer orbits. The newly liberated electrons can then gain high enough velocities to free other valence electrons. In this way, we get an avalanche of free electrons. Avalanche occurs for reverse voltages greater than 6 V or so. The zener effect is different. When a diode is heavily doped, the depletion layer is very narrow. Because of this, the electric field across the depletion layer is very intense. When the field strength reaches approximately 3×107 V/m, the field is intense enough to pull electrons out of valence orbits. The creation of free electrons in this way is called zener breakdown (also known as high-field emission). The zener effect is predominant for breakdown voltages less than 4 V, the avalanche effect is predominant for breakdown voltages greater than 6 V, and both effects are present between 4 and 6 V. Originally, people thought the zener effect was the only breakdown mechanism in diodes. For this reason, the name "zener diode" came into widespread use before the avalanche effect was discovered. All diodes optimized for operation in the breakdown region are therefore still called zener diodes.

Fig. 7-1



ZV

ZrZV

+ZI

−

ZV ≅

Fig. 7-1 shows the schematic symbol and the current-voltage curve of a zener diode. Negligible reverse current flows until we reach the breakdown voltage VZ. In a zener diode, the breakdown has a very sharp knee, followed by an almost vertical increase in current. Note that the voltage is approximately constant, equal to VZ over most of the breakdown region. Data sheets usually specify the value of VZ at a particular knee current IZK which is beyond the knee (see Fig. 7-1). The power dissipation of a zener diode equals the product of its voltage and current. In symbols,

ZZZ IVP ⋅= As long as PZ is less than the power rating PZ(max), the zener diode will not be destroyed. Commercially available zener diodes have power ratings from 0.25 W to more than 50 W. Data sheets often specify the maximum current a zener diode can handle without exceeding its power rating. This maximum current is designated IZM (see Fig. 7-1). The relation between IZM and power rating is given by

Z

ZZM V

PI (max)= [7.1]

When a zener diode is operating in the breakdown region, a small increase in voltage produces a large increase in current. This implies that a zener diode has a small dynamic resistance (rZ, see Fig. 7-1). We can calculate this zener resistance by

ivrZ Δ

Δ=

The complete equivalent circuit of the zener diode in the zener region includes a small dynamic resistance (rZ) and dc battery equal to the zener potential (VZ), as shown in Fig. 7-2a. For all applications to follow, however, we shall assume as a first approximation that the external resistors are much larger in magnitude than the zener-equivalent resistor and that the equivalent circuit is simply the dc battery that equal to VZ as indicated in Fig. 7-2b. (a) (b)

Fig. 7-2



]10[11 VVD Z =

]10[22 VVD Z =

R

Ωk5+

_

iv ov

+

_

tπ2

π

iv+40

- 40

π2π t

2ZVov

1ZV

+10

-100

],3.3[11 SiVVD Z =

],8.6[22 SiVVD Z =

R

Ωk5+

_

iv ov

+

_

π2π t

ov+7.5

- 40

π2π

iv

t

+12

-12

0

12 TZ VV +

21 TZ VV +

+7.5

- 4

t1 t2 t3 t4

Zener Diode Applications: 1. AC Voltage Regulators (Limiters or Clippers): Two back-to-back zeners can be used as an ac regulator or a simple square-wave generator as shown in Examples 7-1 and 7-2 respectively. Example 7-1: Sinusoidal ac regulator, see Fig. 7-3.

Fig. 7-3 For t = 0 → t1 and t2 → π; D1 ON and D2 OFF => io vv = . For t = t1 → t2; D1 ON and D2 BREAKDOWN =>

12 TZo VVv += . For t = π → t3 and t4 → 2π; D2 ON and D1 OFF => io vv = . For t = t3 → t4; D2 ON and D1 BREAKDOWN =>

21 TZo VVv += . Example 7-2: Simple square-wave generator, see Fig. 7-4.

Fig. 7-4



+

_

+

_

+

_

V10

V20

V30

]10[11 VVD Z =

]20[22 VVD Z =

+_E V50

Ωk5R

iV

SR

LR+

−ZV

LIZI

SI

2. DC Voltage Reference: Two or more reference levels can be established by placing zener diodes in series as shown in Fig. 7-5. As long as Vi is grater than the sum of V and , both diodes will be in the breakdown state and the three reference voltages will be available.

1Z 2ZV

Fig. 7-5 3. DC Voltage Regulators: a. Fixed RL, Variable Vi: For the regulator circuit shown in Fig. 7-6;

L

ZL R

VI = (Constant) [7.2a]

ZSSi

LZKS

VRIV

III

+=

+=

(min)(min)

(min) [7.2b]

Fig. 7-6

ZSSi

LZMS

VRIV

III

+=

+=

(max)(max)

(max) [7.2c]



iV

SR

LR+

−ZV

LIZI

SI

iV

SR

LR+

−ZV

LIZI

SI

b. Fixed Vi, Variable RL: For the regulator circuit shown in Fig. 7-7;

S

ZiS R

VVI −= (Constant) [7.3a]

(min)(max)

(min)

L

ZL

ZMSL

IVR

III

=

−=

[7.3b]

Fig. 7-7

(max)(min)

(max)

L

ZL

ZKSL

IVR

III

=

−=

[7.3c]

c. Variable Vi and RL: For the regulator circuit shown in Fig. 7-8;

(min)(max)

(min)(min)

(max)(min)

L

ZL

S

ZiS

LSZK

RVI

RVV

I

III

=

−=

−=

[7.4a]

(max)(min)

(max)(max)

(min)(max)

L

ZL

S

ZiS

LSZM

RVI

RVV

I

III

=

−=

−=

[7.4b] Fig. 7-8



Ω600iV

SR

LR+

−ZV

S

Example 7-3: The reverse current in a certain 12 V, 2.4 W zener diode must be at least 5 mA to ensure that the diode remains in breakdown. The diode is to be used in the regulator circuit shown in Fig. 7-9, where Vi can vary from 18 V to 24 V. Find a suitable value for RS and the minimum rated power dissipation that RS should have.

Fig. 7-9 Solution:

mAIZK 5= and mAVPI

Z

ZZM 200

124.2=== .

AI L 0(min) = (when the switch S is open, Ω∞== (max)LL RR ).

mAR

VIL

ZL 20

60012

(min)(max) === (when the switch S is closed, Ω== 600(min)LL RR ).

(max)(min) LSZK III −= => => . 3

(min)3 1020105 −− ∗−=∗ SI mAI S 25(min) =

(min)(max) LSZM III −= => => . 010200 (max)3 −=∗ −

SI mAI S 200(max) =

Ω=∗−

=−

= − 24010251218

3(min)

(min)(max)

S

ZiS I

VVR .

Ω=∗−

=−

= − 60102001224

3(max)

(max)(min)

S

ZiS I

VVR .

Thus, we require Ω≤≤Ω 24060 SR . Choosing or calculating Ω=∗=⋅= 12024060(max)(min) SSS RRR .

mAR

VVI

S

ZiS 100

1201224(max)

(max) =−

=−

= .

( ) WRIP SSRS2.112010100

232(max) =∗∗=⋅≥ − .



Exercises: 1. Sketch the output (vo) for the circuit of Fig. 7-10 for the input shown (vi) when

|Vm| equal to (i) 5 V, and (ii) 15 V. iv

t

-Vm

+Vm

0π2

π

iV

SR

LR

LIZI

SI

+

−V6

R

],10[ SiVVD Z =

Ωk5

iv

+ +

_ _ov

Fig. 7-10

2. Design the voltage regulator circuit of Fig. 7-11 to maintain VL at 12 V across RL

with Vi that will vary between 16 and 20 V. That is, determine the proper value of RS and the power rating of the zener diode (PZ).

iV

SR

LR Ω240LV+

−

Fig. 7-11 3. The 6-V zener diode in Fig. 7-12 has a maximum rated power dissipated of

690 mW. Its reverse current must be at least 3 mA to keep it in breakdown. Find a suitable value for RS if Vi can vary from 9 V to 12 V and RL can vary from 500 Ω to 1.2 kΩ.

Fig. 7-12 4. If RS in Exercise 3 is set equal to its maximum permissible value, what is the

maximum permissible value of Vi? 5. If RS in Exercise 3 is set equal to its minimum permissible value, what is the

minimum permissible value of RL? 6. If RS in Exercise 3 is set equal to 120 Ω, what is the minimum rated power

dissipated that RS should have?

bai tap ve diode 1

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