b1011Machine Code

ENGR xD52Eric VanWyk

Fall 2012

Today

• Review Homework

• Translating Assembly to Machine Code

• Executing Machine Code

• Biggest Endian is Best Endian

Estimation

• Answers ranged from 3 seconds to many trillions of years, less than a cent to more than the cumulative global GDP for our lifetimes

• Lets use dimensional analysis to pull the range in a little bit…

Dimensional Analysis

• Target a specific unit with a series of translating scaling factors

• Make sure units cancel

• Super easy if everything is to the 1st power

Fast Approximations

• Translate scaling factors to powers of 10

• Add to multiply, subtract to divide

• Memorize your Log Tableslog(8) = 0.903 log(5) = 0.698log(3) = 0.477 log(2) = 0.301

Fast Approximations

• Translate scaling factors to powers of 10

• Add to multiply, subtract to divide

• Memorize your Log Tables8 -> E0.9 5 -> E0.73 -> E0.5 2 -> E0.3

Assumptions Made

• 1 billion tests per second– 10k to 10B is ok

• 20 Watts– 5 to 100 Watts is ok

• 10 cents per kWhr– Or whatever

Duration

• Number of Computations

• Computations / second

• Seconds / year

• Result in years

(2^64): 64*.3 : 10^19.2

10^9

3*10^7 = 10^7.5

19.2-9-7.5 = 2.7

Cost

• Number of Seconds

• Seconds / hour

• Kilowatts (0.020)

• Dollars per kWhr

• Dollars

10^10.2

10^3.6?

10^(1.3-3=-1.7)

10^-1

10.2-3.6+(-1.7)+(-1) = 3.9

Results

Time:

Math = 584.5 years

Estimate = 500

Error = -15%

Ratio = 0.85

Log Error = .06ish

Cost:

Math = 10,248 dollars

Estimate = 8,000 dollars

Error = -22%

Ratio = 0.78

Log Error = .1ish

Machine Code

• The actual bits sent to the processor

Encoding Limitations

• Designing an Encoding Scheme is a Game– Best use of limited space?– Favor some options over others

• Take Available Space and divide into “Fields”– Encoding within an Encoding (MOAR BOXES)– Fixed width per field– How many fields does IEEE-754 use?

Types of Fields

• Enumerations– No mathematical meaning, just enumerate options

• Signed / Unsigned– We know these well

• Biased– Mathematically offset by a constant

MIPS Code Encoding Formats• All instructions encoded in 32 bits• Register (R-type) instructions

• Immediate (I-type) instructions

• Jump (J-type) instructions

3130292827262524232221201918171615141312111009080706050403020100

OP RS RT RD SHAMT FUNCT

3130292827262524232221201918171615141312111009080706050403020100

OP RS RT 16 bit Address/Immediate

3130292827262524232221201918171615141312111009080706050403020100

OP 26 bit Address

(OP = 0,16-20)

(OP = any but 0,2,3,16-20)

(OP = 2,3)

Multiple Encoding Formats?

• Make the most of our limited resources

• How do we know which format?

• Why bother re-using encodings at all?

J-Type

• Used for Unconditional Jumps• Simplest MIPS encoding

• How do we encode “j 100”?

2: j (jump)3: jal (jump and link)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

OP 26 bit Address

J-Type

• Weirdness in the Address Field

• Bottom 2 bits are always ‘00’, so drop’em– Shift everything over by 2

• That’s only 28 effective bits…– Where are the other 4?– How does this limit us?– How do we compensate?

I-Type

• Used for operations with immediate (constant) operand

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

OP RS RT 16 bit Address/Immediate

04: beq05: bne06: blez07: bgtz08: addi09: addiu10: slti11: sltiu12: andi13: ori14: xori32: lb35: lw40: sb43: sw

Op1,L/S addr

Op2, Dest, L/S targ

I-Type

• Used for ops with an immediate operand

• One Op Field (Enumeration)

• Two register address fields

• One Signed/Unsigned field

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

OP RS RT 16 bit Address/Immediate

I-Type Examples

04: beq05: bne06: blez07: bgtz08: addi09: addiu10: slti11: sltiu12: andi13: ori14: xori32: lb35: lw40: sb43: sw

addi $t0, $t1, 100 # $t0 = $t1+1003130292827262524232221201918171615141312111009080706050403020100

beq $a0, $a1, -44 # if $a0 == $a1 GOTO (PC+4+FOO*4)3130292827262524232221201918171615141312111009080706050403020100

lw $t3, 12($t0) # $t3 = Memory[$t0+12]3130292827262524232221201918171615141312111009080706050403020100

I-Type Examples

04: beq05: bne06: blez07: bgtz08: addi09: addiu10: slti11: sltiu12: andi13: ori14: xori32: lb35: lw40: sb43: sw

addi $t0, $t1, 100 # $t0 = $t1+1003130292827262524232221201918171615141312111009080706050403020100

addi $t1 $t0 100

beq $a0, $a1, -44 # if $a0 == $a1 GOTO (PC+4+FOO*4)3130292827262524232221201918171615141312111009080706050403020100

beq $a1 $a0 -11

lw $t3, 12($t0) # $t3 = Memory[$t0+12]3130292827262524232221201918171615141312111009080706050403020100

lw $t0 $t3 12

I-Type Examples

04: beq05: bne06: blez07: bgtz08: addi09: addiu10: slti11: sltiu12: andi13: ori14: xori32: lb35: lw40: sb43: sw

addi $t0, $t1, 100 # $t0 = $t1+1003130292827262524232221201918171615141312111009080706050403020100

8 9 8 100

beq $a0, $a1, -44 # if $a0 == $a1 GOTO (PC+4+FOO*4)3130292827262524232221201918171615141312111009080706050403020100

4 5 4 -11

lw $t3, 12($t0) # $t3 = Memory[$t0+12]3130292827262524232221201918171615141312111009080706050403020100

0x23 8 11 12

R-Type• Used for 3 register ALU operations

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

OP RS RT RD SHAMT FUNCT00: sll02: srl03: sra04: sllv06: srlv07: srav08: jr24: mult26: div32: add33: addu34: sub35: subu36: and37: or38: xor39: nor42: slt

00(10-13 for FP)

Shift amount(0 for non-shift)

add $8, $9, $10 # $8 = $9+$10

sll $8, $9, 6 # $8 = $9<<6

sllv $8, $9, $10 # $8 = $9<<$10

Op2Op1 Dest

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

00 9 10 8 0 32

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

00 X 9 8 6 00

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

00 10 9 8 0 04

Decoding

• The Instruction Decode Unit translates the encoded Machine Code into control signals

• Lets (begin to) figure out the Decode Unit by creating (part of) its truth tables

• To finish, we’d apply Boolean Law and push the design all the way through to gates

Control SignalsFunc 100000 100010 N/A N/A N/A N/A

Op 000000 000000 100011 101011 000100 000010

add sub lw sw beq j

RegDst

ALUSrc

MemToReg

RegWr

MemWr

Branch

Jump

ALUCntrl Add Sub Add Add Sub X

26

Our Single Cycle CPU

SignExtnd

WrEn AddrDin DoutData

Memory

InstructionFetchUnit

Rs Rt Rs Rt Rd Imm16

imm16

Instructions[31:0]

[25:21]

[20:16]

[15:11]

[15:0]

BranchJump

ALUSrc

RegDst

Rd Rt

ALUcntrl

Aw Aa Ab DaDw Db Register

WrEn File RegWr

MemWr MemToRegZero

Control SignalsFunc 100000 100010 N/A N/A N/A N/A

Op 000000 000000 100011 101011 000100 000010

add sub lw sw beq j

RegDst 1 1 0 X X X

ALUSrc 0 0 1 1 0 X

MemToReg

0 0 1 X X X

RegWr 1 1 1 0 0 0

MemWr 0 0 0 1 0 0

Branch 0 0 0 0 1 X

Jump 0 0 0 0 0 1

ALUCntrl Add Sub Add Add Sub X

Design Your Own Encodings

• Memorizing MIPS encodings is super fun, but lets make up our own instead!

• Use the single cycle cpu as a starting point– Modify as necessary to suit your goals

• Come up with an interesting tweak to the design and see it all the way through

Design Your Own Encodings

• Ideas:– What can you fit into a 16 bit Machine Code?– Can you add support for ARM-like shifting?– What about variable length encodings?

• Tools / Tweaks:– How many Registers do you support?– Are some ops redundant?– Nothing is sacred today

Design Your Own Deliverables

• 2 sentences on your idea• Description of supported operations• Description of encoding styles• White Board Schematic of modified CPU• Assemble, Encode, Decode a small example

program to highlight your idea

31

Our Single Cycle CPU

SignExtnd

WrEn AddrDin DoutData

Memory

InstructionFetchUnit

Rs Rt Rs Rt Rd Imm16

imm16

Instructions[31:0]

[25:21]

[20:16]

[15:11]

[15:0]

BranchJump

ALUSrc

RegDst

Rd Rt

ALUcntrl

Aw Aa Ab DaDw Db Register

WrEn File RegWr

MemWr MemToRegZero