aztec pc scope preliminary design review fall 2006 michael masonjed brown andrew youngsjosh price
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Aztec PC Scope
Preliminary Design Review
Fall 2006
Michael Mason Jed BrownAndrew Youngs Josh Price
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Aztec PC Oscilloscope
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Project Description
An Oscilloscope that will interface with a PC2 Initial Modes Trigger Based - Once the
programmable conditions have been met the scope will pass information to the ram.
Free Flow – As soon as enabled it will pass the data to the ram and potentially to the PC.
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Purpose
To provide a cost effective oscilloscope Make the scope affordable to a wider range
of customers.
Facilitate use of a PC in lab testing Allow students and engineers to use the PC
to capture data for storage or use in reports.
Design for possible extensions in the future The concept is easily expandable.
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Features
User Defined Sample Rate.Free flow ModeDefinable trigger ModeData upload to PCToggle Impedance (50 Ohm/100 Ohm)Graphical User Interface
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Basic Flow
Scope Signal Conditioner Analog/Digital converter FPGA Memory MC USB
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Block Diagram
Scope
S C
A/D Spartan-3EHW-SPAR3E-SK-US
SDRAM
M C USBControlle
r
MUX
eeprom
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Scope & Signal Converter
One ChannelSlow speed with possibilities to upgradeSignal converter Needed to scale the signal to < 5.0 volts for
the A/D converter.
Multiplexor is for future additions to the scope Additional channels would require additional
A/D converters. Design should make adding channels simple.
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Input Signal Issues
Noise
DC Offset
Signal Amplitude
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Signal Conditioning Solutions
Filtering
AC/DC Coupling
Signal Amplification
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Filtering
Bessel Low Pass Filter
Notch Filter
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AC/DC Coupling
DC Coupling
AC Coupling
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Signal Amplification
Pre-Amplification Variable High Bandwidth Flat Frequency Response
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Analog to Digital Converter
Single serial input, 8-bit parallel outputMaximum Conversion Rate of 40 Megasamples/second
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Microcontroller
Initially use Siemens 805116-bit addressable, 8-bit data, 64kB accessible external RAMBasic control unit for enables, external peripherals (LCD, SRAM, EEPROM, ADC)Will interface with the computer for sending data and receiving user commands (interface with RS232 and USB).Possible upgrade if time permits
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Microcontroller Block Diagram
Spartan-3E
8051
EEPROM
SRAM
LCD
Serial Interface
PC/GUI
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AC/DC Converter
Utility connected (120 VAC 60 Hz) to board power (+5 VDC)DC/DC on board power conversion can be accomplished through level shifters, voltage regulators.
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RS232 Level Converter
A standard serial interfacing for PC, RS232C, requires negative logic, i.e., logic '1' is -3V to -12V and logic '0' is +3V to +12V
2-channel RS232C port and requires external
10uF capacitors
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USB ControllerFirst Serial, then USBDLP-2232M-G - Dual USB UART/FIFOUART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity Transfer Data Rate 300 to 1 Mega Baud (RS232)
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Spartan-3E FPGA Board
Xilinx Devices: Spartan-3E (XC3S500E-4FG320C) CoolRunner™-II (XC2C64A-5VQ44C) Platform Flash (XCF04S-VO20C)
Clocks: 50 MHz crystal clock oscillator Memory 128 Mbit Parallel Flash 16 Mbit SPI Flash 64 MByte DDR SDRAM
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Spartan-3E
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Spartan-3E FPGA Board cont.
Connectors and Interfaces Ethernet JTAG USB download Two 9-pin RS-232 Serial Port, PS/2- style mouse/keyboard port rotary encoder with push button Four Slide Switches Eight Individual LED Outputs Four Momentary-Contact Push Buttons 100-Pin hirose Expansion Connection Ports Three 6-pin expansion connectors
Display: 16 character - 2 Line LCD
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Risks and Contingency Plan
Use the serial ports on the FPGA board, or microcontroller instead of the USB interface.Decrease capabilities of the graphing software.Use FPGA board interfaces to program triggers and sampling rate instead of USB interface.
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Endless Possibilities
Wireless probe to gather the data.Advanced User Interface with measurement and display controls.Multiple channels on the scope.
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Labor & Responsibilities
Mike – Software, USB (Windows Drivers)Jed – Software, FPGA (verilog)Andrew – Signal Conditioning, A/DJosh - Power, Microcontroller, RS232ALL – PCB
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Schedule
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Questions?