avr architecture and assembly...

AVR Architecture

and Assembly

LanguageLecture# 03

Microprocessor System and Interfacing

Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad

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Class Discussion

Any Class Issues ?

Course Registration etc

One by one Please !!!!


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Lecture Review

Hardvard vs von Neumann Architecture

Microcontroller vs Microprocessor

AVR Microcontroller Architecture

General Purpose Registers

The AVR Data Memory

Instructions with Data Memory

LDI: Copies data in GPRs

ADD: Add numbers in two GPRs

LDS: Copy one byte from data memory to GPR

STS: Copy GPR value to data memory


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Lecture Objectives

AVR Microcontroller Architecture

Assembly Language Instructions


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IN from I/O Location – IN

Load one byte from an I/O register to the GPR

IN Rd, A

Rd: GPR from 0 to 31

A is between 0 to 63

Example

IN R20, 0x16

Instruction will copy the contents of location 0x16 into R20


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IN R20, 0x16

This will copy contents

of location 0x16 to

R20

We can also use their

names instead of

address locations

IN R20, PINB

Class Exercise 1


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Add the contents of PIND and PINB and store the result in location

0x300

IN R1, PIND ; load R1 from PIND

IN R2, PINB ; Load R2 with PINB

ADD R2, R1 ; R2 = R1 + R2

STS 0x300, R2 ; store R2 to data space location 0x300


IN vs LDS

IN is faster as it takes 1 clock cycle while LDS takes 2 clock

cycles

IN is 2 byte instruction, acquires less code space while LDS is

4 bytes instruction

IN supports the name of IO registers

IN is available in all AVRs while LDS is not

Using IN we can access only IO memory while using

LDS we can access all data memory


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OUT to I/O Location – OUT Store one byte from GPR to IO register

OUT A, Rd

Rd: GPR from 0 to 31

A is between 0 to 63

Example

LDI R20, 0x16

OUT PORTD, R20

We cannot copy an immediate value to an IO register

Repeat a loop – JMP

JMP is used to repeat a loop

Example

AGAIN: IN R16, PINB

OUT PORTC, R16

JMP AGAIN


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Copy data in GPRs - MOV Copy data in GPRs

MOV Rd, Rr

Copy Rr to Rd

Example

MOV R10, R20

INC Increments the contents of GPR by 1

DEC Decrements the contents of GPR by 1

SUB Subtracts two registers

SUB Rd, Rr ; Rd = Rd - Rr

COM Complement the contents of a register

COM Rd ; Complements the contents of Rd


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Class Exercise 2


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Take input from PINC, Subtract 9 from it. Take input from PINA, and

increment the input value by 1. Add both values together and

then complement the result. Store the final result on location

0x302.

IN R1, PINC ; load R1 from PINC

LDI R16, 0x09 ; load 0x09 in R2

SUB R1, R16 ; R1 = R1 – R16

IN R3, PINA ; load R3 from PINA

INC R3 ; Increment R3 by 1

ADD R1, R3 ; R1 = R1 + R3

COM R1 ; Decrement R1 by 1

STS 0x302, R1 ; store final result on 0x302

AVR Status Register

C: Whenever there is carry out from D7 in ADD/SUB instructions

Z: Arithmetic/logic operation, Z = 1 if results is zero and vice versa

N: D7 is sign bit, N = 0 when D7 of result is zero, 1 otherwise

V: When signed number operation is too large, overflow to D7

S: N ⊕ V, For signed tests

H: Half Carry Flag, carry from D3 to D4, used for BCD operation

T: Transfer bit (Set Clear Bit)

I: Global Interrupt Enable/Disable Flag


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AVR Data Format and Directives


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Data Format

Decimal

(2510, 1010, 34510, 103310)

Binary

(110012, 10102, 1010110012, 100000010012 ,100000010012)

HexaDecimal

(19, A, 159, 409)

ASCII code



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Compiler Directives

.EQU / .SET

Defines a constant value or a fixed address

.EQU COUNT = 25

The value assigned by .SET can be changed later

.ORG

Used to indicate the starting of an address

.INCLUDE

This tells the AVR assembler to include contents of certain

file to current program

AVR Assembly Language Programming


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Structure of Assembly Language

[label:] mnemonic [operands] [;comment]

label: refers to a line of code by name

mnemonics and operands: perform the real work

comment: are used to make program understandable

Program Counter and Program ROM Space


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Program Counter

Used to point to the address of the next instruction to be

executed.

Whenever CPU fetches the opcode from ROM, the

counter is incremented.

14-bit counter can access memory of 16K (214 = 16K)

Home Task


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Read topic “Executing a program

instruction by instruction” by using a

sample program



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Harvard Architecture



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Harvard Architecture

Separate buses for the code and data memory

Program Bus for access to program flash ROM

Data bus for bringing data to CPU

Example

LDS R20, 0x90

CPU puts 0x90 on address bus

SRAM puts contents of location 0x90 on data bus

RISC Architecture

All instructions possible are available on CPU

Huge cost

Some instructions are barely used

Good portion of transistors are used by instruction decoder

Complex Instruction Set Computer (CISC)

Reduced Instruction Set Computer (RISC)


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Features of RISC Architecture

A fixed instruction set

Variable instruction set makes the task of instruction decoder

difficult

Large number of registers

RISC architecture has a large number of registers

It avoids the need of large stack to store parameters

Small instruction set

Only basic instructions are available

ADD, SUB, MUL, LOAD, STORE, AND, OR, EOR, CALL, JMP etc


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Fast execution

Almost 95% instructions are executed with only one clock cycle

Separate buses for data and code

A set of buses to carry data (operands) in and out of CPU

Address busses for accessing the data

Set of busses to carry opcodes

Address busses to access the opcodes


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Instruction hardware

Hardwire method is used to implement the instruction

Only 10% of transistors are used

Load/store architecture

Instructions can only load from external memory into registers

Then arithmetic operations are performed

No direct way of doing arithmetic and logic operations


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Class Exercise 3


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Write a Program to copy data from PINA,

add the same value 5 times and copy

the result to PORTC

Lecture Review

AVR data Memory

IN, OUT, MOV, INC, DEC, SUB, COM

AVR Status Register





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