8/13/2019 avlsi1

1/20

PARALLEL PROCESSING An Introduction

8/13/2019 avlsi1

2/20

COURSE

ILP

Pipelined

VLIW DSP Architectures

Superscalar

DLP

SIMD

Associative & Neural Architectures

Systolic Architectures

Vector Architectures

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 2

8/13/2019 avlsi1

3/20

COURSE

MIMD

Multi-threaded

Distributed memory MIMD Shared memory MIMD

Case Studies

Simulation based Performance Evaluation Studies

MIPSit, SimpleScalar

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 3

8/13/2019 avlsi1

4/20

EVALUATIONEC

No.

Evaluation

Component

Duration

(min)

Weightage

(%)

Nature of

Component

1 Test I 60 20 Closed Book

2 Test II 60 20 Closed Book3 Assignment &

Case Studies,

Class Room

Interactions

----- 20

4 Comprehensive 180 40 Closed/Open

Book

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 4

8/13/2019 avlsi1

5/20

SPEED UP

Deeply pipelined machines

Many instructions/cycle

Out-of-order execution of instructions

Aggressive branch prediction techniques

2010 1 billion transistors clock frequencies >10GHz

ADAVNCEDVLSI AECHITECTURES K.R.ANUPAMA 5

8/13/2019 avlsi1

6/20

ARCH, IMPLEMENTATION & REALIZATION

Architecture

ISA

Functional level behavior of processorImplementation

Micro-architecture

Logic structure that implements the arch

Realization Physical Implementation

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 6

8/13/2019 avlsi1

7/20

ISA

Contract between software and hardware

Multiple machines can implement ISA

Advantage program portability

Microprocessor design starts with ISA

ISA producesmicro architecture

Micro architecture has to be rigorously verified

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 7

8/13/2019 avlsi1

8/20

ISA

Development is very slow

ISAs varied

No. of operands Implied operands

Operands may be stored in stack

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 8

8/13/2019 avlsi1

9/20

CONTRACT BETWEEN H/W & S/W

SPECIFICATIONS OFMICROPROCESSOR DESIGN

ISA functions

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 9

8/13/2019 avlsi1

10/20

DYNAMIC STATIC INTERFACE

Separates what is done

Compile Time

Statically

At run time

Dynamically

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 10

8/13/2019 avlsi1

11/20

DSI

Architecture

Program (Software)

Machine (Hardware)

Compiler

Complexity

Hardware

Complexity

Exposed to

software

Exposed to

hardware

Static

Dynamic

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 11

8/13/2019 avlsi1

12/20

DSI

DEL CISCHLL

DSI1

DSI2

DSI3

Hardware

VLIW RISC

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 12

8/13/2019 avlsi1

13/20

WHAT IS PARALLEL COMPUTING ? SERIAL

COMPUTINGTraditionally, software has been written forserialcomputation:

To be run on a single computer having a single Central ProcessingUnit (CPU)

A problem is broken into a discrete series of instructions

Instructions are executed one after another

Only one instruction may execute at any moment in time

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 13

8/13/2019 avlsi1

14/20

WHAT IS PARALLEL COMPUTING ? SERIAL

COMPUTINGProblem

CPU

T1T2T3TN

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 14

8/13/2019 avlsi1

15/20

WHAT IS PARALLEL COMPUTINGIn the simplest sense -parallel computing is the simultaneous use of multiplecompute resources to solve a computational problem:

To be run using multiple CPUs

A problem is broken into discrete parts that can be solved concurrently

Each part is further broken down to a series of insts Insts from each part execute simultaneously on different CPUs

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 15

8/13/2019 avlsi1

16/20

WHAT IS PARALLEL COMPUTING

Problem 1

Problem 2

Problem 3

Problem 4

CPU 1

CPU 2

CPU 3

CPU 4

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 16

8/13/2019 avlsi1

17/20

PARALLEL COMPUTING

The compute resources might be:

A single computer with multiple processors

An arbitrary number of computers connected by a network A combination of both

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 17

8/13/2019 avlsi1

18/20

PARALLEL COMPUTING

The computational problem should be able to:

Be broken apart into discrete pieces of work that can

be solved simultaneously Execute multiple program instructions at any moment in

time

Be solved in less time with multiple compute resourcesthan with a single compute resource.

ADAVNCEDVLSI AECHITECTURES K.R.ANUPAMA 18

8/13/2019 avlsi1

19/20

AMDAHLS LAW

Ttotal = 1

Timproved [ Ttotal - Tcomponent ]+ Tcomponentn

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 19

8/13/2019 avlsi1

20/20

APPLNS THAT USE PARALLEL PROCESSING

Databases, data mining

Oil exploration

Web search engines, web based business services Medical imaging and diagnosis

Pharmaceutical design

Management of national and multi-national corporations

Financial and economic modeling

Advanced graphics and virtual reality, particularly in theentertainment industry

Networked video and multi-media technologies

Collaborative work environments

ADAVNCED VLSI AECHITECTURES K.R.ANUPAMA 20