Avionic Bus Protocol Controller “DigiSxt” Technical Data Sheet:

We at Digeratti Systems develops Mil-Std-1553B and ARINC429 protocol based

ISA/PCI interface Boards with Avionic Bus based Simulator software as development

tool for any Military Aircraft Sub System Development. Currently we have come out

with In-House Development of Mil-Std-1553B and ARINC429 protocol modules for

both protocols. Digi-1553-Core developed for all modes of the bus Viz., Bus Controller,

Remote Terminal and Monitor Terminal, and Digi-ARINC429-Core is being integrated

with Single Transmitter and Receiver Channels. These cores are developed using VHDL

language, synthesized and implemented on platform FPGA from M/s Xilinx. Also

The Avionic bus interface modules having BC/RT/MT modes as “IP Core” is embedded

along with SuMMIT-XTE controller being selected as Front-end Host Interface

architecture for Data Bus Interface, and extensively tested with SuMMIT-XTE controller

from M/s UTMC, and Transmitter and receiver modules in our ARINC429 core is being

tested in loop back and then with TS68C429A controller in our PCI Interface board.

The development was aimed at gaining domain knowledge and in-house development of

all the modes in Avionic Bus Protocols, there by provide a single point access as low cost

“Technology development center” having wide spectrum of Military Aircraft

communication protocol solution provider from IP core/Chip compatible/Interface Board

having GUI for PC platform.

Most of the Mil-Std-1553B Data Bus Simulators in Labs are being used with Mil grade

protocol controller for simulating the Avionic Bus based environment on ground. The

Chip level DigiSxt (Digiratti SuMMIT-XTE Controller) interface board solution will

give cost effective solution for ground based equipment integration, there by saving

much needed foreign exchequer.

MIL-STD-1553B Bus Overview:

The MIL-STD-1553B bus is a 1 Mb/s Time-Multiplexed Serial Data Bus differential

serial bus used in military and space equipment. It is comprised of multiple redundant bus

connections and communicates at 1MB per second.

The bus has a single active bus controller (BC) and up to 31 remote terminals (RTs). The

BC manages all data transfers on the bus using the command and status protocol. The bus

controller initiates every transfer by sending a command word and data if required. The

selected RT will respond with a status word and data if required.

The 1553B command word contains a five-bit RT address, transmit or receive bit, five-bit

sub-address and five-bit word count. This allows for 32 RTs on the bus, but only 31 RTs

may be connected, since the RT address (31) is used to indicate a broadcast transfer, i.e.

all RTs should accept the following data. Each RT has 30 sub-addresses reserved for data

transfers. The other two sub-addresses (0 and 31) are reserved for mode codes used for

bus control functions. Data transfers contain up to (32) 16-bit data words. Mode code

command words are used for bus control functions such as synchronization.

Digi-1553-Core Top Module:

Digi-1553-Core is being configured on SPARTAN II device having 200K Gates density

with 32K X 16 bits on board Static RAM for 1553 bus data storage.1553B bus being

connected through 3.3V Dual Trans-Receiver having 1553 Encoder/ Decoder front end.

The system works on 24Mhz System Clock input from the main board, and on board

DLL generate 12Mhz clock for internal state machine operation. There are two major

counters for getting Minor Frame Counter with a resolution of 64 Micro Seconds and

REG counter to get 20 mil seconds event for RAM memory initial 32 Location reading

for initiating any host based event processing. Also 1553 bus command/status/data bus

data capture based on the mode in which the device is configured.

Digi-1553-Core Archtecture:

The block level organization of the different modules to handle the interfaces as well as

protocol stack in core Digi-1553-Core onto FPGA is as shown below.

: Shaded Blocks are Hardware Modules and not part of Digi-1553-Core.

Register File architectures for all modes having initial 32 location holds the Control,

Status, Pointers for Command Block/ Monitor Block / Descriptor Block Area in RAM

memory. 20 Mili second read cycle for this Register area keeps the Protocol engine

updated with Host Application.

The design being plugged as 139pin PGA device on our PCI / ISA interface board for

live Mil-Std-1553B based Protocol logic validation.

Bus

A

Bus

B

Host [ Address Data Control ] Bus

BC Protocol

Handler

Host Interface Module

RAM Interface Module

RT Protocol

Handler

MT Protocol

Handler

DigiSxt

Controller

Interface

Module

Register

File

Handler

1553

Serial

Bus

Handler

32K X 16 Bit

SRAM

Dual

Channel

Mil-Std-1553

Transceiver

With

Encoder

and

Decoder

Channel

A

Transfmr

Channel

B

Transfmr

System Bus Controller (SBC) Module : Flexible command block chaining through Op Code architecture for Command Block

creation and execution.64 micro second Minor Frame Counter for command block

execution.

System Remote Terminal (SRT) Module :

16-bit read/write time-tag with user-defined resolution. Subaddress data buffering. Ping

pong mode of data block storage, separate sub address for Broad cast as per Notice II.

Also subaddress data storage includes Indexed / Circular mode.

Interrupt features with Interrupt Log creation, sub address accessed, broad cast data

received, index reached to zero options have been implemented.

System Monitor Terminal (SMT) Module:

Monitor Terminal is a full-featured MILSTD-1553B bus monitor designed to monitor all

or selected remote terminals on the bus, requiring little host intervention. Each message

transaction generates a Message Information Word. This information helps determine

message validity and remote terminal health. The Message Information Word is stored in

Monitor block indexed memory along with message data words.

We in DigiSxt MT module provides 32bits Counter having 64 Micro Seconds timer in the

Monitor Command Block last two words, instead of 16 bits 64 Micro Seconds one word

from SuMMIT-XTE controller, there by a total time of 76 Hours data logging can be

carried out for a given simulated Monitor session without any software based timer

counter for any long monitor session.

Digi-1553-Core Verification and Compliance:

The Mil-Core1553B functionality has been verified in each simulation mode and

integrated and tested on the PCI hardware Interface card. To fully verify compliance, the

core has been implemented on an DigiSxt Unit with Spartan II FPGA, connected to

external transceivers and memory.

Digi-1553-Core Test Unit:

In House developed and being used in many development center for Simulating Avionic

bus based nodes in their Labs are being used as “DigiSxt” Controller Testing Hardware.

The dual Channel PCI bus Interface Board with Windows 98/2K/XP platform having

VC++ based general purpose GUI front end for Application integration for any mode of

operation on our PCI interface Board. Mil-Std-1553B and ARINC-429 protocol based

ISA and PCI Interface Boards having populated for 1553B bus with DigiSxt Controller

photos:

Conclusion:

On request we can arrange for demo for our Interface card with our Mil-1553B IP Core

working in tandem with other Summit-XTE based Controller.

We can provide the low cost solution for existing Summit-XTE based interface boards

with user application in operation, with no extra cost the new DigiSxt will be integrated

with the interface board to work in existing customer application.